|Introduced||1986 (1996 PA-RISC 2.0)|
|Branching||Compare and branch|
|Extensions||Multimedia Acceleration eXtensions (MAX), MAX-2|
|Floating point||32 64-bit (16 64-bit in PA-RISC 1.0)|
PA-RISC is an instruction set architecture (ISA) developed by Hewlett-Packard. As the name implies, it is a reduced instruction set computer (RISC) architecture, where the PA stands for Precision Architecture. The design is also referred to as HP/PA for Hewlett Packard Precision Architecture.
The architecture was introduced on 26 February 1986, when the HP 3000 Series 930 and HP 9000 Model 840 computers were launched featuring the first implementation, the TS1.
PA-RISC has been succeeded by the Itanium (originally IA-64) ISA, jointly developed by HP and Intel.HP stopped selling PA-RISC-based HP 9000 systems at the end of 2008 but supported servers running PA-RISC chips until 2013.
In the late 1980s, HP was building four series of computers, all based on CISC CPUs. One line was the IBM PC compatible Intel i286-based Vectra Series, started in 1986. All others were non-Intel systems. One of them was the HP Series 300 of Motorola 68000-based workstations, another Series 200 line of technical workstations based on a custom silicon on sapphire (SOS) chip design, the SOS based 16-bit HP 3000 classic series, and finally the HP 9000 Series 500 minicomputers, based on their own (16 and 32-bit) FOCUS microprocessor.
Precision Architecture is the result of what was known inside Hewlett-Packard as the Spectrum program.HP planned to use Spectrum to move all of their non-PC compatible machines to a single RISC CPU family.
The first processors were introduced in 1986. It had thirty-two 32-bit integer registers and sixteen 64-bit floating-point registers. The number of floating-point registers was doubled in the 1.1 version to 32 once it became apparent that 16 were inadequate and restricted performance. The architects included Allen Baum, Hans Jeans, Michael J. Mahon, Ruby Bei-Loh Lee, Russel Kao, Steve Muchnick, Terrence C. Miller, David Fotland, and William S. Worley.
The first implementation was the TS1, a central processing unit built from discrete transistor–transistor logic (74F TTL) devices. Later implementations were multi-chip VLSI designs fabricated in NMOS processes (NS1 and NS2) and CMOS (CS1 and PCX). – the 930 and 950, commonly known at the time as Spectrum systems, the name given to them in the development labs. These machines ran MPE-XL. The HP 9000 machines were soon upgraded with the PA-RISC processor as well, running the HP-UX version of UNIX.They were first used in a new series of HP 3000 machines in the late 1980s
Other operating systems ported to the PA-RISC architecture include Linux, OpenBSD, NetBSD and NeXTSTEP.
An interesting aspect of the PA-RISC line is that most of its generations have no Level 2 cache. Instead large Level 1 caches are used, formerly as separate chips connected by a bus, and now integrated on-chip. Only the PA-7100LC and PA-7300LC had L2 caches. Another innovation of the PA-RISC was the addition of vectorized instructions (SIMD) in the form of MAX, which were first introduced on the PA-7100LC.
Precision RISC Organization, an industry group led by HP, was founded in 1992, to promote the PA-RISC architecture. Members included Convex, Hitachi, Hughes Aircraft, Mitsubishi, NEC, OKI, Prime, Stratus, Yokogawa, Red Brick Software, and Allegro Consultants, Inc..
The ISA was extended in 1996 to 64 bits, with this revision named PA-RISC 2.0. PA-RISC 2.0 also added fused multiply–add instructions, which help certain floating-point intensive algorithms, and the MAX-2 SIMD extension, which provides instructions for accelerating multimedia applications. The first PA-RISC 2.0 implementation was the PA-8000, which was introduced in January 1996.
|Model||Marketing name||Year||Frequency [MHz]||Memory Bus [MB/s]||Process [μm]||Transistors [millions]||Die size [mm²]||Power [W]||Dcache [kB]||Icache [kB]||L2 cache [MB]||ISA||Notes|
|Mako||PA-8800||2003||800–1000||6400||0.13||300||361||?||768/core||768/core||0 or 32||2.0|
|Shortfin||PA-8900||2005||800–1100||6400||0.13||?||?||?||768/core||768/core||0 or 64||2.0|
Alpha, originally known as Alpha AXP, is a 64-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC), designed to replace their 32-bit VAX complex instruction set computer (CISC) ISA. Alpha was implemented in microprocessors originally developed and fabricated by DEC. These microprocessors were most prominently used in a variety of DEC workstations and servers, which eventually formed the basis for almost all of their mid-to-upper-scale lineup. Several third-party vendors also produced Alpha systems, including PC form factor motherboards.
Itanium is a family of 64-bit Intel microprocessors that implement the Intel Itanium architecture. Intel marketed the processors for enterprise servers and high-performance computing systems. The Itanium architecture originated at Hewlett-Packard (HP), and was later jointly developed by HP and Intel.
A minicomputer, or colloquially mini, is a class of smaller computers that was developed in the mid-1960s and sold for much less than mainframe and mid-size computers from IBM and its direct competitors. In a 1970 survey, The New York Times suggested a consensus definition of a minicomputer as a machine costing less than US$25,000, with an input-output device such as a teleprinter and at least four thousand words of memory, that is capable of running programs in a higher level language, such as Fortran or BASIC.
A reduced instruction set computer, or RISC, is a computer instruction set that allows a computer's microprocessor to have fewer cycles per instruction (CPI) than a complex instruction set computer (CISC).
HP-UX is Hewlett Packard Enterprise's proprietary implementation of the Unix operating system, based on Unix System V and first released in 1984. Recent versions support the HP 9000 series of computer systems, based on the PA-RISC instruction set architecture, and HP Integrity systems, based on Intel's Itanium architecture.
Very long instruction word (VLIW) refers to instruction set architectures designed to exploit instruction level parallelism (ILP). Whereas conventional central processing units mostly allow programs to specify instructions to execute in sequence only, a VLIW processor allows programs to explicitly specify instructions to execute in parallel. This design is intended to allow higher performance without the complexity inherent in some other designs.
IA-64 is the instruction set architecture (ISA) of the Itanium family of 64-bit Intel microprocessors. The basic ISA specification originated at Hewlett-Packard (HP), and was evolved and then implemented in a new processor microarchitecture by Intel with HP's continued partnership and expertise on the underlying EPIC design concepts. In order to establish what was their first new ISA in 20 years and bring an entirely new product line to market, Intel made a massive investment in product definition, design, software development tools, OS, software industry partnerships, and marketing. To support this effort Intel created the largest design team in their history and a new marketing and industry enabling team completely separate from x86. The first Itanium processor, codenamed Merced, was released in 2001.
Tandem Computers, Inc. was the dominant manufacturer of fault-tolerant computer systems for ATM networks, banks, stock exchanges, telephone switching centers, and other similar commercial transaction processing applications requiring maximum uptime and zero data loss. The company was founded by Jimmy Treybig in 1974 in Cupertino, California. It remained independent until 1997, when it became a server division within Compaq. It is now a server division within Hewlett Packard Enterprise, following Hewlett-Packard's acquisition of Compaq and the split of Hewlett Packard into HP Inc. and Hewlett Packard Enterprise.
The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions (code) or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is being increasingly used in conventional von Neumann architecture processors for security reasons.
The HP 3000 series is a family of minicomputers from Hewlett-Packard. It was designed to be the first minicomputer with full support for time-sharing in the hardware and the operating system, features that had mostly been limited to mainframes to that point.
HP 9000 is a line of workstation and server computer systems produced by the Hewlett-Packard Company (HP). The native operating system for almost all HP 9000 systems is HP-UX, which is based on UNIX System V. The HP 9000 brand was introduced in 1984 to encompass several existing technical workstation models previously launched in the early 1980s.
The Hewlett-Packard FOCUS microprocessor, launched in 1982, was the first commercial, single chip, fully 32-bit microprocessor available on the market. At this time, all 32-bit competitors used multi-chip bit-slice-CPU designs. The FOCUS architecture was used in the Hewlett-Packard HP 9000 Series 500 workstations and servers. It was a stack architecture, with over 220 instructions, a segmented memory model, and no general purpose programmer-visible registers. The design of the FOCUS CPU was richly inspired by the custom silicon on sapphire (SOS) chip design, HP used in their 16-bit HP 3000 series machines.
PRISM was Apollo Computer's high-performance CPU used in their DN10000 series workstations. It was for some time the fastest microprocessor available, a high fraction of a Cray-1 in a workstation. Hewlett Packard purchased Apollo in 1989, ending development of PRISM, although some of PRISM's ideas were later used in HP's own HP-PA Reduced instruction set computer (RISC) and Itanium processors.
Hombre is a RISC chipset for the Amiga, designed by Commodore, which was intended as the basis of its next generation game machine called CD64 and a 3D accelerator PCI card. Hombre was canceled along with the bankruptcy of Commodore International.
The HP Superdome is a high-end server computer developed and produced by Hewlett Packard Enterprise. The latest version of product, "Superdome 2" was introduced in 2010. Superdome 2 scales from 2 to 32 sockets and 4 TB of memory. When introduced in 2000, the Superdome used PA-RISC processors. Since 2002, there has been another version of the machine based on Itanium 2 processors, marketed in parallel as the HP Integrity Superdome. The classic PA-RISC Superdome was subsequently rebranded to HP 9000 Superdome. The predecessor to the Superdome was the HP V-Class.
The PA-8000 (PCX-U), code-named Onyx, is a microprocessor developed and fabricated by Hewlett-Packard (HP) that implemented the PA-RISC 2.0 instruction set architecture (ISA). It was a completely new design with no circuitry derived from previous PA-RISC microprocessors. The PA-8000 was introduced on 2 November 1995 when shipments began to members of the Precision RISC Organization (PRO). It was used exclusively by PRO members and was not sold on the merchant market. All follow-on PA-8x00 processors are based on the basic PA-8000 processor core.
The R2000 is a 32-bit microprocessor chip set developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture (ISA). Introduced in January 1986, it was the first commercial implementation of the MIPS architecture and the first commercial RISC processor available to all companies. The R2000 competed with Digital Equipment Corporation (DEC) VAX minicomputers and with Motorola 68000 and Intel Corporation 80386 microprocessors. R2000 users included Ardent Computer, DEC, Silicon Graphics, Northern Telecom and MIPS's own Unix workstations.
The PA-7200 – also known as PCX-T', code-named Thunderbird' –, is a microprocessor that implements the PA-RISC 1.1 instruction set architecture (ISA) developed by Hewlett-Packard (HP). It was introduced in early 1995, debuting in systems from HP. The PA-7200 was not sold openly and the only third-party users were Convex Computer and Stratus Computer, both members of the Precision RISC Organization (PRO). It was developed for small multiprocessing systems with two or four microprocessors. The microprocessor was first described at the Compcon and IEEE International Solid-State Circuits Conference (ISSCC) conferences.
The PA-7100LC is a microprocessor that implements the PA-RISC 1.1 instruction set architecture (ISA) developed by Hewlett-Packard (HP). It is also known as the PCX-L, and by its code-name, Hummingbird. It was designed as a low-cost microprocessor for low-end systems. The first systems to feature the PA-7100LC were introduced in January 1994. These systems used 60 and 80 MHz parts. A 100 MHz part debuted in June 1994. The PA-7100LC was the first PA-RISC microprocessor to implement the MAX-1 multimedia instructions, an early single instruction, multiple data (SIMD) multimedia instruction set extension that provided instructions for improving the performance of MPEG video decoding.
The PA-7100 is a microprocessor developed by Hewlett-Packard (HP) that implemented the PA-RISC 1.1 instruction set architecture (ISA). It is also known as the PCX-T and by its code-name Thunderbird. It was introduced in early 1992 and was the first PA-RISC microprocessor to integrate the floating-point unit (FPU) on-die. It operated at 33 - 100 MHz and competed primarily with the Digital Equipment Corporation (DEC) Alpha 21064 in the workstation and server markets. PA-7100 users were HP in its HP 9000 workstations and Stratus Computer in its Continuum fault-tolerant servers.
... In the March 1987 issue we described the HP 3000 Series 930 and HP 9000 Model 840 Computers, which were HP's first realizations of HP Precision Architecture in off-the-shelf TTL technology. ...
The HP Precision Architecture development program, known within HP as the Spectrum program, ...