This article needs to be updated.October 2019)(
This article needs additional citations for verification . (October 2019) (Learn how and when to remove this template message)
In computing, the clock multiplier (or CPU multiplier or bus/core ratio) sets the ratio of an internal CPU clock rate to the externally supplied clock. A CPU with a 10x multiplier will thus see 10 internal cycles (produced by PLL-based frequency multiplier circuitry) for every external clock cycle. For example, a system with an external clock of 100 MHz and a 36x clock multiplier will have an internal CPU clock of 3.6 GHz. The external address and data buses of the CPU (often collectively termed front side bus (FSB) in PC contexts) also use the external clock as a fundamental timing base; however, they could also employ a (small) multiple of this base frequency (typically two or four) to transfer data faster.
Computing is any activity that uses computers to manage, process, and communicate information. It includes development of both hardware and software. Computing is a critical, integral component of modern industrial technology. Major computing disciplines include computer engineering, software engineering, computer science, information systems, and information technology.
The clock rate typically refers to the frequency at which the clock circuit of a processor can generate pulses, which are used to synchronize the operations of its components, and is used as an indicator of the processor's speed. It is measured in clock cycles per second or its equivalent, the SI unit hertz (Hz). The clock rate of the first generation of computers was measured in hertz or kilohertz (kHz), the first personal computers (PCs) to arrive throughout the 1970s and 1980s had clock rates measured in megahertz (MHz), and in the 21st century the speed of modern CPUs is commonly advertised in gigahertz (GHz). This metric is most useful when comparing processors within the same family, holding constant other features that may affect performance. Video card and CPU manufacturers commonly select their highest performing units from a manufacturing batch and set their maximum clock rate higher, fetching a higher price.
In electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that oscillates between a high and a low state and is used like a metronome to coordinate actions of digital circuits.
The internal frequency of microprocessors is usually based on FSB frequency. To calculate internal frequency the CPU multiplies bus frequency by a number called the clock multiplier. For calculation, the CPU uses actual bus frequency, and not effective bus frequency. To determine the actual bus frequency for processors that use dual-data rate (DDR) buses (AMD Athlon and Duron) and quad-data rate buses (all Intel microprocessors starting from Pentium 4) the effective bus speed should be divided by 2 for AMD or 4 for Intel.
Clock multipliers on many modern processors are fixed; it is usually not possible to change them. Some versions of processors have clock multipliers unlocked; that is, they can be "overclocked" by increasing the clock multiplier setting in the motherboard's BIOS setup program. Some CPU engineering samples may also have the clock multiplier unlocked. Many Intel qualification samples have maximum clock multiplier locked: these CPUs may be underclocked (run at lower frequency), but they cannot be overclocked by increasing clock multiplier higher than intended by CPU design. While these qualification samples and majority of production microprocessors cannot be overclocked by increasing their clock multiplier, they still can be overclocked by using a different technique: by increasing FSB frequency.
As of 2009 [update] , computers have several interconnected devices (CPU, RAM, peripherals, etc. – see diagram) that typically run at different speeds. Thus they use internal buffers and caches when communicating with each other via the shared buses in the system. In PCs, the CPU's external address and data buses connect the CPU to the rest of the system via the "northbridge". Nearly every desktop CPU produced since the introduction of the 486DX2 in 1992 has employed a clock multiplier to run its internal logic at a higher frequency than its external bus, but still remain synchronous with it. This improves the CPU performance by relying on internal cache memories or wide buses (often also capable of more than one transfer per clock cycle) to make up for the frequency difference.
A northbridge or host bridge is one of the two chips in the core logic chipset architecture on a PC motherboard, the other being the southbridge. Unlike the southbridge, northbridge is connected directly to the CPU via the front-side bus (FSB) and is thus responsible for tasks that require the highest performance. The northbridge, also known as Memory Controller Hub, is usually paired with a southbridge. In systems where they are included, these two chips manage communications between the CPU and other parts of the motherboard, and constitute the core logic chipset of the PC motherboard.
The Intel i486DX2, rumored as 80486DX2 is a CPU produced by Intel that was introduced in 1992. The i486DX2 was nearly identical to the i486DX, but it had additional clock multiplier circuitry. It was the first chip to use clock doubling, whereby the processor runs two internal logic clock cycles per external bus cycle. An i486 DX2 was thus significantly faster than an i486 DX at the same bus speed thanks to the 8K on-chip cache shadowing the slower clocked external bus.
Some CPUs, such as Athlon 64 and Opteron, handle main memory using a separate and dedicated low-level memory bus. These processors communicate with other devices in the system (including other CPUs) using one or more slightly higher-level HyperTransport links; like the data and address buses in other designs, these links employ the external clock for data transfer timing (typically 800 MHz or 1 GHz, as of 2007).
The Athlon 64 is an eighth-generation, AMD64-architecture microprocessor produced by AMD, released on September 23, 2003. It is the third processor to bear the name Athlon, and the immediate successor to the Athlon XP. The second processor to implement AMD64 architecture and the first 64-bit processor targeted at the average consumer, it was AMD's primary consumer microprocessor, and competes primarily with Intel's Pentium 4, especially the "Prescott" and "Cedar Mill" core revisions. It is AMD's first K8, eighth-generation processor core for desktop and mobile computers. Despite being natively 64-bit, the AMD64 architecture is backward-compatible with 32-bit x86 instructions. Athlon 64s have been produced for Socket 754, Socket 939, Socket 940 and Socket AM2. The line was succeeded by the dual-core Athlon 64 X2 and Athlon X2 lines.
Opteron is AMD's x86 former server and workstation processor line, and was the first processor which supported the AMD64 instruction set architecture. It was released on April 22, 2003, with the SledgeHammer core (K8) and was intended to compete in the server and workstation markets, particularly in the same segment as the Intel Xeon processor. Processors based on the AMD K10 microarchitecture were announced on September 10, 2007, featuring a new quad-core configuration. The most-recently released Opteron CPUs are the Piledriver-based Opteron 4300 and 6300 series processors, codenamed "Seoul" and "Abu Dhabi" respectively. In January 2016, the first ARMv8-A based Opteron SoC was released.
The memory bus is the computer bus which connects the main memory to the memory controller in computer systems. Originally, general-purpose buses like VMEbus and the S-100 bus were used, but to reduce latency, modern memory buses are designed to connect directly to DRAM chips, and thus are designed by chip standards bodies such as JEDEC. Examples are the various generations of SDRAM, and serial point-to-point buses like SLDRAM and RDRAM. An exception is the Fully Buffered DIMM which, despite being carefully designed to minimize the effect, has been criticized for its higher latency.
Some systems allow owners to change the clock multiplier in the BIOS menu. Increasing the clock multiplier will increase the CPU clock speed without affecting the clock speed of other components. Increasing the external clock (and bus speed) will affect the CPU as well as RAM and other components.
BIOS is firmware used to perform hardware initialization during the booting process, and to provide runtime services for operating systems and programs. The BIOS firmware comes pre-installed on a personal computer's system board, and it is the first software to run when powered on. The name originates from the Basic Input/Output System used in the CP/M operating system in 1975. The BIOS originally proprietary to the IBM PC has been reverse engineered by companies looking to create compatible systems. The interface of that original system serves as a de facto standard.
These adjustments provide the two common methods of overclocking and underclocking a computer, perhaps combined with some adjustment of CPU or memory voltages (changing oscillator crystals occurs only rarely); note that careless overclocking can cause damage to a CPU or other component due to overheating or even voltage breakdown. Newer CPUs often have a locked clock multiplier, meaning that the bus speed or the clock multiplier cannot be changed in the BIOS unless the user hacks the CPU to unlock the multiplier. High end CPUs, however, normally have an unlocked clock multiplier.
In computing, overclocking is the practice of increasing the clock rate of a computer to exceed that certified by the manufacturer. Commonly operating voltage is also increased to maintain a component's operational stability at accelerated speeds. Semiconductor devices operated at higher frequencies and voltages increase power consumption and heat. An overclocked device may be unreliable or fail completely if the additional heat load is not removed or power delivery components cannot meet increased power demands. Many device warranties state that overclocking and/or over-specification voids any warranty.
Underclocking, also known as downclocking, is modifying a computer or electronic circuit's timing settings to run at a lower clock rate than is specified. Underclocking is used to reduce a computer's power consumption, increase battery life, reduce heat emission, and it may also increase the system's stability and compatibility. Underclocking may be implemented by the factory, but many computers and components may be underclocked by the end user.
The phrase clock doubling implies a clock multiplier of two.
Examples of clock-doubled CPUs include:
Weitek Corporation was an American chip-design company that originally focused on floating-point units for a number of commercial CPU designs. During the early to mid-1980s, Weitek designs could be found powering a number of high-end designs and parallel-processing supercomputers. During the early 1990s most CPU designs started including FPUs built into the system, basically "for free", and Weitek made a series of attempts to break into the general CPU and graphics driver market. By 1995 the company was almost dead, and in late 1996 the remains were purchased by Rockwell's Semiconductor Systems and quickly disappeared.
SPARC is a reduced instruction set computing (RISC) instruction set architecture (ISA) originally developed by Sun Microsystems and Fujitsu. Its design was strongly influenced by the experimental Berkeley RISC system developed in the early 1980s. First developed in 1986 and released in 1987, SPARC was one of the most successful early commercial RISC systems, and its success led to the introduction of similar RISC designs from a number of vendors through the 1980s and 90s.
In both these cases the overall speed of the systems increased by about 75%.[ citation needed ]
By the late 1990s almost all high-performance processors (excluding typical embedded systems) run at higher speeds than their external buses, so the term "clock doubling" has lost much of its impact.
For CPU-bound applications, clock doubling will theoretically improve the overall performance of the machine substantially, provided the fetching of data from memory does not prove a bottleneck. In more modern processors where the multiplier greatly exceeds two, the bandwidth and latency of specific memory ICs (or the bus or memory controller) typically become a limiting factor.
Pentium 4 is a brand by Intel for an entire series of single-core CPUs for desktops, laptops and entry-level servers. The processors were shipped from November 20, 2000, until August 8, 2008.
The Pentium II brand refers to Intel's sixth-generation microarchitecture ("P6") and x86-compatible microprocessors introduced on May 7, 1997. Containing 7.5 million transistors, the Pentium II featured an improved version of the first P6-generation core of the Pentium Pro, which contained 5.5 million transistors. However, its L2 cache subsystem was a downgrade when compared to the Pentium Pro's.
The Pentium III brand refers to Intel's 32-bit x86 desktop and mobile microprocessors based on the sixth-generation P6 microarchitecture introduced on February 26, 1999. The brand's initial processors were very similar to the earlier Pentium II-branded microprocessors. The most notable differences were the addition of the SSE instruction set, and the introduction of a controversial serial number embedded in the chip during the manufacturing process.
A front-side bus (FSB) is a computer communication interface (bus) that was often used in Intel-chip-based computers during the 1990s and 2000s. The EV6 bus served the same function for competing AMD CPUs. Both typically carry data between the central processing unit (CPU) and a memory controller hub, known as the northbridge.
The K6-III, code-named "Sharptooth", is an x86 microprocessor manufactured by AMD, released on February 22, 1999, with 400 and 450 MHz models. It was the last Socket 7 desktop processor. For an extremely short time after its release, the fastest available desktop processor from Intel was the Pentium II 450 MHz. However, the K6-III also competed against the Pentium III "Katmai" line, released just days later on February 26. "Katmai" CPUs reached speeds of 500 MHz, slightly faster than the K6-III 450 MHz. K6-III performance was significantly improved over the K6-2 due to the addition of an on-die L2 cache running at full clock speed. When equipped with a 1MB L3 cache on the motherboard the 400 and 450 MHz K6-IIIs is claimed by Ars Technica to often outperform the more expensive Pentium III "Katmai" 450- and 500-MHz models, respectively.
In personal computer microprocessor architecture, a back-side bus (BSB), or backside bus, was a computer bus used on early Intel platforms to connect the CPU to CPU cache memory, usually off-die L2. If a design utilizes it along with a front-side bus (FSB), it is said to use a dual-bus architecture, or in Intel's terminology Dual Independent Bus (DIB) architecture. The Back-side bus architecture was discontinued when newer processors like the second-generation Pentium III began to incorporate on-die L2 cache, which at the time was advertised as Advanced Transfer Cache.
The Pentium D brand refers to two series of desktop dual-core 64-bit x86-64 microprocessors with the NetBurst microarchitecture, which is the dual-core variant of Pentium 4 "Prescott" manufactured by Intel. Each CPU comprised two dies, each containing a single core, glued together on a multi-chip module package. The brand's first processor, codenamed Smithfield, was released by Intel on May 25, 2005. Nine months later, Intel introduced its successor, codenamed Presler, but without offering significant upgrades in design, still resulting in relatively high power consumption. By 2004, the NetBurst processors reached a clock speed barrier at 3.8 GHz due to a thermal limit exemplified by the Presler's 130 watt thermal design power. The future belonged to more energy efficient and slower clocked dual-core CPUs on a single die instead of two. The final shipment date of the dual die Presler chips was August 8, 2008, which marked the end of the Pentium D brand and also the NetBurst microarchitecture.
The P6 microarchitecture is the sixth-generation Intel x86 microarchitecture, implemented by the Pentium Pro microprocessor that was introduced in November 1995. It is frequently referred to as i686. It was succeeded by the NetBurst microarchitecture in 2000, but eventually revived in the Pentium M line of microprocessors. The successor to the Pentium M variant of the P6 microarchitecture is the Core microarchitecture which in turn is also derived from the P6 microarchitecture.
Pumping, when referring to computer systems, is an informal term for transmitting a data signal more than one time per clock signal.
A memory divider is a ratio which is used to determine the operating clock frequency of computer memory in accordance with front side bus (FSB) frequency, if the memory system is dependent on FSB clock speed. Along with memory latency timings, memory dividers are extensively used in overclocking memory subsystems to find stable, working memory states at higher FSB frequencies. The ratio between DRAM and FSB is commonly referred to as "DRAM:FSB ratio".
The UltraSPARC III, code-named "Cheetah", is a microprocessor that implements the SPARC V9 instruction set architecture (ISA) developed by Sun Microsystems and fabricated by Texas Instruments. It was introduced in 2001 and operates at 600 to 900 MHz. It was succeeded by the UltraSPARC IV in 2004. Gary Lauterbach was the chief architect.