Last updated
SuperH (SH)
Designer Hitachi Ltd.
Bits32-bit (32 → 64)
Design RISC
Encoding Fixed
Endianness Bi

SuperH (or SH) is a 32-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Hitachi and currently produced by Renesas. It is implemented by microcontrollers and microprocessors for embedded systems.

In computer architecture, 32-bit integers, memory addresses, or other data units are those that are 32 bits wide. Also, 32-bit CPU and ALU architectures are those that are based on registers, address buses, or data buses of that size. 32-bit microcomputers are computers in which 32-bit microprocessors are the norm.

An instruction set architecture (ISA) is an abstract model of a computer. It is also referred to as architecture or computer architecture. A realization of an ISA is called an implementation. An ISA permits multiple implementations that may vary in performance, physical size, and monetary cost ; because the ISA serves as the interface between software and hardware. Software that has been written for an ISA can run on different implementations of the same ISA. This has enabled binary compatibility between different generations of computers to be easily achieved, and the development of computer families. Both of these developments have helped to lower the cost of computers and to increase their applicability. For these reasons, the ISA is one of the most important abstractions in computing today.

Hitachi Japanese multinational engineering and electronics company

Hitachi, Ltd. is a Japanese multinational conglomerate company headquartered in Chiyoda, Tokyo, Japan. It is the parent company of the Hitachi Group and forms part of the DKB Group of companies. Hitachi is a highly diversified company that operates eleven business segments: Information & Telecommunication Systems, Social Infrastructure, High Functional Materials & Components, Financial Services, Power Systems, Electronic Systems & Equipment, Automotive Systems, Railway & Urban Systems, Digital Media & Consumer Products, Construction Machinery and Other Components & Systems.


As of 2015, many of the original patents for the SuperH architecture are expiring and the SH2 CPU has been reimplemented as open source hardware under the name J2.

Patent Intellectual property conferring a monopoly on a new invention

A patent is a form of intellectual property that gives its owner the legal right to exclude others from making, using, selling, and importing an invention for a limited period of years, in exchange for publishing an enabling public disclosure of the invention. In most countries patent rights fall under civil law and the patent holder needs to sue someone infringing the patent in order to enforce his or her rights. In some industries patents are an essential form of competitive advantage; in others they are irrelevant.


SH-2 on Sega 32X and Sega Saturn HD6417095 01.jpg
SH-2 on Sega 32X and Sega Saturn

The SuperH processor core family was first developed by Hitachi in the early 1990s. Hitachi has developed a complete group of upward compatible instruction set CPU cores. The SH-1 and the SH-2 were used in the Sega Saturn, Sega 32X and Capcom CPS-3. [1] These cores have 16-bit instructions for better code density than 32-bit instructions, which was a great benefit at the time, due to the high cost of main memory.

Sega Saturn Video game console

The Sega Saturn is a 32-bit fifth-generation home video game console developed by Sega and released on November 22, 1994 in Japan, May 11, 1995 in North America, and July 8, 1995 in Europe. The successor to the successful Sega Genesis, the Saturn has a dual-CPU architecture and eight processors. Its games are in CD-ROM format, and its game library contains several arcade ports as well as original games.

In computer architecture, 16-bit integers, memory addresses, or other data units are those that are 16 bits wide. Also, 16-bit CPU and ALU architectures are those that are based on registers, address buses, or data buses of that size. 16-bit microcomputers are computers in which 16-bit microprocessors were the norm.

A few years later the SH-3 core was added to the SH CPU family; new features included another interrupt concept, a memory management unit (MMU) and a modified cache concept. The SH-3 core also got a DSP extension, then called SH-3-DSP. With extended data paths for efficient DSP processing, special accumulators and a dedicated MAC-type DSP engine, this core was unifying the DSP and the RISC processor world. A derivative was also used with the original SH-2 core.

Memory management unit Hardware translating virtual addresses to physical address

A memory management unit (MMU), sometimes called paged memory management unit (PMMU), is a computer hardware unit having all memory references passed through itself, primarily performing the translation of virtual memory addresses to physical addresses.

Digital signal processing (DSP) is the use of digital processing, such as by computers or more specialized digital signal processors, to perform a wide variety of signal processing operations. The signals processed in this manner are a sequence of numbers that represent samples of a continuous variable in a domain such as time, space, or frequency.

Between 1994 and 1996, 35.1 million SuperH devices were shipped worldwide. [2]

For the Dreamcast, Hitachi developed the SH-4 architecture. Superscalar (2-way) instruction execution and a vector floating point unit (particularly suited to 3d graphics) were the highlights of this architecture. SH-4 based standard chips were introduced around 1998.

Dreamcast video game console

The Dreamcast is a home video game console released by Sega on November 27, 1998 in Japan, September 9, 1999 in North America, and October 14, 1999 in Europe. It was the first in the sixth generation of video game consoles, preceding Sony's PlayStation 2, Nintendo's GameCube and Microsoft's Xbox. The Dreamcast was Sega's final home console, marking the end of the company's 18 years in the console market.

In computing, a vector processor or array processor is a central processing unit (CPU) that implements an instruction set containing instructions that operate on one-dimensional arrays of data called vectors, compared to the scalar processors, whose instructions operate on single data items. Vector processors can greatly improve performance on certain workloads, notably numerical simulation and similar tasks. Vector machines appeared in the early 1970s and dominated supercomputer design through the 1970s into the 1990s, notably the various Cray platforms. The rapid fall in the price-to-performance ratio of conventional microprocessor designs led to the vector supercomputer's demise in the later 1990s.

The SH-3 and SH-4 architectures support both big-endian and little-endian byte ordering (they are bi-endian).


Hitachi and STMicroelectronics started collaborating as early as 1997 on the design of the SH-4. In early 2001, they formed the IP company SuperH, Inc., which was going to license the SH-4 core to other companies and was developing the SH-5 architecture, the first move of SuperH into the 64-bit area. [3] [4] In 2003, Hitachi and Mitsubishi Electric formed a joint-venture called Renesas Technology, with Hitachi controlling 55% of it. In 2004, Renesas Technology bought STMicroelectronics's share of ownership in the SuperH Inc. and with it the licence to the SH cores. [5] Renesas Technology later became Renesas Electronics, following their merger with NEC Electronics.

The SH-5 design supported two modes of operation. SHcompact mode is equivalent to the user-mode instructions of the SH-4 instruction set. SHmedia mode is very different, using 32-bit instructions with sixty-four 64-bit integer registers and SIMD instructions. In SHmedia mode the destination of a branch (jump) is loaded into a branch register separately from the actual branch instruction. This allows the processor to prefetch instructions for a branch without having to snoop the instruction stream. The combination of a compact 16-bit instruction encoding with a more powerful 32-bit instruction encoding is not unique to SH-5; ARM processors have a 16-bit Thumb mode (ARM licensed several patents from SuperH for Thumb [6] ) and MIPS processors have a MIPS-16 mode. However, SH-5 differs because its backward compatibility mode is the 16-bit encoding rather than the 32-bit encoding.

The evolution of the SuperH architecture still continues. The latest evolutionary step happened around 2003 where the cores from SH-2 up to SH-4 were getting unified into a superscalar SH-X core which forms a kind of instruction set superset of the previous architectures.

Today, the SuperH CPU cores, architecture and products are with Renesas Electronics, a merger of the Hitachi and Mitsubishi semiconductor groups and the architecture is consolidated around the SH-2, SH-2A, SH-3, SH-4 and SH-4A platforms giving a scalable family.

J Core

The last of the SH-2 patents expired in 2014. At LinuxCon Japan 2015, j-core developers presented a cleanroom reimplemention of the SH-2 ISA with extensions (known as the "J2 core" due to the unexpired trademarks). [6] [7] Subsequently, a design walkthrough was presented at ELC 2016. [8]

The open source BSD licensed VHDL code for the J2 core has been proven on Xilinx FPGAs and on ASICs manufactured on TSMC's 180 nm process, and is capable of booting µClinux. [6] J2 is backwards ISA compatible with SH-2, implemented as a 5-stage pipeline with separate Instruction and Data memory interfaces, and a machine generated Instruction Decoder supporting the densely packed and complex (relative to other RISC machines) ISA. Additional instructions are easy to add. J2 implements instructions for dynamic shift (using the SH-3 and later instruction patterns), extended atomic operations (used for threading primitives) and locking/interfaces for symmetric multiprocessor support. Plans to implement the SH-2A (as "J2+") and SH-4 (as "J4") instruction sets as the relevant patents expire in 2016-2017. [6]

Several features of SuperH have been cited as motivations for designing new cores based on this architecture: [6]


Hitachi SH-3 CPU Hitachi SH3.jpg
Hitachi SH-3 CPU

The family of SuperH CPU cores includes:


Hitachi SH-2 CPU Denso-SH2.jpg
Hitachi SH-2 CPU

The SH-2 is a 32-bit RISC architecture with a 16-bit fixed instruction length for high code density and features a hardware multiply–accumulate (MAC) block for DSP algorithms and has a five-stage pipeline.

The SH-2 has a cache on all ROM-less devices.

It provides 16 general purpose registers, a vector-base-register, global-base-register, and a procedure register.

Today the SH-2 family stretches from 32 KB of on-board flash up to ROM-less devices. It is used in a variety of different devices with differing peripherals such as CAN, Ethernet, motor-control timer unit, fast ADC and others.


The SH-2A is an upgrade to the SH-2 core. It was announced in early 2006.

At launch in 2007 the SH-2A based SH7211 was the world's fastest embedded flash microcontroller running at 160 MHz. It has later been superseded by several newer SuperH devices running at up to 200 MHz.

New features on the SH-2A core include:

The SH-2A family today spans a wide memory field from 16 KB up to and includes many ROM-less variations. The devices feature standard peripherals such as CAN, Ethernet, USB and more as well as more application specific peripherals such as motor control timers, TFT controllers and peripherals dedicated to automotive powertrain applications.


Hitachi SH-4 CPU SH7091 01.jpg
Hitachi SH-4 CPU

The SH-4 is a 32-bit RISC CPU and was developed for primary use in multimedia applications, such as Sega's Dreamcast and NAOMI game systems. It includes a much more powerful floating point unit [note] and additional built-in functions, along with the standard 32-bit integer processing and 16-bit instruction size.

SH-4 features include:

^ There is no FPU in the custom SH4 made for Casio, the SH7305.


The SH-5 is a 64-bit RISC CPU. [11]

Almost no non-simulated SH-5 hardware was ever released, [12] and unlike the still live SH-4, support for SH-5 was dropped from gcc. [13]

Related Research Articles

MIPS is a reduced instruction set computer (RISC) instruction set architecture (ISA) developed by MIPS Computer Systems, now MIPS Technologies, based in the United States.

Very long instruction word (VLIW) refers to instruction set architectures designed to exploit instruction level parallelism (ILP). Whereas conventional central processing units mostly allow programs to specify instructions to execute in sequence only, a VLIW processor allows programs to explicitly specify instructions to execute in parallel. This design is intended to allow higher performance without the complexity inherent in some other designs.

ARM, previously Advanced RISC Machine, originally Acorn RISC Machine, is a family of reduced instruction set computing (RISC) architectures for computer processors, configured for various environments. Arm Holdings develops the architecture and licenses it to other companies, who design their own products that implement one of those architectures‍—‌including systems-on-chips (SoC) and systems-on-modules (SoM) that incorporate memory, interfaces, radios, etc. It also designs cores that implement this instruction set and licenses these designs to a number of companies that incorporate those core designs into their own products.

The Motorola 68000 series is a family of 32-bit CISC microprocessors. During the 1980s and early 1990s, they were popular in personal computers and workstations and were the primary competitors of Intel's x86 microprocessors. They were most well known as the processors powering the early Apple Macintosh, the Commodore Amiga, the Sinclair QL, the Atari ST, the Sega Genesis, and several others. Although no modern desktop computers are based on processors in the 68000 series, derivative processors are still widely used in embedded systems.


The transputer is a series of pioneering microprocessors from the 1980s, featuring integrated memory and serial communication links, intended for parallel computing. They were designed and produced by Inmos, a semiconductor company based in Bristol, United Kingdom.

Intel i960 RISC-based microprocessor design

Intel's i960 was a RISC-based microprocessor design that became popular during the early 1990s as an embedded microcontroller. It became a best-selling CPU in that segment, along with the competing AMD 29000. In spite of its success, Intel stopped marketing the i960 in the late 1990s, as a result of a settlement with DEC whereby Intel received the rights to produce the StrongARM CPU. The processor continues to be used for a few military applications.


The Blackfin is a family of 16-/32-bit microprocessors developed, manufactured and marketed by Analog Devices. The processors have built-in, fixed-point digital signal processor (DSP) functionality supplied by 16-bit multiply–accumulates (MACs), accompanied on-chip by a microcontroller. It was designed for a unified low-power processor architecture that can run operating systems while simultaneously handling complex numeric tasks such as real-time H.264 video encoding.

ARM7 is a group of older 32-bit RISC ARM processor cores licensed by ARM Holdings for microcontroller use. The ARM7 core family consists of ARM700, ARM710, ARM7DI, ARM710a, ARM720T, ARM740T, ARM710T, ARM7TDMI, ARM7TDMI-S, ARM7EJ-S. The ARM7TDMI and ARM7TDMI-S were the most popular cores of the family. Since ARM7 cores were released from 1993 to 2001, they are no longer recommended for new IC designs; instead ARM Cortex-M or ARM Cortex-R cores are preferred.

V850 is the trademark name for a 32-bit RISC CPU architecture of Renesas Electronics for embedded microcontrollers, introduced in early 90's by NEC and still being developed as of 2018.
V850 Family has been evolved by many microarchitecture extensions until today, but all the extensions have binary code level backward compatibility of programs across a quarter century. Its basis is 32 of 32-bit general-purpose registers with load/store architecture. It has high code efficiency because most of frequently used instructions are mapped into 16-bit half-word.
In its earlier stage, it mainly focused on ultra-low power consumption such as 0.5 mW/MIPS. V850 has been widely used in variety of applications including: optical disk drives, hard disk drives, mobile phones, car audio and inverter compressors for air conditioners. But today, new microarchitectures are mainly toward high performance and high reliability with such as dual-lockstep redundant mechanism for automotive industry. Nowadays, V850 Family and RH850 Family are comprehensively used in a car.
V850 Family and RH850 Family has huge assets of software and development tools such as ITRON based RTOS, AUTOSAR (OSEK/VDX) based RTOS, famous RTOS, compilers, automated code reviewers, virtual platform with instruction set simulators, debuggers, and both full probing-pod-based and JTAG-based in-circuit emulators.

Sega Aurora is a highly integrated hardware platform that Sega Sammy developed to power amusement devices like their pachinko/pachislot machine displays and arcade games and to also be sublicensed to outside manufacturers who are looking to build multimedia portable and embedded systems. It was developed by SI Electronics Inc, a former Sammy subsidiary. It was introduced in 2004 and is primarily based on an enhanced Dreamcast hardware. The name "Aurora" derives from a top secret code name that Sega Enterprises, Ltd. used during the development of Sega Saturn in the mid 1990s. As SI Electronics left Sammy Holdings after being acquired by Kaga Electronics in July 1, 2008, they made the "System Board Y2" platform in 2009, mainly known for the game "King of Fighters 2002: Ultimate Match".

ARM9 is a group of older 32-bit RISC ARM processor cores licensed by ARM Holdings for microcontroller use. The ARM9 core family consists of ARM9TDMI, ARM940T, ARM9E-S, ARM966E-S, ARM920T, ARM922T, ARM946E-S, ARM9EJ-S, ARM926EJ-S, ARM968E-S, ARM996HS. Since ARM9 cores were released from 1998 to 2006, they are no longer recommended for new IC designs, instead ARM Cortex-A, ARM Cortex-M, ARM Cortex-R cores are preferred.

IEBus Communication bus specification

IEBus is a communication bus specification "between equipments within a vehicle or a chassis" of Renesas Electronics. It defines OSI model layer 1 and layer 2 specification. IEBus is mainly used for car audio and car navigations, which established de facto standard in Japan, though SAE J1850 is major in United States.
IEBus is also used in some vending machines, which major customer is Fuji Electric. Each button on the vending machine has an IEBus ID, i.e. has a controller.
Detailed specification is disclosed to licensees only, but protocol analyzers are provided from some test equipment vendors. Its modulation method is PWM with 6.00 MHz base clock originally, but most of automotive customers use 6.291 MHz, and physical layer is a pair of differential signalling harness. Its physical layer adopts half-duplex, asynchronous, and multi-master communication with CSMA/CD for access control. It allows for up to fifty units on one bus over a maximum length of 150 meters. Two differential signalling lines are used with Bus+ / Bus− naming, sometimes labeled as Data(+) / Data(−).

PowerPC e300

The PowerPC e300 is a family of 32-bit PowerPC microprocessor cores developed by Freescale for primary use in system-on-a-chip (SoC) designs with speed ranging up to 800 MHz, thus making them ideal for embedded applications.

ARM Cortex-M series of processor core models

The ARM Cortex-M is a group of 32-bit RISC ARM processor cores licensed by Arm Holdings. They are intended for microcontroller use, and have been shipped in tens of billions of devices. The cores consist of the Cortex-M0, Cortex-M0+, Cortex-M1, Cortex-M3, Cortex-M4, Cortex-M7, Cortex-M23, Cortex-M33, Cortex-M35P. The Cortex-M4 / M7 / M33 / M35P cores have an FPU silicon option, and when included in the silicon these cores are known as "Cortex-Mx with FPU" or "Cortex-MxF", where 'x' is the core number.

The IBM POWER ISA is a reduced instruction set computer (RISC) instruction set architecture (ISA) developed by IBM. The name is an acronym for Performance Optimization With Enhanced RISC.

RISC-V is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.


  1. "CP System III (CPS3) Hardware (Capcom)". System 16. Retrieved 3 August 2019.
  3. "STMicro, Hitachi plan new company to develop RISC cores". EE Times. 3 April 2001. Hitachi created the SH family of processors and developed its first four major iterations, but has worked with ST since 1997, when the companies agreed to share a common high-end microprocessor road map. They jointly developed the 32-bit SH4 RISC processor core, and began development of the SH5 architecture, which will now be completed by SuperH. SuperH's initial product will be the SH4 core. Earlier SH versions will not be part of the spin-off agreement.
  4. "SuperH, Inc. formed by Hitachi and STMicroelectronics to Boost the Proliferation of SuperH™ Cores in Embedded Microprocessor Applications".
  5. "Renesas to take over SuperH core business". EE Times. 28 September 2004.
  6. 1 2 3 4 5 Nathan Willis (June 10, 2015). "Resurrecting the SuperH architecture".
  7. 1 2 "J Cores". j-core. Archived from the original on May 11, 2016. Retrieved April 27, 2016.
  9. V.M. Weaver (17 March 2015). "Exploring the Limits of Code Density (Tech Report with Newest Results)" (PDF).
  10. Kuwabara (25 July 2019). "Korg EMX / ESX Service Manual" (PDF).
  11. "SH-5 CPU Core, Volume1: Architecture" (PDF).
  12. "Wasabi SH-5 Press Release". 8 March 2016.
  13. "GCC 7 Release Series Changes, New Features, and Fixes". 2 February 2018.