Last updated
SuperH (SH)
Designer Hitachi Ltd.
Bits32-bit (32 → 64)
Design RISC
Encoding SH2: 16-bit instructions; SH2A and newer: mixed 16- and 32-bit instructions
Endianness Bi
OpenYes, and royalty free [1]

SuperH (or SH) is a 32-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Hitachi and currently produced by Renesas. It is implemented by microcontrollers and microprocessors for embedded systems.


At the time of introduction, SH2 was notable for having fixed-length 16-bit instructions despite of 32-bit architecture. This was a novel approach: at the time RISC processors instruction width was always dictated by architecture width. In other words, 32-bit RISC processors always used fixed 32-bit instructions.

Later the idea of what is now called compressed instruction set[ citation needed ] was adopted by other companies, most notable example being ARM that licensed relevant SuperH patents to create Thumb instruction set.

As of 2015, many of the original patents for the SuperH architecture are expiring and the SH2 CPU has been reimplemented as open source hardware under the name J2.


SH-2 on Sega 32X and Sega Saturn HD6417095 01.jpg
SH-2 on Sega 32X and Sega Saturn

The SuperH processor core family was first developed by Hitachi in the early 1990s. Hitachi has developed a complete group of upward compatible instruction set CPU cores. The SH-1 and the SH-2 were used in the Sega Saturn, Sega 32X and Capcom CPS-3. [2] These cores have 16-bit instructions for better code density than 32-bit instructions, which was a great benefit at the time, due to the high cost of main memory.

A few years later, the SH-3 core was added to the SH CPU family; new features included another interrupt concept, a memory management unit (MMU) and a modified cache concept. The SH-3 core also got a DSP extension, then called SH-3-DSP. With extended data paths for efficient DSP processing, special accumulators and a dedicated MAC-type DSP engine, this core was unifying the DSP and the RISC processor world. A derivative was also used with the original SH-2 core.

Between 1994 and 1996, 35.1 million SuperH devices were shipped worldwide. [3]

For the Dreamcast, Hitachi developed the SH-4 architecture. Superscalar (2-way) instruction execution and a vector floating-point unit (particularly suited to 3d graphics) were the highlights of this architecture. SH-4 based standard chips were introduced around 1998.

The SH-3 and SH-4 architectures support both big-endian and little-endian byte ordering (they are bi-endian).


Hitachi and STMicroelectronics started collaborating as early as 1997 on the design of the SH-4. In early 2001, they formed the IP company SuperH, Inc., which was going to license the SH-4 core to other companies and was developing the SH-5 architecture, the first move of SuperH into the 64-bit area. [4] [5] In 2003, Hitachi and Mitsubishi Electric formed a joint-venture called Renesas Technology, with Hitachi controlling 55% of it. In 2004, Renesas Technology bought STMicroelectronics's share of ownership in the SuperH Inc. and with it the licence to the SH cores. [6] Renesas Technology later became Renesas Electronics, following their merger with NEC Electronics.

The SH-5 design supported two modes of operation. SHcompact mode is equivalent to the user-mode instructions of the SH-4 instruction set. SHmedia mode is very different, using 32-bit instructions with sixty-four 64-bit integer registers and SIMD instructions. In SHmedia mode the destination of a branch (jump) is loaded into a branch register separately from the actual branch instruction. This allows the processor to prefetch instructions for a branch without having to snoop the instruction stream. The combination of a compact 16-bit instruction encoding with a more powerful 32-bit instruction encoding is not unique to SH-5; ARM processors have a 16-bit Thumb mode (ARM licensed several patents from SuperH for Thumb [7] ) and MIPS processors have a MIPS-16 mode. However, SH-5 differs because its backward compatibility mode is the 16-bit encoding rather than the 32-bit encoding.

The evolution of the SuperH architecture still continues. The latest evolutionary step happened around 2003 where the cores from SH-2 up to SH-4 were getting unified into a superscalar SH-X core which forms a kind of instruction set superset of the previous architectures.

Today[ when? ], the SuperH CPU cores, architecture and products are with Renesas Electronics, a merger of the Hitachi and Mitsubishi semiconductor groups and the architecture is consolidated around the SH-2, SH-2A, SH-3, SH-4 and SH-4A platforms giving a scalable family.

J Core

The last of the SH-2 patents expired in 2014. At LinuxCon Japan 2015, j-core developers presented a cleanroom reimplemention of the SH-2 ISA with extensions (known as the "J2 core" due to the unexpired trademarks). [7] [8] Subsequently, a design walkthrough was presented at ELC 2016. [9]

The open source BSD licensed VHDL code for the J2 core has been proven on Xilinx FPGAs and on ASICs manufactured on TSMC's 180 nm process, and is capable of booting µClinux. [7] J2 is backwards ISA compatible with SH-2, implemented as a 5-stage pipeline with separate Instruction and Data memory interfaces, and a machine generated Instruction Decoder supporting the densely packed and complex (relative to other RISC machines) ISA. Additional instructions are easy to add. J2 implements instructions for dynamic shift (using the SH-3 and later instruction patterns), extended atomic operations (used for threading primitives) and locking/interfaces for symmetric multiprocessor support. Plans to implement the SH-2A (as "J2+") and SH-4 (as "J4") instruction sets as the relevant patents expire in 2016-2017. [7]

Several features of SuperH have been cited as motivations for designing new cores based on this architecture: [7]


Hitachi SH-3 CPU Hitachi SH3.jpg
Hitachi SH-3 CPU

The family of SuperH CPU cores includes:


Hitachi SH-2 CPU Denso-SH2.jpg
Hitachi SH-2 CPU

The SH-2 is a 32-bit RISC architecture with a 16-bit fixed instruction length for high code density and features a hardware multiply–accumulate (MAC) block for DSP algorithms and has a five-stage pipeline.

The SH-2 has a cache on all ROM-less devices.

It provides 16 general purpose registers, a vector-base-register, global-base-register, and a procedure register.

Today the SH-2 family stretches from 32 KB of on-board flash up to ROM-less devices. It is used in a variety of different devices with differing peripherals such as CAN, Ethernet, motor-control timer unit, fast ADC and others.


The SH-2A is an upgrade to the SH-2 core that added some 32-bit instructions. It was announced in early 2006.

New features on the SH-2A core include:

The SH-2A family today spans a wide memory field from 16 KB up to and includes many ROM-less variations. The devices feature standard peripherals such as CAN, Ethernet, USB and more as well as more application specific peripherals such as motor control timers, TFT controllers and peripherals dedicated to automotive powertrain applications.


Hitachi SH-4 CPU SH7091 01.jpg
Hitachi SH-4 CPU

The SH-4 is a 32-bit RISC CPU and was developed for primary use in multimedia applications, such as Sega's Dreamcast and NAOMI game systems. It includes a much more powerful floating-point unit [note] and additional built-in functions, along with the standard 32-bit integer processing and 16-bit instruction size.

SH-4 features include:

^ There is no FPU in the custom SH4 made for Casio, the SH7305.


The SH-5 is a 64-bit RISC CPU. [12]

Almost no non-simulated SH-5 hardware was ever released, [13] and unlike the still live SH-4, support for SH-5 was dropped from gcc. [14]

Related Research Articles

Reduced instruction set computer a processor executing one instruction in minimal clock cycles

A reduced instruction set computer, or RISC, is a computer with a small, highly-optimized set of instructions, rather than the more specialized set often found in other types of architecture, such as in a complex instruction set computer (CISC). The main distinguishing feature of RISC architecture is that the instruction set is optimized with a large number of registers and a highly regular instruction pipeline, allowing a low number of clock cycles per instruction (CPI). Another common RISC feature is the load/store architecture, in which memory is accessed through specific instructions rather than as a part of most instructions in the set.

Superscalar processor CPU that implements instruction-level parallelism within a single processor

A superscalar processor is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor. In contrast to a scalar processor that can execute at most one single instruction per clock cycle, a superscalar processor can execute more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to different execution units on the processor. It therefore allows for more throughput than would otherwise be possible at a given clock rate. Each execution unit is not a separate processor, but an execution resource within a single CPU such as an arithmetic logic unit.

Very long instruction word (VLIW) refers to instruction set architectures designed to exploit instruction level parallelism (ILP). Whereas conventional central processing units mostly allow programs to specify instructions to execute in sequence only, a VLIW processor allows programs to explicitly specify instructions to execute in parallel. This design is intended to allow higher performance without the complexity inherent in some other designs.

Arm, previously Advanced RISC Machine, originally Acorn RISC Machine, is a family of reduced instruction set computing (RISC) architectures for computer processors, configured for various environments. Arm Holdings develops the architecture and licenses it to other companies, who design their own products that implement one of those architectures‍—‌including systems-on-chips (SoC) and systems-on-modules (SoM) that incorporate memory, interfaces, radios, etc. It also designs cores that implement this instruction set and licenses these designs to a number of companies that incorporate those core designs into their own products.

The Motorola 68000 series is a family of 32-bit CISC microprocessors. During the 1980s and early 1990s, they were popular in personal computers and workstations and were the primary competitors of Intel's x86 microprocessors. They were most well known as the processors powering the early Apple Macintosh, the Sharp X68000, the Commodore Amiga, the Sinclair QL, the Atari ST, the Sega Genesis, the AT&T UnixPC, the Tandy Model 16/16B/6000, the Sun Microsystems Sun-1/Sun-3, the NeXT Computer, the Texas Instruments TI-89/TI-92 calculators, the Palm Pilot and the Space Shuttle. Although no modern desktop computers are based on processors in the 680x0 series, derivative processors are still widely used in embedded systems.

Transputer Series of pioneering microprocessors from the 1980s

The transputer is a series of pioneering microprocessors from the 1980s, featuring integrated memory and serial communication links, intended for parallel computing. They were designed and produced by Inmos, a semiconductor company based in Bristol, United Kingdom.

Intel i960 RISC-based microprocessor design

Intel's i960 was a RISC-based microprocessor design that became popular during the early 1990s as an embedded microcontroller. It became a best-selling CPU in that segment, along with the competing AMD 29000. In spite of its success, Intel stopped marketing the i960 in the late 1990s, as a result of a settlement with DEC whereby Intel received the rights to produce the StrongARM CPU. The processor continues to be used for a few military applications.

The POWER1 is a multi-chip CPU developed and fabricated by IBM that implemented the POWER instruction set architecture (ISA). It was originally known as the RISC System/6000 CPU or, when in an abbreviated form, the RS/6000 CPU, before introduction of successors required the original name to be replaced with one that used the same naming scheme (POWERn) as its successors in order to differentiate it from the newer designs.

Clipper architecture 32-bit RISC-like computing architecture

The Clipper architecture is a 32-bit RISC-like instruction set architecture designed by Fairchild Semiconductor. The architecture never enjoyed much market success, and the only computer manufacturers to create major product lines using Clipper processors were Intergraph and High Level Hardware. The first processors using the Clipper architecture were designed and sold by Fairchild, but the division responsible for them was subsequently sold to Intergraph in 1987; Intergraph continued work on Clipper processors for use in its own systems.

V850 is the trademark name for a 32-bit RISC CPU architecture of Renesas Electronics for embedded microcontrollers, introduced in the early 1990s by NEC and still being developed as of 2018.

IEBus Communication bus specification

IEBus is a communication bus specification "between equipments within a vehicle or a chassis" of Renesas Electronics. It defines OSI model layer 1 and layer 2 specification. IEBus is mainly used for car audio and car navigations, which established de facto standard in Japan, though SAE J1850 is major in United States.
IEBus is also used in some vending machines, which major customer is Fuji Electric. Each button on the vending machine has an IEBus ID, i.e. has a controller.
Detailed specification is disclosed to licensees only, but protocol analyzers are provided from some test equipment vendors. Its modulation method is PWM with 6.00 MHz base clock originally, but most of automotive customers use 6.291 MHz, and physical layer is a pair of differential signalling harness. Its physical layer adopts half-duplex, asynchronous, and multi-master communication with CSMA/CD for access control. It allows for up to fifty units on one bus over a maximum length of 150 meters. Two differential signalling lines are used with Bus+ / Bus− naming, sometimes labeled as Data(+) / Data(−).

PowerPC e300

The PowerPC e300 is a family of 32-bit PowerPC microprocessor cores developed by Freescale for primary use in system-on-a-chip (SoC) designs with speed ranging up to 800 MHz, thus making them ideal for embedded applications.

ARM Cortex-M series of processor core models

The ARM Cortex-M is a group of 32-bit RISC ARM processor cores licensed by Arm Holdings. These cores are optimized for low-cost and energy-efficient microcontrollers, which have been embedded in tens of billions of consumer devices. The cores consist of the Cortex-M0, Cortex-M0+, Cortex-M1, Cortex-M3, Cortex-M4, Cortex-M7, Cortex-M23, Cortex-M33, Cortex-M35P, Cortex-M55. The Cortex-M4 / M7 / M33 / M35P / M55 cores have an FPU silicon option, and when included in the silicon these cores are sometimes known as "Cortex-Mx with FPU" or "Cortex-MxF", where 'x' is the core number.

The IBM POWER ISA is a reduced instruction set computer (RISC) instruction set architecture (ISA) developed by IBM. The name is an acronym for Performance Optimization With Enhanced RISC.

RISC-V is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.

Since 1985, numerous processors implementing some version of the MIPS architecture have been designed and widely used.


  1. J-core Open Processor
  2. "CP System III (CPS3) Hardware (Capcom)". System 16. Retrieved 3 August 2019.
  4. "STMicro, Hitachi plan new company to develop RISC cores". EE Times. 3 April 2001. Hitachi created the SH family of processors and developed its first four major iterations, but has worked with ST since 1997, when the companies agreed to share a common high-end microprocessor road map. They jointly developed the 32-bit SH4 RISC processor core, and began development of the SH5 architecture, which will now be completed by SuperH. SuperH's initial product will be the SH4 core. Earlier SH versions will not be part of the spin-off agreement.
  5. "SuperH, Inc. formed by Hitachi and STMicroelectronics to Boost the Proliferation of SuperH™ Cores in Embedded Microprocessor Applications".
  6. "Renesas to take over SuperH core business". EE Times. 28 September 2004.
  7. 1 2 3 4 5 Nathan Willis (June 10, 2015). "Resurrecting the SuperH architecture".
  8. 1 2 "J Cores". j-core. Archived from the original on May 11, 2016. Retrieved April 27, 2016.
  10. V.M. Weaver (17 March 2015). "Exploring the Limits of Code Density (Tech Report with Newest Results)" (PDF).
  11. Kuwabara (25 July 2019). "Korg EMX / ESX Service Manual" (PDF).
  12. "SH-5 CPU Core, Volume1: Architecture" (PDF).
  13. "Wasabi SH-5 Press Release". 8 March 2016.
  14. "GCC 7 Release Series Changes, New Features, and Fixes". 2 February 2018.