|Bits||32-bit (32 → 64)|
|Encoding||SH2: 16-bit instructions; SH2A and newer: mixed 16- and 32-bit instructions|
|Open||Yes, and royalty free|
SuperH (or SH) is a 32-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Hitachi and currently produced by Renesas. It is implemented by microcontrollers and microprocessors for embedded systems.
At the time of introduction, SH2 was notable for having fixed-length 16-bit instructions despite of 32-bit architecture. This was a novel approach: at the time RISC processors instruction width was always dictated by architecture width. In other words, 32-bit RISC processors always used fixed 32-bit instructions.
Later the idea of what is now called compressed instruction set[ citation needed ] was adopted by other companies, most notable example being ARM that licensed relevant SuperH patents to create Thumb instruction set.
As of 2015 [update] , many of the original patents for the SuperH architecture are expiring and the SH2 CPU has been reimplemented as open source hardware under the name J2.
The SuperH processor core family was first developed by Hitachi in the early 1990s. Hitachi has developed a complete group of upward compatible instruction set CPU cores. The SH-1 and the SH-2 were used in the Sega Saturn, Sega 32X and Capcom CPS-3.These cores have 16-bit instructions for better code density than 32-bit instructions, which was a great benefit at the time, due to the high cost of main memory.
A few years later, the SH-3 core was added to the SH CPU family; new features included another interrupt concept, a memory management unit (MMU) and a modified cache concept. The SH-3 core also got a DSP extension, then called SH-3-DSP. With extended data paths for efficient DSP processing, special accumulators and a dedicated MAC-type DSP engine, this core was unifying the DSP and the RISC processor world. A derivative was also used with the original SH-2 core.
Between 1994 and 1996, 35.1 million SuperH devices were shipped worldwide.
For the Dreamcast, Hitachi developed the SH-4 architecture. Superscalar (2-way) instruction execution and a vector floating-point unit (particularly suited to 3d graphics) were the highlights of this architecture. SH-4 based standard chips were introduced around 1998.
The SH-3 and SH-4 architectures support both big-endian and little-endian byte ordering (they are bi-endian).
Hitachi and STMicroelectronics started collaborating as early as 1997 on the design of the SH-4. In early 2001, they formed the IP company SuperH, Inc., which was going to license the SH-4 core to other companies and was developing the SH-5 architecture, the first move of SuperH into the 64-bit area.In 2003, Hitachi and Mitsubishi Electric formed a joint-venture called Renesas Technology, with Hitachi controlling 55% of it. In 2004, Renesas Technology bought STMicroelectronics's share of ownership in the SuperH Inc. and with it the licence to the SH cores. Renesas Technology later became Renesas Electronics, following their merger with NEC Electronics.
The SH-5 design supported two modes of operation. SHcompact mode is equivalent to the user-mode instructions of the SH-4 instruction set. SHmedia mode is very different, using 32-bit instructions with sixty-four 64-bit integer registers and SIMD instructions. In SHmedia mode the destination of a branch (jump) is loaded into a branch register separately from the actual branch instruction. This allows the processor to prefetch instructions for a branch without having to snoop the instruction stream. The combination of a compact 16-bit instruction encoding with a more powerful 32-bit instruction encoding is not unique to SH-5; ARM processors have a 16-bit Thumb mode (ARM licensed several patents from SuperH for Thumb) and MIPS processors have a MIPS-16 mode. However, SH-5 differs because its backward compatibility mode is the 16-bit encoding rather than the 32-bit encoding.
The evolution of the SuperH architecture still continues. The latest evolutionary step happened around 2003 where the cores from SH-2 up to SH-4 were getting unified into a superscalar SH-X core which forms a kind of instruction set superset of the previous architectures.
Today[ when? ], the SuperH CPU cores, architecture and products are with Renesas Electronics, a merger of the Hitachi and Mitsubishi semiconductor groups and the architecture is consolidated around the SH-2, SH-2A, SH-3, SH-4 and SH-4A platforms giving a scalable family.
The last of the SH-2 patents expired in 2014. At LinuxCon Japan 2015, j-core developers presented a cleanroom reimplemention of the SH-2 ISA with extensions (known as the "J2 core" due to the unexpired trademarks).Subsequently, a design walkthrough was presented at ELC 2016.
The open source BSD licensed VHDL code for the J2 core has been proven on Xilinx FPGAs and on ASICs manufactured on TSMC's 180 nm process, and is capable of booting µClinux.J2 is backwards ISA compatible with SH-2, implemented as a 5-stage pipeline with separate Instruction and Data memory interfaces, and a machine generated Instruction Decoder supporting the densely packed and complex (relative to other RISC machines) ISA. Additional instructions are easy to add. J2 implements instructions for dynamic shift (using the SH-3 and later instruction patterns), extended atomic operations (used for threading primitives) and locking/interfaces for symmetric multiprocessor support. Plans to implement the SH-2A (as "J2+") and SH-4 (as "J4") instruction sets as the relevant patents expire in 2016-2017.
Several features of SuperH have been cited as motivations for designing new cores based on this architecture:
The family of SuperH CPU cores includes:
The SH-2 is a 32-bit RISC architecture with a 16-bit fixed instruction length for high code density and features a hardware multiply–accumulate (MAC) block for DSP algorithms and has a five-stage pipeline.
The SH-2 has a cache on all ROM-less devices.
It provides 16 general purpose registers, a vector-base-register, global-base-register, and a procedure register.
Today the SH-2 family stretches from 32 KB of on-board flash up to ROM-less devices. It is used in a variety of different devices with differing peripherals such as CAN, Ethernet, motor-control timer unit, fast ADC and others.
The SH-2A is an upgrade to the SH-2 core that added some 32-bit instructions. It was announced in early 2006.
New features on the SH-2A core include:
The SH-2A family today spans a wide memory field from 16 KB up to and includes many ROM-less variations. The devices feature standard peripherals such as CAN, Ethernet, USB and more as well as more application specific peripherals such as motor control timers, TFT controllers and peripherals dedicated to automotive powertrain applications.
The SH-4 is a 32-bit RISC CPU and was developed for primary use in multimedia applications, such as Sega's Dreamcast and NAOMI game systems. It includes a much more powerful floating-point unit [note] and additional built-in functions, along with the standard 32-bit integer processing and 16-bit instruction size.
SH-4 features include:
^ There is no FPU in the custom SH4 made for Casio, the SH7305.
The SH-5 is a 64-bit RISC CPU.
Almost no non-simulated SH-5 hardware was ever released,and unlike the still live SH-4, support for SH-5 was dropped from gcc.
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IEBus is also used in some vending machines, which major customer is Fuji Electric. Each button on the vending machine has an IEBus ID, i.e. has a controller.
Detailed specification is disclosed to licensees only, but protocol analyzers are provided from some test equipment vendors. Its modulation method is PWM with 6.00 MHz base clock originally, but most of automotive customers use 6.291 MHz, and physical layer is a pair of differential signalling harness. Its physical layer adopts half-duplex, asynchronous, and multi-master communication with CSMA/CD for access control. It allows for up to fifty units on one bus over a maximum length of 150 meters. Two differential signalling lines are used with Bus+ / Bus− naming, sometimes labeled as Data(+) / Data(−).
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Hitachi created the SH family of processors and developed its first four major iterations, but has worked with ST since 1997, when the companies agreed to share a common high-end microprocessor road map. They jointly developed the 32-bit SH4 RISC processor core, and began development of the SH5 architecture, which will now be completed by SuperH. SuperH's initial product will be the SH4 core. Earlier SH versions will not be part of the spin-off agreement.