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In digital electronics, a **binary decoder** is a combinational logic circuit that converts binary information from the n coded inputs to a maximum of 2^{n} unique outputs. They are used in a wide variety of applications, including data multiplexing and data demultiplexing, seven segment displays, and as address decoders for memory and port-mapped I/O.

There are several types of binary decoders, but in all cases a decoder is an electronic circuit with multiple input and multiple output signals, which converts every unique combination of input states to a specific combination of output states. In addition to integer data inputs, some decoders also have one or more "enable" inputs. When the enable input is negated (disabled), all decoder outputs are forced to their inactive states.

Depending on its function, a binary decoder will convert binary information from n input signals to as many as 2^{n} unique output signals. Some decoders have less than 2^{n} output lines; in such cases, at least one output pattern may be repeated for different input values.

A binary decoder is usually implemented as either a stand-alone integrated circuit (IC) or as part of a more complex IC. In the latter case the decoder may be synthesized by means of a hardware description language such as VHDL or Verilog. Widely used decoders are often available in the form of standardized ICs.

A 1-of-n binary decoder has n output bits. This type of decoder asserts exactly one of its n output bits, or none of them, for every integer input value. The "address" (bit number) of the activated output is specified by the integer input value. For example, output bit number 0 is selected when the integer value 0 is applied to the inputs.

Examples of this type of decoder include:

- A
*3-to-8 line decoder*activates one of eight output bits for each input value from 0 to 7 — the range of integer values that can be expressed in three bits. Similarly, a*4-to-16 line decoder*activates one of 16 outputs for each 4-bit input in the integer range [0,15]. - A
*BCD to decimal decoder*has ten output bits. It accepts an input value consisting of a binary-coded decimal integer value and activates one specific, unique output for every input value in the range [0,9]. All outputs are held inactive when a non-decimal value is applied to the inputs. - A demultiplexer is a 1-of-n binary decoder that is used to route a data bit to one of its n outputs while all other outputs remain inactive.

Code translators differ from 1-of-n decoders in that multiple output bits may be active at the same time. An example of this is a *seven-segment decoder*, which converts an integer into the combination of segment control signals needed to display the integer's value on a seven-segment display digit.

One variant of seven-segment decoder is the *BCD to seven-segment decoder*, which translates a binary-coded decimal value into the corresponding segment control signals for input integer values 0 to 9. This decoder function is available in standard ICs such as the CMOS 4511.

Look up in Wiktionary, the free dictionary. decoder |

- Multiplexer
- One-hot, the format of the 1-of-n decoder's output (or the unencoded output of a ring counter)
- Priority encoder
- Sum-addressed decoder

In computing and electronic systems, **binary-coded decimal** (**BCD**) is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed number of bits, usually four or eight. Special bit patterns are sometimes used for a sign or for other indications.

In digital logic and computing, a **counter** is a device which stores the number of times a particular event or process has occurred, often in relationship to a clock. The most common type is a sequential digital logic circuit with an input line called the *clock* and multiple output lines. The values on the output lines represent a number in the binary or BCD number system. Each pulse applied to the clock input increments or decrements the number in the counter.

In electronics, a **multiplexer**, also known as a **data selector**, is a device that selects between several analog or digital input signals and forwards it to a single output line. A multiplexer of inputs has select lines, which are used to select which input line to send to the output. Multiplexers are mainly used to increase the amount of data that can be sent over the network within a certain amount of time and bandwidth. Multiplexers can also be used to implement Boolean functions of multiple variables.

In electronics, an **analog-to-digital converter** is a system that converts an analog signal, such as a sound picked up by a microphone or light entering a digital camera, into a digital signal. An ADC may also provide an isolated measurement such as an electronic device that converts an input analog voltage or current to a digital number representing the magnitude of the voltage or current. Typically the digital output is a two's complement binary number that is proportional to the input, but there are other possibilities.

**Elias γ code** or **Elias gamma code** is a universal code encoding positive integers developed by Peter Elias. It is used most commonly when coding integers whose upper-bound cannot be determined beforehand.

The **ternary** numeral system has three as its base. Analogous to a bit, a ternary digit is a **trit**. One trit is equivalent to log_{2} 3 bits of information.

In electronics, a **digital-to-analog converter** is a system that converts a digital signal into an analog signal. An analog-to-digital converter (ADC) performs the reverse function.

**G.711** is an ITU-T standard (Recommendation) for audio companding, titled **Pulse code modulation (PCM) of voice frequencies**, it is a required standard in many technologies, such as in the H.320 and H.323 standards. It was originally designed for use in telephony and was released for use in 1972. It can also be used for fax communication over IP networks. G.711 is a narrowband audio codec that provides toll-quality audio at 64 kbit/s. G.711 passes audio signals in the range of 300–3400 Hz and samples them at the rate of 8,000 samples per second, with the tolerance on that rate of 50 parts per million (ppm). Non-uniform (logarithmic) quantization with 8 bits is used to represent each sample, resulting in a 64 kbit/s bit rate. There are two slightly different versions: μ-law, which is used primarily in North America and Japan, and A-law, which is in use in most other countries outside North America.

The **4000 series** is a CMOS logic family of integrated circuits (ICs) first introduced in 1968 by RCA. Almost all IC manufacturers active during this initial era fabricated models for this series. It is still in use today.

In computing, a **fixed-point number** representation is a real data type for a number that has a fixed number of digits after the radix point. Fixed-point number representation can be compared to the more complicated floating-point number representation.

A **seven-segment display** is a form of electronic display device for displaying decimal numerals that is an alternative to the more complex dot matrix displays.

In digital circuits and machine learning, **one-hot** is a group of bits among which the legal combinations of values are only those with a single high (1) bit and all the others low (0). A similar implementation in which all bits are '1' except one '0' is sometimes called **one-cold**. In statistics, dummy variables represent a similar technique for representing categorical data.

**Densely packed decimal** (DPD) is an efficient method for binary encoding decimal digits.

**Levenstein coding**, or **Levenshtein coding**, is a universal code encoding the non-negative integers developed by Vladimir Levenshtein.

In computer science, the **double dabble** algorithm is used to convert binary numbers into binary-coded decimal (BCD) notation. It is also known as the **shift-and-add-3 algorithm**, and can be implemented using a small number of gates in computer hardware, but at the expense of high latency.

A **canonical Huffman code** is a particular type of Huffman code with unique properties which allow it to be described in a very compact manner.

In digital logic, a **don't-care term** for a function is an input-sequence for which the function output does not matter. An input that is known never to occur is a **can't-happen term**. Both these types of conditions are treated the same way in logic design and may be referred to collectively as *don't-care conditions* for brevity. The designer of a logic circuit to implement the function need not care about such inputs, but can choose the circuit's output arbitrarily, usually such that the simplest circuit results (minimization). Examples of don't-care terms are the binary values 1010 through 1111 for a function that takes a binary-coded decimal (BCD) value, because a BCD value never takes on such values ; in the pictures, the circuit computing the lower left bar of a 7-segment display can be minimized to *a**b* + *a**c* by an appropriate choice of circuit outputs for *dcba*=1010...1111.

In computing, **decimal32** is a decimal floating-point computer numbering format that occupies 4 bytes in computer memory. It is intended for applications where it is necessary to emulate decimal rounding exactly, such as financial and tax computations. Like the binary16 format, it is intended for memory saving storage.

In computing, **decimal128** is a decimal floating-point computer numbering format that occupies 16 bytes in computer memory. It is intended for applications where it is necessary to emulate decimal rounding exactly, such as financial and tax computations.

An **arithmetic logic unit** (**ALU**) is a combinational digital electronic circuit that performs arithmetic and bitwise operations on integer binary numbers. This is in contrast to a floating-point unit (FPU), which operates on floating point numbers. An ALU is a fundamental building block of many types of computing circuits, including the central processing unit (CPU) of computers, FPUs, and graphics processing units (GPUs). A single CPU, FPU or GPU may contain multiple ALUs.

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