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In electronics, a **multiplexer** (or **mux**) is a device that selects between several analog or digital input signals and forwards it to a single output line.^{ [1] } A multiplexer of inputs has select lines, which are used to select which input line to send to the output.^{ [2] } Multiplexers are mainly used to increase the amount of data that can be sent over the network within a certain amount of time and bandwidth.^{ [1] } A multiplexer is also called a **data selector**. Multiplexers can also be used to implement Boolean functions of multiple variables.

**Electronics** comprises the physics, engineering, technology and applications that deal with the emission, flow and control of electrons in vacuum and matter.

An **analog signal** is any continuous signal for which the time-varying feature (variable) of the signal is a representation of some other time varying quantity, i.e., *analogous* to another time varying signal. For example, in an analog audio signal, the instantaneous voltage of the signal varies continuously with the pressure of the sound waves. It differs from a digital signal, in which the continuous quantity is a representation of a sequence of discrete values which can only take on one of a finite number of values. The term *analog signal* usually refers to electrical signals; however, mechanical, pneumatic, hydraulic, human speech, and other systems may also convey or be considered analog signals.

**Bandwidth** is the difference between the upper and lower frequencies in a continuous band of frequencies. It is typically measured in hertz, and depending on context, may specifically refer to *passband bandwidth* or *baseband bandwidth*. Passband bandwidth is the difference between the upper and lower cutoff frequencies of, for example, a band-pass filter, a communication channel, or a signal spectrum. Baseband bandwidth applies to a low-pass filter or baseband signal; the bandwidth is equal to its upper cutoff frequency.

- Cost saving
- Digital multiplexers
- Chaining multiplexers
- List of ICs which provide multiplexing
- Digital demultiplexers
- List of ICs which provide demultiplexing
- Multiplexers as PLDs
- See also
- References
- Further reading
- External links

An electronic multiplexer makes it possible for several signals to share one device or resource, for example, one A/D converter or one communication line, instead of having one device per input signal.

Conversely, a **demultiplexer** (or **demux**) is a device taking a single input and selecting signals of the output of the compatible **mux**, which is connected to the single input, and a shared selection line. A multiplexer is often used with a complementary demultiplexer on the receiving end.^{ [1] }

An electronic multiplexer can be considered as a multiple-input, single-output switch, and a demultiplexer as a single-input, multiple-output switch.^{ [3] } The schematic symbol for a multiplexer is an isosceles trapezoid with the longer parallel side containing the input pins and the short parallel side containing the output pin.^{ [4] } The schematic on the right shows a 2-to-1 multiplexer on the left and an equivalent switch on the right. The wire connects the desired input to the output.

In Euclidean geometry, an **isosceles trapezoid** is a convex quadrilateral with a line of symmetry bisecting one pair of opposite sides. It is a special case of a trapezoid. Alternatively, it can be defined as a trapezoid in which both legs and both base angles are of the same measure. Note that a non-rectangular parallelogram is not an isosceles trapezoid because of the second condition, or because it has no line of symmetry. In any isosceles trapezoid, two opposite sides are parallel, and the two other sides are of equal length. The diagonals are also of equal length. The base angles of an isosceles trapezoid are equal in measure.

One use for multiplexers is economizing connections over a single channel, by connecting the multiplexer's single output to the demultiplexer's single input. The image to the right demonstrates this benefit. In this case, the cost of implementing separate channels for each data source is higher than the cost and inconvenience of providing the multiplexing/demultiplexing functions.

At the receiving end of the data link a complementary *demultiplexer* is usually required to break the single data stream back down into the original streams. In some cases, the far end system may have functionality greater than a simple demultiplexer; and while the demultiplexing still occurs technically, it may never be implemented discretely. This would be typical when: a multiplexer serves a number of IP network users; and then feeds directly into a router, which immediately reads the content of the entire link into its routing processor; and then does the demultiplexing in memory from where it will be converted directly into IP sections.

In telecommunication a **data link** is the means of connecting one location to another for the purpose of transmitting and receiving digital information. It can also refer to a set of electronics assemblies, consisting of a transmitter and a receiver and the interconnecting data telecommunication circuit. These are governed by a link protocol enabling digital data to be transferred from a data source to a data sink.

The **Internet Protocol** (**IP**) is the principal communications protocol in the Internet protocol suite for relaying datagrams across network boundaries. Its routing function enables internetworking, and essentially establishes the Internet.

A **router** is a networking device that forwards data packets between computer networks. Routers perform the traffic directing functions on the Internet. Data sent through the internet, such as a web page or email, is in the form of data packets. A packet is typically forwarded from one router to another router through the networks that constitute an internetwork until it reaches its destination node.

Often, a multiplexer and demultiplexer are combined together into a single piece of equipment, which is conveniently referred to as a "multiplexer". Both circuit elements are needed at both ends of a transmission link because most communications systems transmit in both directions.

A **duplex** communication system is a point-to-point system composed of two or more connected parties or devices that can communicate with one another in both directions. Duplex systems are employed in many communications networks, either to allow for simultaneous communication in both directions between two connected parties or to provide a reverse path for the monitoring and remote adjustment of equipment in the field. There are two types of duplex communication systems: full-duplex (FDX) and half-duplex (HDX).

In analog circuit design, a multiplexer is a special type of analog switch that connects one signal selected from several inputs to a single output.

In digital circuit design, the selector wires are of digital value. In the case of a 2-to-1 multiplexer, a logic value of 0 would connect to the output while a logic value of 1 would connect to the output. In larger multiplexers, the number of selector pins is equal to where is the number of inputs.

For example, 9 to 16 inputs would require no fewer than 4 selector pins and 17 to 32 inputs would require no fewer than 5 selector pins. The binary value expressed on these selector pins determines the selected input pin.

A 2-to-1 multiplexer has a boolean equation where and are the two inputs, is the selector input, and is the output:

Which can be expressed as a truth table:

0 | 0 | 0 | 0 |

0 | 0 | 1 | 0 |

0 | 1 | 0 | 1 |

0 | 1 | 1 | 1 |

1 | 0 | 0 | 0 |

1 | 0 | 1 | 1 |

1 | 1 | 0 | 0 |

1 | 1 | 1 | 1 |

Or, in simpler notation:

0 | A |

1 | B |

These tables show that when then but when then . A straightforward realization of this 2-to-1 multiplexer would need 2 AND gates, an OR gate, and a NOT gate. While this is mathematically correct, a direct physical implementation would be prone to race conditions that require additional gates to suppress.^{ [5] }

Larger multiplexers are also common and, as stated above, require selector pins for inputs. Other common sizes are 4-to-1, 8-to-1, and 16-to-1. Since digital logic uses binary values, powers of 2 are used (4, 8, 16) to maximally control a number of inputs for the given number of selector inputs.

- 4-to-1 mux
- 8-to-1 mux
- 16-to-1 mux

The boolean equation for a 4-to-1 multiplexer is:

The following 4-to-1 multiplexer is constructed from 3-state buffers and AND gates (the AND gates are acting as the decoder):

The subscripts on the inputs indicate the decimal value of the binary control inputs at which that input is let through.

Larger Multiplexers can be constructed by using smaller multiplexers by chaining them together. For example, an 8-to-1 multiplexer can be made with two 4-to-1 and one 2-to-1 multiplexers. The two 4-to-1 multiplexer outputs are fed into the 2-to-1 with the selector pins on the 4-to-1's put in parallel giving a total number of selector inputs to 3, which is equivalent to an 8-to-1.

The 7400 series has several ICs that contain multiplexer(s):

IC No. | Function | Output State |
---|---|---|

74157 | Quad 2:1 mux. | Output same as input given |

74158 | Quad 2:1 mux. | Output is inverted input |

74153 | Dual 4:1 mux. | Output same as input |

74352 | Dual 4:1 mux. | Output is inverted input |

74151A | 8:1 mux. | Both outputs available (i.e., complementary outputs) |

74151 | 8:1 mux. | Output is inverted input |

74150 | 16:1 mux. | Output is inverted input |

Demultiplexers take one data input and a number of selection inputs, and they have several outputs. They forward the data input to one of the outputs depending on the values of the selection inputs. Demultiplexers are sometimes convenient for designing general purpose logic, because if the demultiplexer's input is always true, the demultiplexer acts as a decoder. This means that any function of the selection bits can be constructed by logically OR-ing the correct set of outputs.

If X is the input and S is the selector, and A and B are the outputs:

The 7400 series has several ICs that contain demultiplexer(s):

IC No. (7400) | IC No. (4000) | Function | Output State |
---|---|---|---|

74139 | Dual 1:4 demux. | Output is inverted input | |

74156 | Dual 1:4 demux. | Output is open collector | |

74138 | 1:8 demux. | Output is inverted input | |

74238 | 1:8 demux. | ||

74154 | 1:16 demux. | Output is inverted input | |

74159 | CD4514/15 | 1:16 demux. | Output is open collector and same as input |

Multiplexers can also be used as programmable logic devices, specifically to implement Boolean functions. Any Boolean function of *n* variables and one result can be implemented with a multiplexer with *n* selector inputs. The variables are connected to the selector inputs, and the function result, 0 or 1, for each possible combination of selector inputs is connected to the corresponding data input. This is especially useful in situations when cost is a factor, for modularity, and for ease of modification. If one of the variables (for example, *D*) is also available inverted, a multiplexer with *n*-1 selector inputs is sufficient; the data inputs are connected to 0, 1, *D*, or ~*D*, according to the desired output for each combination of the selector inputs.^{ [6] }

- Digital subscriber line access multiplexer (DSLAM)
- Inverse multiplexer
- Multiplexing
- Priority encoder
- Rule 184, a cellular automaton in which each cell acts as a multiplexer for the values from the two adjacent cells
- Statistical multiplexer

In logic, mathematics and linguistics, And (∧) is the truth-functional operator of **logical conjunction**; the *and* of a set of operands is true if and only if *all* of its operands are true. The logical connective that represents this operator is typically written as ∧ or ⋅ .

In logic, a **logical connective** is a symbol or word used to connect two or more sentences in a grammatically valid way, such that the value of the compound sentence produced depends only on that of the original sentences and on the meaning of the connective.

In logic, a **many-valued logic** is a propositional calculus in which there are more than two truth values. Traditionally, in Aristotle's logical calculus, there were only two possible values for any proposition. Classical two-valued logic may be extended to ** n-valued logic** for

In Boolean logic, a formula is in **conjunctive normal form** (**CNF**) or **clausal normal form** if it is a conjunction of one or more clauses, where a clause is a disjunction of literals; otherwise put, it is **an AND of ORs**. As a canonical normal form, it is useful in automated theorem proving and circuit theory.

In digital circuit theory, **combinational logic** is a type of digital logic which is implemented by Boolean circuits, where the output is a pure function of the present input only. This is in contrast to sequential logic, in which the output depends not only on the present input but also on the history of the input. In other words, sequential logic has *memory* while combinational logic does not.

In digital logic, an **inverter** or **NOT gate** is a logic gate which implements logical negation. The truth table is shown on the right.

**Intuitionistic logic**, sometimes more generally called **constructive logic**, refers to systems of symbolic logic that differ from the systems used for classical logic by more closely mirroring the notion of constructive proof. In particular, systems of intuitionistic logic do not include the law of the excluded middle and double negation elimination, which are fundamental inference rules in classical logic.

In mathematics, a **Heyting algebra** is a bounded lattice equipped with a binary operation *a* → *b* of *implication* such that *c* ∧ *a* ≤ *b* is equivalent to *c* ≤ *a* → *b*. From a logical standpoint, *A* → *B* is by this definition the weakest proposition for which modus ponens, the inference rule *A* → *B*, *A* ⊢ *B*, is sound. Equivalently a Heyting algebra is a residuated lattice whose monoid operation is ∧; yet another definition is as a posetal cartesian closed category with all finite sums. Like Boolean algebras, Heyting algebras form a variety axiomatizable with finitely many equations. Heyting algebras were introduced by Arend Heyting (1930) to formalize intuitionistic logic.

In digital electronics, a **binary decoder** is a combinational logic circuit that converts binary information from the n coded inputs to a maximum of 2^{n} unique outputs. They are used in a wide variety of applications, including data demultiplexing, seven segment displays, and memory address decoding.

In logic, a **truth function** is a function that accepts truth values as input and produces a truth value as output, i.e., the input and output are all truth values. The typical example is in propositional logic, wherein a compound statement is constructed by one or two statements connected by a logical connective; if the truth value of the compound statement is determined by the truth value(s) of the constituent statement(s), the compound statement is called a **truth function**, and the logical connective is said to be **truth functional**.

**System F**, also known as the (**Girard–Reynolds**) **polymorphic lambda calculus** or the **second-order lambda calculus**, is a typed lambda calculus that differs from the simply typed lambda calculus by the introduction of a mechanism of universal quantification over types. System F thus formalizes the notion of parametric polymorphism in programming languages, and forms a theoretical basis for languages such as Haskell and ML. System F was discovered independently by logician Jean-Yves Girard (1972) and computer scientist John C. Reynolds (1974).

Because the NAND function has functional completeness all logic systems can be converted into NAND gates – the mathematical proof for this was published by Henry M. Sheffer in 1913 in the *Transactions of the American Mathematical Society*. This is also true for NOR gates. In principle, any combinatorial logic function can be realized with enough NAND gates.

In logic, a **functionally complete** set of logical connectives or Boolean operators is one which can be used to express all possible truth tables by combining members of the set into a Boolean expression. A well-known complete set of connectives is { AND, NOT }, consisting of binary conjunction and negation. Each of the singleton sets { NAND } and { NOR } is functionally complete.

In abstract algebra, a **skew lattice** is an algebraic structure that is a non-commutative generalization of a lattice. While the term *skew lattice* can be used to refer to any non-commutative generalization of a lattice, since 1989 it has been used primarily as follows.

The **Intel 8255** Programmable Peripheral Interface (PPI) chip was developed and manufactured by Intel in the first half of the 1970s for the Intel 8080 microprocessor. The 8255 provides 24 parallel input/output lines with a variety of programmable operating modes.

In logic, **converse nonimplication** is a logical connective which is the negation of converse implication.

**AND-OR-Invert** (AOI) logic and AOI gates are two-level compound logic functions constructed from the combination of one or more AND gates followed by a NOR gate. Construction of AOI cells is particularly efficient using CMOS technology where the total number of transistor gates can be compared to the same construction using NAND logic or NOR logic. The complement of AOI Logic is OR-AND-Invert (OAI) logic where the OR gates precede a NAND gate.

The **Tseytin transformation**, alternatively written **Tseitin transformation**, takes as input an arbitrary combinatorial logic circuit and produces a boolean formula in conjunctive normal form (CNF), which can be solved by a CNF-SAT solver. The length of the formula is linear in the size of the circuit. Input vectors that make the circuit output "true" are in 1-to-1 correspondence with assignments that satisfy the formula. This reduces the problem of circuit satisfiability on any circuit to the satisfiability problem on 3-CNF formulas.

**Łukasiewicz–Moisil algebras** were introduced in the 1940s by Grigore Moisil in the hope of giving algebraic semantics for the *n*-valued Łukasiewicz logic. However, in 1956 Alan Rose discovered that for *n* ≥ 5, the Łukasiewicz–Moisil algebra does not model the Łukasiewicz logic. A faithful model for the ℵ_{0}-valued (infinitely-many-valued) Łukasiewicz–Tarski logic was provided by C. C. Chang's MV-algebra, introduced in 1958. For the axiomatically more complicated (finite) *n*-valued Łukasiewicz logics, suitable algebras were published in 1977 by Revaz Grigolia and called MV_{n}-algebras. MV_{n}-algebras are a subclass of LM_{n}-algebras, and the inclusion is strict for *n* ≥ 5. In 1982 Roberto Cignoli published some additional constraints that added to LM_{n}-algebras produce proper models for *n*-valued Łukasiewicz logic; Cignoli called his discovery **proper Łukasiewicz algebras**.

In mathematics and mathematical logic, **Boolean algebra** is the branch of algebra in which the values of the variables are the truth values *true* and *false*, usually denoted 1 and 0 respectively. Instead of elementary algebra where the values of the variables are numbers, and the prime operations are addition and multiplication, the main operations of Boolean algebra are the conjunction *and* denoted as ∧, the disjunction *or* denoted as ∨, and the negation *not* denoted as ¬. It is thus a formalism for describing logical operations in the same way that elementary algebra describes numerical operations.

- 1 2 3 Dean, Tamara (2010).
*Network+ Guide to Networks*. Delmar. pp. 82–85. - ↑ Debashis, De (2010).
*Basic Electronics*. Dorling Kindersley. p. 557. - ↑ Lipták, Béla (2002).
*Instrument engineers' handbook: Process software and digital networks*. CRC Press. p. 343. - ↑ Harris, David (2007).
*Digital Design and Computer Architecture*. Penrose. p. 79. - ↑ Crowe, John and Barrie Hayes-Gill (1998)
*Introduction to Digital Electronics*pp. 111-113 - ↑ Donald E. Lancaster (1975).
*The TTL Cookbook*. Howard W. Sams & Co. pp. 140–143.

- M. Morris Mano; Charles R. Kime (2008).
*Logic and Computer Design Fundamentals*(4 ed.). Prentice Hall. ISBN 0-13-198926-X.

*multiplexer*at Wiktionary

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