An instruction set architecture (ISA) is an abstract model of a computer, also referred to as computer architecture. A realization of an ISA is called an implementation. An ISA permits multiple implementations that may vary in performance, physical size, and monetary cost (among other things); because the ISA serves as the interface between software and hardware. Software that has been written for an ISA can run on different implementations of the same ISA. This has enabled binary compatibility between different generations of computers to be easily achieved, and the development of computer families. Both of these developments have helped to lower the cost of computers and to increase their applicability. For these reasons, the ISA is one of the most important abstractions in computing today.
An ISA defines everything a machine language programmer needs to know in order to program a computer. What an ISA defines differs between ISAs; in general, ISAs define the supported data types, what state there is (such as the main memory and registers) and their semantics (such as the memory consistency and addressing modes), the instruction set (the set of machine instructions that comprises a computer's machine language), and the input/output model.
In the early decades of computing, there were computers that used binary, decimal [1] and even ternary. [2] [3] Contemporary computers are almost exclusively binary.
Characters are encoded as strings of bits or digits, using a wide variety of character sets; even within a single manufacturer there were character set differences.
Integers are encoded with a variety of representations, including Sign-magnitude, Ones' complement, Two's complement, Offset binary, Nines' complement and Ten's complement.
Similarly, floating point numbers are encoded with a variety of representations for the sign, exponent and mantissa. In contemporary machines IBM hexadecimal floating-point and IEEE 754 floating point have largely supplanted older formats.
Addresses are typically unsigned integers generated from a combination of fields in an instruction, data from registers and data from storage; the details vary depending on the architecture.
Computer architectures are often described as n-bit architectures. In the first 3⁄4 of the 20th century, n is often 12, 18, 24, 30, 36, 48 or 60. In the last 1⁄3 of the 20th century, n is often 8, 16, or 32, and in the 21st century, n is often 16, 32 or 64, but other sizes have been used (including 6, 39, 128). This is actually a simplification as computer architecture often has a few more or less "natural" data sizes in the instruction set, but the hardware implementation of these may be very different. Many instruction set architectures have instructions that, on some implementations of that instruction set architecture, operate on half and/or twice the size of the processor's major internal datapaths. Examples of this are the Z80, MC68000, and the IBM System/360. On these types of implementations, a twice as wide operation typically also takes around twice as many clock cycles (which is not the case on high performance implementations). On the 68000, for instance, this means 8 instead of 4 clock ticks, and this particular chip may be described as a 32-bit architecture with a 16-bit implementation. The IBM System/360 instruction set architecture is 32-bit, but several models of the System/360 series, such as the IBM System/360 Model 30, have smaller internal data paths, while others, such as the 360/195, have larger internal data paths. The external databus width is not used to determine the width of the architecture; the NS32008, NS32016 and NS32032 were basically the same 32-bit chip with different external data buses; the NS32764 had a 64-bit bus, and used 32-bit register. Early 32-bit microprocessors often had a 24-bit address, as did the System/360 processors.
In the first 3⁄4 of the 20th century, word oriented decimal computers typically had 10 digit [4] [5] [6] words with a separate sign, using all ten digits in integers and using two digits for exponents [7] [5] in floating point numbers.
An architecture may use "big" or "little" endianness, or both, or be configurable to use either. Little-endian processors order bytes in memory with the least significant byte of a multi-byte value in the lowest-numbered memory location. Big-endian architectures instead arrange bytes with the most significant byte at the lowest-numbered address. The x86 architecture as well as several 8-bit architectures are little-endian. Most RISC architectures (SPARC, Power, PowerPC, MIPS) were originally big-endian (ARM was little-endian), but many (including ARM) are now configurable as either.
Endianness only applies to processors that allow individual addressing of units of data (such as bytes) that are smaller than some of the data formats.
In some architectures, an instruction has a single opcode. In others, some instructions have an opcode and one or more modifiers. E.g., on the IBM System/370, byte 0 is the opcode but when byte 0 is a B216 then byte 1 selects a specific instruction, e.g., B20516 is store clock (STCK).
Architectures typically allow instructions to include some combination of operand addressing modes
The number of operands is one of the factors that may give an indication about the performance of the instruction set. A three-operand architecture (2-in, 1-out) will allow
A := B + C
to be computed in one instruction
ADD B, C, A
A two-operand architecture (1-in, 1-in-and-out) will allow
A := A + B
to be computed in one instruction
ADD B, A
but requires that
A := B + C
be done in two instructions
MOVE B, A ADD C, A
As can be seen in the table below some instructions sets keep to a very simple fixed encoding length, and other have variable-length. Usually it is RISC architectures that have fixed encoding length and CISC architectures that have variable length, but not always.
This section may be confusing or unclear to readers. In particular, Open and Royalty free are not defined and most entries are unsourced.(October 2021) |
The table below compares basic information about instruction set architectures.
Notes:
Archi- tecture | Bits | Version | Intro- duced | Max # operands | Type | Design | Registers (excluding FP/vector) | Instruction encoding | Branch evaluation | Endian- ness | Extensions | Open | Royalty free |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
6502 | 8 | 1975 | 1 | Register–Memory | CISC | 3 | Variable (8- to 24-bit) | Condition register | Little | ||||
6800 | 8 | 1974 | 1 | Register–Memory | CISC | 3 | Variable (8- to 24-bit) | Condition register | Big | ||||
6809 | 8 | 1978 | 1 | Register–Memory | CISC | 5 | Variable (8- to 32-bit) | Condition register | Big | ||||
680x0 | 32 | 1979 | 2 | Register–Memory | CISC | 8 data and 8 address | Variable | Condition register | Big | ||||
8080 | 8 | 1974 | 2 | Register–Memory | CISC | 7 | Variable (8 to 24 bits) | Condition register | Little | ||||
8051 | 32 (8→32) | 1977? | 1 | Register–Register | CISC |
| Variable (8 to 24 bits) | Compare and branch | Little | ||||
x86 | 16, 32, 64 (16→32→64) | v4 (x86-64) | 1978 | 2 (integer) 3 (AVX) [a] 4 (FMA4 and VPBLENDVPx ) [8] | Register–Memory | CISC |
| Variable(8086 ~ 80386: variable between 1 and 6 bytes /w MMU + intel SDK, 80486: 2 to 5 bytes with prefix, pentium and onward: 2 to 4 bytes with prefix, x64: 4 bytes prefix, third party x86 emulation: 1 to 15 bytes w/o prefix & MMU . SSE/MMX: 4 bytes /w prefix AVX: 8 Bytes /w prefix) | Condition code | Little | x87, IA-32, MMX, 3DNow!, SSE, SSE2, PAE, x86-64, SSE3, SSSE3, SSE4, BMI, AVX, AES, FMA, XOP, F16C | No | No |
Alpha | 64 | 1992 | 3 | Register–Register | RISC | 32 (including "zero") | Fixed (32-bit) | Condition register | Bi | MVI, BWX, FIX, CIX | No | ||
ARC | 16/32/64 (32→64) | ARCv3 [9] | 1996 | 3 | Register–Register | RISC | 16 or 32 including SP user can increase to 60 | Variable (16- or 32-bit) | Compare and branch | Bi | APEX User-defined instructions | ||
ARM/A32 | 32 | ARMv1–v9 | 1983 | 3 | Register–Register | RISC |
| Fixed (32-bit) | Condition code | Bi | NEON, Jazelle, VFP, TrustZone, LPAE | No | |
Thumb/T32 | 32 | ARMv4T-ARMv8 | 1994 | 3 | Register–Register | RISC |
| Thumb: Fixed (16-bit), Thumb-2: Variable (16- or 32-bit) | Condition code | Bi | NEON, Jazelle, VFP, TrustZone, LPAE | No | |
Arm64/A64 | 64 | v8.9-A/v9.4-A, [10] Armv8-R [11] | 2011 [12] | 3 | Register–Register | RISC | 32 (including the stack pointer/"zero" register) | Fixed (32-bit), Variable (32-bit or 64-bit for FMA4 with 32-bit prefix [13] ) | Condition code | Bi | SVE and SVE2 | No | |
AVR | 8 | 1997 | 2 | Register–Register | RISC | 32 16 on "reduced architecture" | Variable (mostly 16-bit, four instructions are 32-bit) | Condition register, skip conditioned on an I/O or general purpose register bit, compare and skip | Little | ||||
AVR32 | 32 | Rev 2 | 2006 | 2–3 | RISC | 15 | Variable [14] | Big | Java virtual machine | ||||
Blackfin | 32 | 2000 | 3 [15] | Register–Register | RISC [16] | 2 accumulators 8 data registers 8 pointer registers 4 index registers 4 buffer registers | Variable (16- or 32-bit) | Condition code | Little [17] | ||||
CDC Upper 3000 series | 48 | 1963 | 3 | Register–Memory | CISC | 48-bit A reg., 48-bit Q reg., 6 15-bit B registers, miscellaneous | Variable (24- or 48-bit) | Multiple types of jump and skip | Big | ||||
CDC 6000 Central Processor (CP) | 60 | 1964 | 3 | Register–Register | n/a [b] | 24 (8 18-bit address reg., 8 18-bit index reg., 8 60-bit operand reg.) | Variable (15-, 30-, or 60-bit) | Compare and branch | n/a [c] | Compare/Move Unit | No | No | |
CDC 6000 Peripheral Processor (PP) | 12 | 1964 | 1 or 2 | Register–Memory | CISC | 1 18-bit A register, locations 1–63 serve as index registers for some instructions | Variable (12- or 24-bit) | Test A register, test channel | n/a [d] | additional Peripheral Processing Units | No | No | |
Crusoe (native VLIW) | 32 [18] | 2000 | 1 | Register–Register | VLIW [18] [19] | Variable (64- or 128-bit in native mode, 15 bytes in x86 emulation) [19] | Condition code [18] | Little | |||||
Elbrus 2000 (native VLIW) | 64 | v6 | 2007 | 1 | Register–Register [18] | VLIW | 8–64 | 64 | Condition code | Little | Just-in-time dynamic translation: x87, IA-32, MMX, SSE, SSE2, x86-64, SSE3, AVX | No | No |
DLX | 32 | ? | 1990 | 3 | ? | RISC | 32 | Fixed (32-bit) | ? | Big | ? | Yes | ? |
eSi-RISC | 16/32 | 2009 | 3 | Register–Register | RISC | 8–72 | Variable (16- or 32-bit) | Compare and branch and condition register | Bi | User-defined instructions | No | No | |
iAPX 432 [20] | 32 | 1981 | 3 | Stack machine | CISC | 0 | Variable (6 to 321 bits) | No | No | ||||
Itanium (IA-64) | 64 | 2001 | Register–Register | EPIC | 128 | Fixed (128-bit bundles with 5-bit template tag and 3 instructions, each 41-bit long) | Condition register | Bi (selectable) | Intel Virtualization Technology | No | No | ||
LoongArch | 32, 64 | 2021 | 4 | Register–Register | RISC | 32 (including "zero") | Fixed (32-bit) | Little | No | No | |||
M32R | 32 | 1997 | 3 | Register–Register | RISC | 16 | Variable (16- or 32-bit) | Condition register | Bi | ||||
m88k | 32 | 1988 | 3 | Register–Register | RISC | Fixed (32-bit) | Big | ||||||
Mico32 | 32 | ? | 2006 | 3 | Register–Register | RISC | 32 [21] | Fixed (32-bit) | Compare and branch | Big | User-defined instructions | Yes [22] | Yes |
MIPS | 64 (32→64) | 6 [23] [24] | 1981 | 1–3 | Register–Register | RISC | 4–32 (including "zero") | Fixed (32-bit) | Condition register | Bi | MDMX, MIPS-3D | No | No [25] [26] |
MMIX | 64 | ? | 1999 | 3 | Register–Register | RISC | 256 | Fixed (32-bit) | Condition register | Big | ? | Yes | Yes |
Nios II | 32 | ? | 2000 | 3 | Register–Register | RISC | 32 | Fixed (32-bit) | Condition register | Little | Soft processor that can be instantiated on an Altera FPGA device | No | On Altera/Intel FPGA only |
NS320xx | 32 | 1982 | 5 | Memory–Memory | CISC | 8 | Variable Huffman coded, up to 23 bytes long | Condition code | Little | BitBlt instructions | |||
OpenRISC | 32, 64 | 1.4 [27] | 2000 | 3 | Register–Register | RISC | 16 or 32 | Fixed | Condition code | Bi | ? | Yes | Yes |
PA-RISC (HP/PA) | 64 (32→64) | 2.0 | 1986 | 3 | Register–Register | RISC | 32 | Fixed (32-bit) | Compare and branch | Big → Bi | MAX | No | |
PDP-5 [28] PDP-8 [29] | 12 | 1963 | Register–Memory | CISC | 1 accumulator 1 multiplier quotient register | Fixed (12-bit) | Condition register Test and branch | EAE (Extended Arithmetic Element) | |||||
PDP-11 | 16 | 1970 | 2 | Memory–Memory | CISC | 8 (includes program counter and stack pointer, though any register can act as stack pointer) | Variable (16-, 32-, or 48-bit) | Condition code | Little | Extended Instruction Set, Floating Instruction Set, Floating Point Processor, Commercial Instruction Set | No | No | |
POWER, PowerPC, Power ISA | 32/64 (32→64) | 3.1 [30] | 1990 | 3 (mostly). FMA, LD/ST-Update | Register–Register | RISC | 32 GPR, 8 4-bit Condition Fields, Link Register, Counter Register | Fixed (32-bit), Variable (32- or 64-bit with the 32-bit prefix [30] ) | Condition code, Branch-Counter auto-decrement | Bi | AltiVec, APU, VSX, Cell, Floating-point, Matrix Multiply Assist | Yes | Yes |
RISC-V | 32, 64, 128 | 20191213 [31] | 2010 | 3 | Register–Register | RISC | 32 (including "zero") | Variable | Compare and branch | Little | ? | Yes | Yes |
RX | 64/32/16 | 2000 | 3 | Memory–Memory | CISC | 4 integer + 4 address | Variable | Compare and branch | Little | No | |||
S+core | 16/32 | 2005 | RISC | Little | |||||||||
SPARC | 64 (32→64) | OSA2017 [32] | 1985 | 3 | Register–Register | RISC | 32 (including "zero") | Fixed (32-bit) | Condition code | Big → Bi | VIS | Yes | Yes [33] |
SuperH (SH) | 32 | ? | 1994 | 2 | Register–Register Register–Memory | RISC | 16 | Fixed (16- or 32-bit), Variable | Condition code (single bit) | Bi | ? | Yes | Yes |
System/360 System/370 System/390 z/Architecture | 64 (32→64) | 1964 | 2 (most) 3 (FMA, distinct operand facility) 4 (some vector inst.) | Register–Memory Memory–Memory Register–Register | CISC | 16 general 16 control (S/370 and later) 16 access (ESA/370 and later) | Variable (16-, 32-, or 48-bit) | Condition code, compare and branch auto increment, Branch-Counter auto-decrement | Big | No | No | ||
TMS320 C6000 series | 32 | 1983 | 3 | Register-Register | VLIW | 32 on C67x 64 on C67x+ | Fixed (256-bit bundles with 8 instructions, each 32-bit long) | Condition register | Bi | No | No | ||
Transputer | 32 (4→64) | 1987 | 1 | Stack machine | MISC | 3 (as stack) | Fixed (8-bit) | Compare and branch | Little | ||||
VAX | 32 | 1977 | 6 | Memory–Memory | CISC | 16 | Variable | Condition code, compare and branch | Little | No | |||
Z80 | 8 | 1976 | 2 | Register–Memory | CISC | 17 | Variable (8 to 32 bits) | Condition register | Little | ||||
Archi- tecture | Bits | Version | Intro- duced | Max # operands | Type | Design | Registers (excluding FP/vector) | Instruction encoding | Branch evaluation | Endian- ness | Extensions | Open | Royalty free |
Alpha is a 64-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC). Alpha was designed to replace 32-bit VAX complex instruction set computers (CISC) and to be a highly competitive RISC processor for Unix workstations and similar markets.
PowerPC is a reduced instruction set computer (RISC) instruction set architecture (ISA) created by the 1991 Apple–IBM–Motorola alliance, known as AIM. PowerPC, as an evolving instruction set, has been named Power ISA since 2006, while the old name lives on as a trademark for some implementations of Power Architecture–based processors.
In electronics and computer science, a reduced instruction set computer (RISC) is a computer architecture designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set computer (CISC), a RISC computer might require more instructions in order to accomplish a task because the individual instructions are written in simpler code. The goal is to offset the need to process more instructions by increasing the speed of each instruction, in particular by implementing an instruction pipeline, which may be simpler to achieve given simpler instructions.
x86 is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel based on the 8086 microprocessor and its 8-bit-external-bus variant, the 8088. The 8086 was introduced in 1978 as a fully 16-bit extension of 8-bit Intel's 8080 microprocessor, with memory segmentation as a solution for addressing more memory than can be covered by a plain 16-bit address. The term "x86" came into being because the names of several successors to Intel's 8086 processor end in "86", including the 80186, 80286, 80386 and 80486. Colloquially, their names were "186", "286", "386" and "486".
SPARC is a reduced instruction set computer (RISC) instruction set architecture originally developed by Sun Microsystems. Its design was strongly influenced by the experimental Berkeley RISC system developed in the early 1980s. First developed in 1986 and released in 1987, SPARC was one of the most successful early commercial RISC systems, and its success led to the introduction of similar RISC designs from many vendors through the 1980s and 1990s.
In computing, endianness is the order in which bytes within a word of digital data are transmitted over a data communication medium or addressed in computer memory, counting only byte significance compared to earliness. Endianness is primarily expressed as big-endian (BE) or little-endian (LE), terms introduced by Danny Cohen into computer science for data ordering in an Internet Experiment Note published in 1980. The adjective endian has its origin in the writings of 18th century Anglo-Irish writer Jonathan Swift. In the 1726 novel Gulliver's Travels, he portrays the conflict between sects of Lilliputians divided into those breaking the shell of a boiled egg from the big end or from the little end. By analogy, a CPU may read a digital word big end first, or little end first.
In computer science, an instruction set architecture (ISA) is an abstract model that generally defines how software controls the CPU in a computer or a family of computers. A device or program that executes instructions described by that ISA, such as a central processing unit (CPU), is called an implementation of that ISA.
AltiVec is a single-precision floating point and integer SIMD instruction set designed and owned by Apple, IBM, and Freescale Semiconductor — the AIM alliance. It is implemented on versions of the PowerPC processor architecture, including Motorola's G4, IBM's G5 and POWER6 processors, and P.A. Semi's PWRficient PA6T. AltiVec is a trademark owned solely by Freescale, so the system is also referred to as Velocity Engine by Apple and VMX by IBM and P.A. Semi.
In computer architecture, 32-bit computing refers to computer systems with a processor, memory, and other major system components that operate on data in 32-bit units. Compared to smaller bit widths, 32-bit computers can perform large calculations more efficiently and process more data per clock cycle. Typical 32-bit personal computers also have a 32-bit address bus, permitting up to 4 GB of RAM to be accessed, far more than previous generations of system architecture allowed.
SuperH is a 32-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Hitachi and currently produced by Renesas. It is implemented by microcontrollers and microprocessors for embedded systems.
In computer architecture, 64-bit integers, memory addresses, or other data units are those that are 64 bits wide. Also, 64-bit central processing units (CPU) and arithmetic logic units (ALU) are those that are based on processor registers, address buses, or data buses of that size. A computer that uses such a processor is a 64-bit computer.
An index register in a computer's CPU is a processor register used for pointing to operand addresses during the run of a program. It is useful for stepping through strings and arrays. It can also be used for holding loop iterations and counters. In some architectures it is used for read/writing blocks of memory. Depending on the architecture it may be a dedicated index register or a general-purpose register. Some instruction sets allow more than one index register to be used; in that case additional instruction fields may specify which index registers to use.
A processor register is a quickly accessible location available to a computer's processor. Registers usually consist of a small amount of fast storage, although some registers have specific hardware functions, and may be read-only or write-only. In computer architecture, registers are typically addressed by mechanisms other than main memory, but may in some cases be assigned a memory address e.g. DEC PDP-10, ICT 1900.
Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how the machine language instructions in that architecture identify the operand(s) of each instruction. An addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere.
In computer engineering, an orthogonal instruction set is an instruction set architecture where all instruction types can use all addressing modes. It is "orthogonal" in the sense that the instruction type and the addressing mode may vary independently. An orthogonal instruction set does not impose a limitation that requires a certain instruction to use a specific register so there is little overlapping of instruction functionality.
In computer architecture, 128-bit integers, memory addresses, or other data units are those that are 128 bits wide. Also, 128-bit central processing unit (CPU) and arithmetic logic unit (ALU) architectures are those that are based on registers, address buses, or data buses of that size.
The history of general-purpose CPUs is a continuation of the earlier history of computing hardware.
RISC-V is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. The project began in 2010 at the University of California, Berkeley, transferred to the RISC-V Foundation in 2015, and on to RISC-V International, a Swiss non-profit entity, in November 2019. Like several other RISC ISAs, e.g. Amber (ARMv2) or OpenRISC, RISC-V is offered under royalty-free open-source licenses. The documents defining the RISC-V instruction set architecture (ISA) are offered under a Creative Commons license or a BSD License.
Power ISA is a reduced instruction set computer (RISC) instruction set architecture (ISA) currently developed by the OpenPOWER Foundation, led by IBM. It was originally developed by IBM and the now-defunct Power.org industry group. Power ISA is an evolution of the PowerPC ISA, created by the mergers of the core PowerPC ISA and the optional Book E for embedded applications. The merger of these two components in 2006 was led by Power.org founders IBM and Freescale Semiconductor.
A compressed instruction set, or simply compressed instructions, are a variation on a microprocessor's instruction set architecture (ISA) that allows instructions to be represented in a more compact format. In most real-world examples, compressed instructions are 16 bits long in a processor that would otherwise use 32-bit instructions. The 16-bit ISA is a subset of the full 32-bit ISA, not a separate instruction set. The smaller format requires some tradeoffs: generally, there are fewer instructions available, and fewer processor registers can be used.