This article uses HTML markup . (February 2019)
A MOS 6502 processor in a DIP-40 plastic package. The four-digit date code indicates it was made in the 45th week of 1985
|Max. CPU clock rate||1 MHz to 3 MHz|
|Instruction set||MOS 6502|
The MOS Technology 6502 (typically "sixty-five-oh-two" or "six-five-oh-two")is an 8-bit microprocessor that was designed by a small team led by Chuck Peddle for MOS Technology. When it was introduced in 1975, the 6502 was, by a considerable margin, the least expensive microprocessor on the market. It initially sold for less than one-sixth the cost of competing designs from larger companies, such as Motorola and Intel, and caused rapid decreases in pricing across the entire processor market. Along with the Zilog Z80, it sparked a series of projects that resulted in the home computer revolution of the early 1980s.
In computer architecture, 8-bit integers, memory addresses, or other data units are those that are 8 bits wide. Also, 8-bit CPU and ALU architectures are those that are based on registers, address buses, or data buses of that size. 8-bit is also a generation of microcomputers in which 8-bit microprocessors were the norm.
A microprocessor is a computer processor that incorporates the functions of a central processing unit on a single integrated circuit (IC), or at most a few integrated circuits. The microprocessor is a multipurpose, clock driven, register based, digital integrated circuit that accepts binary data as input, processes it according to instructions stored in its memory, and provides results as output. Microprocessors contain both combinational logic and sequential digital logic. Microprocessors operate on numbers and symbols represented in the binary number system.
Charles Ingerham Peddle is an American electrical engineer best known as the main designer of the MOS Technology 6502 microprocessor, as well as the KIM-1 SBC and its successor the Commodore PET PC, both based on the 6502.
Popular home video game consoles and computers, such as the Atari 2600, Atari 8-bit family, Apple II, Nintendo Entertainment System, Commodore 64, Atari Lynx, BBC Micro and others, used the 6502 or variations of the basic design. Soon after the 6502's introduction, MOS Technology was purchased outright by Commodore International, who continued to sell the microprocessor and licenses to other manufacturers. In the early days of the 6502, it was second-sourced by Rockwell and Synertek, and later licensed to other companies. In its CMOS form, which was developed by the Western Design Center, the 6502 family continues to be widely used in embedded systems, with estimated production volumes in the hundreds of millions.[ citation needed ]
A video game console is a computer device that outputs a video signal or visual image to display a video game that one or more people can play.
The Atari 2600, originally sold as the Atari Video Computer System or Atari VCS until November 1982, is a home video game console from Atari, Inc. Released on September 11, 1977, it is credited with popularizing the use of microprocessor-based hardware and games contained on ROM cartridges, a format first used with the Fairchild Channel F in 1976. This contrasts with the older model of having dedicated hardware that could play only those games that were physically built into the unit. The 2600 was bundled with two joystick controllers, a conjoined pair of paddle controllers, and a game cartridge: initially Combat, and later Pac-Man.
The Atari 8-bit family is a series of 8-bit home computers introduced by Atari, Inc. in 1979 and manufactured until 1992. All of the machines in the family are technically similar and differ primarily in packaging. They are based on the MOS Technology 6502 CPU running at 1.79 MHz, and were the first home computers designed with custom co-processor chips. This architecture enabled graphics and sound capabilities that were more advanced than contemporary machines at the time of release, and gaming on the platform was a major draw. Star Raiders is considered the platform's killer app.
The 6502 was designed by many of the same engineers that had designed the Motorola 6800 microprocessor family.Motorola started the 6800 microprocessor project in 1971 with Tom Bennett as the main architect. The chip layout began in late 1972, the first 6800 chips were fabricated in February 1974 and the full family was officially released in November 1974. John Buchanan was the designer of the 6800 chip and Rod Orgill, who later did the 6501, assisted Buchanan with circuit analyses and chip layout. Bill Mensch joined Motorola in June 1971 after graduating from the University of Arizona (at age 26). His first assignment was helping define the peripheral ICs for the 6800 family and later he was the principal designer of the 6820 Peripheral Interface Adapter (PIA). Motorola's engineers could run analog and digital simulations on an IBM 370-165 mainframe computer. Bennett hired Chuck Peddle in 1973 to do architectural support work on the 6800 family products already in progress. He contributed in many areas, including the design of the 6850 ACIA (serial interface).
The 6800 is an 8-bit microprocessor designed and first manufactured by Motorola in 1974. The MC6800 microprocessor was part of the M6800 Microcomputer System that also included serial and parallel interface ICs, RAM, ROM and other support chips. A significant design feature was that the M6800 family of ICs required only a single five-volt power supply at a time when most other microprocessors required three voltages. The M6800 Microcomputer System was announced in March 1974 and was in full production by the end of that year.
William (Bill) David Mensch, Jr., is an American electrical engineer born in Quakertown, Pennsylvania. He was a major contributor to the design of the Motorola 6800 8-bit microprocessor, was part of the small team led by Chuck Peddle that created the MOS Technology 6502, and he designed the 16-bit successor to the 6502, the 65816.
A Peripheral Interface Adapter (PIA) is a peripheral integrated circuit providing parallel I/O interfacing for microprocessor systems.
Motorola's target customers were established electronics companies such as Hewlett-Packard, Tektronix, TRW, and Chrysler.In May 1972, Motorola's engineers began visiting select customers and sharing the details of their proposed 8-bit microprocessor system with ROM, RAM, parallel and serial interfaces. In early 1974, they provided engineering samples of the chips so that customers could prototype their designs. Motorola's "total product family" strategy did not focus on the price of the microprocessor, but on reducing the customer's total design cost. They offered development software on a timeshare computer, the "EXORciser" debugging system, onsite training and field application engineer support. Both Intel and Motorola had initially announced a $360 price for a single microprocessor. (The IBM System/360 mainframe was a well known computer at the time.) The actual price for production quantities was much less. Motorola offered a design kit containing the 6800 with six support chips for $300.
The Hewlett-Packard Company or Hewlett-Packard was an American multinational information technology company headquartered in Palo Alto, California. It developed and provided a wide variety of hardware components as well as software and related services to consumers, small- and medium-sized businesses (SMBs) and large enterprises, including customers in the government, health and education sectors.
Tektronix, Inc., historically widely known as Tek, is an American company best known for manufacturing test and measurement devices such as oscilloscopes, logic analyzers, and video and mobile test protocol equipment.
TRW Inc. was an American corporation involved in a variety of businesses, mainly aerospace, automotive, and credit reporting. It was a pioneer in multiple fields including electronic components, integrated circuits, computers, software and systems engineering. TRW built many spacecraft, including Pioneer 1, Pioneer 10, and several space-based observatories. It was #57 on the 1986 Fortune 500 list, and had 122,258 employees. In 1958 the company was called Thompson Ramo Wooldridge, after three prominent leaders. This was later shortened to TRW.
Peddle, who would accompany the sales people on customer visits, found that customers were put off by the high cost of the microprocessor chips. To lower the price, the IC chip size would have to shrink so that more chips could be produced on each silicon wafer. This could be done by removing inessential features in the 6800 and using a newer fabrication technology, "depletion-load" MOS transistors. Peddle and other team members started outlining the design of an improved feature, reduced size microprocessor. At that time, Motorola's new semiconductor fabrication facility in Austin, Texas, was having difficulty producing MOS chips and mid 1974 was the beginning of a year-long recession in the semiconductor industry. Also, many of the Mesa, Arizona, employees were displeased with the upcoming relocation to Austin.Motorola Semiconductor Products Division's management was overwhelmed with problems and showed no interest in Peddle's low-cost microprocessor proposal. Chuck Peddle was frustrated with Motorola's management for missing this new opportunity. In a November 1975 interview, Motorola's Chairman, Robert Galvin, agreed. He said, "We did not choose the right leaders in the Semiconductor Products division." The division was reorganized and the management replaced. New group vice-president John Welty said, "The semiconductor sales organization lost its sensitivity to customer needs and couldn't make speedy decisions."
A wafer, also called a slice or substrate, is a thin slice of semiconductor material, such as a crystalline silicon, used in electronics for the fabrication of integrated circuits and in photovoltaics for conventional, wafer-based solar cells. The wafer serves as the substrate for microelectronic devices built in and over the wafer and undergoes many microfabrication process steps such as doping or ion implantation, etching, deposition of various materials, and photolithographic patterning. Finally, the individual microcircuits are separated (dicing) and packaged.
The metal-oxide-semiconductor field-effect transistor is a type of field-effect transistor (FET), most commonly fabricated by the controlled oxidation of silicon. It has an insulated gate, whose voltage determines the conductivity of the device. This ability to change conductivity with the amount of applied voltage can be used for amplifying or switching electronic signals. A metal-insulator-semiconductor field-effect transistor or MISFET is a term almost synonymous with MOSFET. Another synonym is IGFET for insulated-gate field-effect transistor.
Peddle began looking for a source of funding for this new project and found a small semiconductor company in Pennsylvania. In August 1974, Chuck Peddle, Bill Mensch, Rod Orgill, Harry Bawcom, Ray Hirt, Terry Holdt and Wil Mathys left Motorola to join MOS Technology. (Mike James joined later.) Of the seventeen chip designers and layout people on the 6800 team, seven left. There were 30 to 40 other marketers, application engineers and system engineers on the 6800 team.That December, Gary Daniels transferred into the 6800 microprocessor group. Tom Bennett did not want to leave the Phoenix area so Daniels took over the microprocessor development in Austin. His first project was a "depletion-load" version of the 6800; this cut the chip area nearly in half and doubled the speed. The faster parts were available in July 1976. This was followed by the 6802 which added 128 bytes of RAM and an on-chip clock oscillator circuit.
MOS Technology, Inc., also known as CSG , was a semiconductor design and fabrication company based in Norristown, Pennsylvania, in the United States. It is most famous for its 6502 microprocessor and various designs for Commodore International's range of home computers.
MOS Technology was formed in 1969 by three executives from General Instrument, Mort Jaffe, Don McLaughlin, and John Pavinen, to produce metal-oxide-semiconductor (MOS) integrated circuits. Allen-Bradley, a supplier of electronic components and industrial controls, acquired a majority interest in 1970.The company designed and fabricated custom ICs for customers and had developed a line of calculator chips.
On August 19, 1974, the former Motorola employees moved into MOS Technology's headquarters at Valley Forge, Pennsylvania. The goal was to design and produce a low cost microprocessor for embedded applications and to target as wide as possible a customer base. This would be possible only if the microprocessor was low cost—and in the semiconductor business, chip size determined cost. The size goal required n-channel "depletion-load" MOS transistors, a more advanced process than MOS Technology's calculator chips used. John Paivinen was able to have the fabrication process ready by June 1975. Chuck Peddle, Rod Orgill, and Wil Mathys designed the initial architecture of the new processors. There would be two microprocessors: the 6501 would plug into the same socket as the Motorola 6800, while the 6502 would work with 6800 family peripherals and have an on-chip clock oscillator. These processors would not run 6800 software because they had a different instruction set, different registers, and mostly different addressing modes. A September 1975 article in EDN magazine gives this summary of the design:
The MOS Technology 650X family represents a conscious attempt of eight former Motorola employees who worked on the development of the 6800 system to put out a part that would replace and outperform the 6800, yet undersell it. With the benefit of hindsight gained on the 6800 project, the MOS Technology team headed by Chuck Peddle, made the following architectural changes in the Motorola CPU…
The second "B" accumulator was omitted. The 16-bit 6800 index register with an 8-bit offset in the instruction was replaced with two 8-bit index registers with an 8-bit or 16-bit offset. Three-state control was eliminated from the address bus outputs. A clock generator was included on the chip. The address bus was always active so the VMA (valid-memory address) output was eliminated. An "8080-type" RDY signal for single-cycle stepping was added.
The chip high level design had to be turned into drawings of transistors and interconnects. At MOS Technology, the "layout" was a very manual process done with color pencils and vellum paper. The layout consisted of thousands of polygon shapes on six different drawings; one for each layer of the semiconductor fabrication process. Rod Orgill was responsible for the 6501 design; he had assisted John Buchanan at Motorola on the 6800. Bill Mensch did the 6502; he was the designer of the 6820 Peripheral Interface Adapter (PIA) at Motorola. Harry Bawcom, Mike James and Sydney-Anne Holt helped with the layout.
The size goal for the 6502 chip was 153 x 168 mils (3.9 x 4.3 mm) or an area of 16.6 mm2. At that time the technical literature would state the length and width of each chip in "mils" (0.001 inch). A smaller chip area means more chips per silicon wafer and greater yield as defects are generally randomly but uniformly scattered across the wafer area. So the more chips per wafer, the smaller the ratio of defective chips to total wafer chips. The original 6800 chips were intended to be 180 x 180 mils but layout was completed at 212 x 212 mils (5.4 x 5.4 mm) or an area of 29.0 mm2. The first 6502 chips were 168 x 183 mils (4.3 x 4.7 mm) or an area of 19.8 mm2. The Rotate Right instruction (ROR) did not work in the first silicon, so the instruction was temporarily omitted from the published documents, but the next iteration of the design shrank the chip and fixed the Rotate Right instruction, which was then included in revised documentation.
MOS Technology's microprocessor introduction was quite different from the traditional months-long product launch. The first run of a new integrated circuit is normally used for internal testing and shared with select customers as "engineering samples". These chips often have a minor design defect or two that will be corrected before production begins. Chuck Peddle's goal was to sell the first run 6501 and 6502 chips to the attendees at the Wescon trade show in San Francisco beginning on September 16, 1975. Peddle was a very effective spokesman and the MOS Technology microprocessors were extensively covered in the trade press. One of the earliest was a full-page story on the MCS6501 and MCS6502 microprocessors in the July 24, 1975 issue of Electronics magazine.Stories also ran in EE Times (August 24, 1975), EDN (September 20, 1975), Electronic News (November 3, 1975), Byte (November 1975) and Microcomputer Digest (November 1975). Advertisements for the 6501 appeared in several publications the first week of August 1975. The 6501 would be for sale at Wescon for $20 each. In September 1975, the advertisements included both the 6501 and the 6502 microprocessors. The 6502 would cost only $25.
When MOS Technology arrived at Wescon, they found that exhibitors could not sell anything on the show floor. They rented the MacArthur Suite at the St. Francis Hotel and directed customers there to purchase the processors. At the suite, the processors were stored in large jars to imply that the chips were in production and readily available. The customers did not know the bottom half of each jar contained non-functional chips.The chips were $20 and $25 while the documentation package was an additional $10. Users were encouraged to make copies of the documents, an inexpensive way for MOS Technology to distribute product information. The processors were supposed to have 56 instructions, but the Rotate Right (ROR) instruction did not work correctly on these chips, so the preliminary data sheets listed just 55 instructions. The reviews in Byte and EDN noted the lack of the ROR instruction. The next revision of the layout fixed this problem and the May 1976 datasheet listed 56 instructions. Peddle wanted every interested engineer and hobbyist to have access to the chips and documentation; other semiconductor companies only wanted to deal with "serious" customers. For example, Signetics was introducing the 2650 microprocessor and its advertisements asked readers to write for information on their company letterhead.
|3||∅1 (in)||∅1 (in)||∅1 (out)|
|5||Valid Memory Address||Valid Memory Address||N.C.|
|7||Bus Available||Bus Available||SYNC|
|36||Data Bus Enable||Data Bus Enable||N.C.|
|37||∅2 (in)||∅2 (in)||∅0 (in)|
|38||N.C.||N.C.||Set Overflow Flag|
|39||Three-State Control||N.C.||∅2 (out)|
The 6501/6502 introduction in print and at Wescon was an enormous success. The downside was that the extensive press coverage got Motorola's attention. In October 1975, Motorola reduced the price of a single 6800 microprocessor from $175 to $69. The $300 system design kit was reduced to $150 and it now came with a printed circuit board.On November 3, 1975, Motorola sought an injunction in Federal Court to stop MOS Technology from making and selling microprocessor products. They also filed a lawsuit claiming patent infringement and misappropriation of trade secrets. Motorola claimed that seven former employees joined MOS Technology to create that company's microprocessor products.
Motorola was a billion-dollar company with a plausible case and lawyers. On October 30, 1974, Motorola had filed numerous patent applications on the microprocessor family and was granted twenty-five patents. The first was in June 1976 and the second was to Bill Mensch on July 6, 1976, for the 6820 PIA chip layout. These patents covered the 6800 bus and how the peripheral chips interfaced with the microprocessor.Motorola began making transistors in 1950 and had a portfolio of semiconductor patents. Allen-Bradley decided not to fight this case and sold their interest in MOS Technology back to the founders. Four of the former Motorola engineers were named in the suit: Chuck Peddle, Will Mathys, Bill Mensch and Rod Orgill. All were named inventors in the 6800 patent applications. During the discovery process, Motorola found that one engineer, Mike James, had ignored Peddle's instructions and brought his 6800 design documents to MOS Technology. In March 1976, the now independent MOS Technology was running out of money and had to settle the case. They agreed to drop the 6501 processor, pay Motorola $200,000 and return the documents that Motorola contended were confidential. Both companies agreed to cross-license microprocessor patents. That May, Motorola dropped the price of a single 6800 microprocessor to $35. By November, Commodore had acquired MOS Technology.
With legal troubles behind them, MOS was still left with the problem of getting developers to try their processor, prompting Chuck Peddle to design the MDT-650 ("microcomputer development terminal") single-board computer. Another group inside the company designed the KIM-1, which was sold semi-complete and could be turned into a usable system with the addition of a 3rd party computer terminal and compact cassette drive. Much to their amazement, the KIM-1 sold well to hobbyists and tinkerers, as well as to the engineers to which it had been targeted. The related Rockwell AIM 65 control/training/development system also did well. The software in the AIM 65 was based on that in the MDT. Another roughly similar product was the Synertek SYM-1.
One of the first "public" uses for the design was the Apple I microcomputer, introduced in 1976. The 6502 was next used in the Commodore PET and the Apple II, —it too was a 6502.both released in 1977. It was later used in the Atari 8-bit family and Acorn Atom home computers, the BBC Micro, Commodore VIC-20 and other designs both for home computers and business, such as Ohio Scientific and Oric. The 6510, a direct successor of the 6502 with a digital I/O port and a tri-state address bus, was the CPU utilized in the best-selling Commodore 64 home computer. Commodore's floppy disk drive, the 1541, had a processor of its own
Another important use of the 6500 family was in video games. The first to make use of the processor design was the Atari VCS, later renamed the Atari 2600. The VCS used an offshoot of the 6502 called the 6507, which had fewer pins and, as a result, could address only 8 KB of memory. Millions of the Atari consoles would be sold, each with a MOS processor. Another significant use was by the Nintendo Entertainment System and Famicom. The 6502 used in the NES was a second source version by Ricoh, a partial system-on-a-chip, that lacked the binary-coded decimal mode but added 22 memory-mapped registers (and on-die hardware) for sound generation, joypad reading, and sprite list DMA. Called 2A03 in NTSC consoles and 2A07 in PAL consoles (the difference being the memory divider ratio and a lookup table for audio sample rates), this processor was produced exclusively for Nintendo. The Atari Lynx used a 4MHz version of the chip, the 65SC02.
In the 1980s, a popular electronics magazine Elektor/Elektuur used the processor in its microprocessor development board Junior Computer.
|MOS 6502 registers|
The 6502 is a little-endian 8-bit processor with a 16-bit address bus. The original versions were fabricated using an 8 µm process technology chip with an advertised die size of 153 x 168 mils (3.9 x 4.3 mm) or an area of 16.6 mm2.
The internal logic runs at the same speed as the external clock rate, but despite the slow clock speeds (typically in the neighborhood of 1 to 2 MHz), the 6502's performance was competitive with other contemporary CPUs using significantly faster clocks. This is partly due to a simple state machine implemented by combinational (clockless) logic to a greater extent than in many other designs; the two phase clock (supplying two synchronizations per cycle) can thereby control the whole machine-cycle directly. Typical instructions might take half as many cycles to complete on the 6502 than contemporary designs. Like most simple CPUs of the era, the dynamic NMOS 6502 chip is not sequenced by a microcode ROM but uses a PLA (which occupied about 15 percent of the chip area) for instruction decoding and sequencing. As in most eight-bit microprocessors, the chip does some limited overlapping of fetching and execution.
The low clock frequency moderated the speed requirement of memory and peripherals attached to the CPU, as only about 50 percent of the clock cycle was available for memory access (due to the asynchronous design, this percentage varied strongly among chip versions). This was critical at a time when affordable memory had access times in the range 250 - 450 ns. The original NMOS 6502 was minimalistically engineered and efficiently manufactured and therefore cheap—an important factor in getting design wins in the very price-sensitive game console and home computer markets.
Like its precursor, the Motorola 6800, the 6502 has very few registers. To this end, the CPU includes a zero-page addressing mode that uses one address byte in the instruction instead of the two needed to address the full 64 KB of memory. This provides fast access to the first 256 bytes of RAM by using shorter instructions. Chuck Peddle has said in interviews that the specific intention was to allow these first 256 bytes of RAM to be used like registers.[ citation needed ]
The 6502's registers include one 8-bit accumulator register (A), two 8-bit index registers (X and Y), 7 processor status flag bits (P), an 8-bit stack pointer (S), and a 16-bit program counter (PC). The stack's address space is hardwired to memory page $01, i.e. the address range $0100–$01FF (256–511). Software access to the stack is done via four implied addressing mode instructions, whose functions are to push or pop (pull) the accumulator or the processor status register. The same stack is also used for subroutine calls via the JSR (Jump to Subroutine) and RTS (Return from Subroutine) instructions and for interrupt handling.
The chip uses the index and stack registers effectively with several addressing modes, including a fast "direct page" or "zero page" mode, similar to that found on the PDP-8, that accesses memory locations from addresses 0 to 255 with a single 8-bit address (saving the cycle normally required to fetch the high-order byte of the address)—code for the 6502 uses the zero page much as code for other processors would use registers. On some 6502-based microcomputers with an operating system, the OS uses most of zero page, leaving only a handful of locations for the user.
Addressing modes also include implied (1 byte instructions); absolute (3 bytes); indexed absolute (3 bytes); indexed zero-page (2 bytes); relative (2 bytes); accumulator (1); indirect,x and indirect,y (2); and immediate (2). Absolute mode is a general-purpose mode. Branch instructions use a signed 8-bit offset relative to the instruction after the branch; the numerical range -128..127 therefore translates to 128 bytes backward and 127 bytes forward from the instruction following the branch (which is 126 bytes backward and 129 bytes forward from the start of the branch instruction). Accumulator mode uses the accumulator as an effective address, and does not need any operand data. Immediate mode uses an 8-bit literal operand.
The indirect modes are useful for array processing and other looping. With the 5/6 cycle "(indirect),y" mode, the 8-bit Y register is added to a 16-bit base address read from zero page which is located by a single byte following the opcode. The Y register is therefore an index-register in the sense that it is used to hold an actual index (as opposed to the X register in the 6800 where a base address was directly stored and to which an immediate offset could be added). Incrementing the index register to walk the array byte-wise takes only two additional cycles. With the less frequently used "(indirect,x)" mode the effective address for the operation is found at the zero page address formed by adding the second byte of the instruction to the contents of the X register. Using the indexed modes, the zero page effectively acts as a set of up to 128 additional (though very slow) address registers.
The 6502 is capable of performing addition and subtraction in binary or binary coded decimal. Placing the CPU into BCD mode with the SED (set D flag) instruction results in decimal arithmetic, in which $99 + $01 would result in $00 and the carry (C) flag being set. In binary mode (CLD, clear D flag), the same operation would result in $9A and the carry flag being cleared. Other than Atari BASIC, BCD mode was seldom used in home computer applications.
See the Hello world! article for a simple but characteristic example of 6502 assembly language.
The processor's non-maskable interrupt (NMI) input is edge sensitive, which means that the interrupt is triggered by the falling edge of the signal rather than its level. The implication of this feature is that a wired-OR interrupt circuit is not readily supported. However, this also prevents nested NMI interrupts from occurring until the hardware makes the NMI input inactive again, often under control of the NMI interrupt handler.
The simultaneous assertion of the NMI and IRQ (maskable) hardware interrupt lines causes IRQ to be ignored. However, if the IRQ line remains asserted after the servicing of the NMI, the processor will immediately respond to IRQ, as IRQ is level sensitive. Thus a sort of built-in interrupt priority was established in the 6502 design.
The "Break" flag of the processor is very different from the other flag bits. It has no flag setting, resetting, or testing instructions of its own, and is not affected by the PHP and PLP instructions. It exists only on the stack, where BRK and PHP always write a 1, while IRQ and NMI always write a 0.
The "SO" input pin, when asserted, will set the processor's overflow status bit (deasserting it does not clear the overflow bit, however). This can be used by a high-speed polling device driver, which can poll the hardware once in only three cycles by using a Branch-on-oVerflow-Clear (BVC) instruction that branches to itself. For example, the Commodore 1541 and other Commodore floppy disk drives use this technique to detect without delay whether the serializer is ready to accept or provide another byte of disk data. Obviously great care must be used in the device driver and the associated system design, as spurious assertion of the overflow bit could ruin arithmetic processing.
A 6502 assembly language statement consists of a three-character instruction mnemonic, followed by an operand in the case of an instruction that takes an operand. When assembled, the resulting machine code consists of a one-byte operation code (opcode), followed by a one- or two-byte operand, if the instruction was assembled with an operand, hence 6502 machine instructions vary in length from one to three bytes.The operand is stored in the 6502's customary little-endian format. The 65C816, the 16-bit CMOS version of the 6502, also supports 24-bit addressing, which results in instructions being assembled with three-byte operands, also arranged in little-endian format.
|Opcode matrix for the 6502 instruction set|
|Addressing modes: A –accumulator, # –immediate, zpg –zero page, abs –absolute, ind –indirect, X –indexed by X register, Y –indexed by Y register, rel –relative|
|High nibble||Low nibble|
|0||BRK||ORA (ind,X)||ORA zpg||ASL zpg||PHP||ORA #||ASL A||ORA abs||ASL abs|
|1||BPL rel||ORA (ind),Y||ORA zpg,X||ASL zpg,X||CLC||ORA abs,Y||ORA abs,X||ASL abs,X|
|2||JSR abs||AND (ind,X)||BIT zpg||AND zpg||ROL zpg||PLP||AND #||ROL A||BIT abs||AND abs||ROL abs|
|3||BMI rel||AND (ind),Y||AND zpg,X||ROL zpg,X||SEC||AND abs,Y||AND abs,X||ROL abs,X|
|4||RTI||EOR (ind,X)||EOR zpg||LSR zpg||PHA||EOR #||LSR A||JMP abs||EOR abs||LSR abs|
|5||BVC rel||EOR (ind),Y||EOR zpg,X||LSR zpg,X||CLI||EOR abs,Y||EOR abs,X||LSR abs,X|
|6||RTS||ADC (ind,X)||ADC zpg||ROR zpg||PLA||ADC #||ROR A||JMP (ind)||ADC abs||ROR abs|
|7||BVS rel||ADC (ind),Y||ADC zpg,X||ROR zpg,X||SEI||ADC abs,Y||ADC abs,X||ROR abs,X|
|8||STA (ind,X)||STY zpg||STA zpg||STX zpg||DEY||TXA||STY abs||STA abs||STX abs|
|9||BCC rel||STA (ind),Y||STY zpg,X||STA zpg,X||STX zpg,Y||TYA||STA abs,Y||TXS||STA abs,X|
|A||LDY #||LDA (ind,X)||LDX #||LDY zpg||LDA zpg||LDX zpg||TAY||LDA #||TAX||LDY abs||LDA abs||LDX abs|
|B||BCS rel||LDA (ind),Y||LDY zpg,X||LDA zpg,X||LDX zpg,Y||CLV||LDA abs,Y||TSX||LDY abs,X||LDA abs,X||LDX abs,Y|
|C||CPY #||CMP (ind,X)||CPY zpg||CMP zpg||DEC zpg||INY||CMP #||DEX||CPY abs||CMP abs||DEC abs|
|D||BNE rel||CMP (ind),Y||CMP zpg,X||DEC zpg,X||CLD||CMP abs,Y||CMP abs,X||DEC abs,X|
|E||CPX #||SBC (ind,X)||CPX zpg||SBC zpg||INC zpg||INX||SBC #||NOP||CPX abs||SBC abs||INC abs|
|F||BEQ rel||SBC (ind),Y||SBC zpg,X||INC zpg,X||SED||SBC abs,Y||SBC abs,X||INC abs,X|
|Blank opcodes (e.g., F2) and all opcodes whose low nibbles are 3, 7, B and F are undefined in the 6502 instruction set.|
There were several variants of the NMOS 6502:
The MOS Technology 6512, 6513, 6514, and 6515 each rely on an external clock, instead of using an internal clock generator like the 650x (e.g. 6502). This was used to advantage in some designs where the clocks could be run asymmetrically, increasing overall CPU performance.
The 6512 was used in the BBC Micro B+64.
The Western Design Center designed and currently produces the W65C816S processor, a 16-bit, static-core successor to the 65C02, with greatly enhanced features. The W65C816S is a newer variant of the 65C816, which was the core of the Apple IIGS computer and was the basis of the Ricoh 5A22 processor that powered the popular Super Nintendo Entertainment System. The W65C816S incorporates minor improvements over the 65C816 that make the newer chip not an exact hardware-compatible replacement for the earlier one. Currently available through electronics distributors as of November 2017, the W65C816S costs about US $8 (down to under US $6 in bulk) and is rated for 14 MHz operation.
The Western Design Center also designed and produced the 65C802, which was a 65C816 core with a 64 KB address space in a 65(C)02 pin-compatible package. The 65C802 could be retrofitted to a 6502 board and would function as a 65C02 on power-up, operating in "emulation mode." As with the 65C816, a two-instruction sequence would switch the 65C802 to "native mode" operation, exposing its 16 bit accumulator and index registers, as well as other 65C816 enhanced features. The 65C802 was not widely used: new designs almost always were built around the 65C816, resulting in 65C802 production being discontinued.
The 65GZ032 designed by Gideon Zweijtzer is a VHDL source core that is 6502 compatible and extends the 8-bit CPU to a 32-bit design. It features pipelined RISC, new opcodes, access to 4 GByte of linear memory, paged memory and a clock speed of 33 MHz.
The following 6502 assembly language source code is for a subroutine named
TOLOWER, which copies a null-terminated character string from one location to another, converting upper case letter characters to lower case letters. The string being copied is the "source" and the string into which the converted source is stored is the "destination."
0080 0080 00 04 0082 00 05 0600 0600 A0 00 0602 B1 80 0604 F0 11 0606 C9 41 0608 90 06 060A C9 5B 060C B0 02 060E 09 20 0610 91 82 0612 C8 0613 D0 ED 0615 38 0616 60 0617 91 82 0618 18 0619 60 061A
; TOLOWER:;; Convert a null-terminated character string to all lower case.; Maximum string length is 255 characters, plus the null term-; inator.;; Parameters:;; SRC - Source string address; DST - Destination string address;ORG$0080;SRC.WORD$0400;source string pointer ($40)DST.WORD$0500;destination string pointer ($42);ORG$0600;execution start address;TOLOWERLDY#$00;starting index;LOOPLDA(SRC),Y;get from source stringBEQDONE;end of string;CMP#'A';if lower than UC alphabet...BCCSKIP;copy unchanged;CMP#'Z'+1;if greater than UC alphabet...BCSSKIP;copy unchanged;ORA#%00100000;convert to lower case;SKIPSTA(DST),Y;store to destination stringINY;bump indexBNELOOP;next character;; NOTE: If .Y wraps the destination string will be left in an undefined; state. We set carry to indicate this to the calling function.;SEC;report string too long error &...RTS;return to caller;DONESTA(DST),Y;terminate destination stringCLC;report conversion completed &...RTS;return to caller;.END
The Intel 8080 ("eighty-eighty") was the second 8-bit microprocessor designed and manufactured by Intel and was released in April 1974. It is an extended and enhanced variant of the earlier 8008 design, although without binary compatibility. The initial specified clock frequency limit was 2 MHz, and with common instructions using 4, 5, 7, 10, or 11 cycles this meant that it operated at a typical speed of a few hundred thousand instructions per second. A faster variant 8080A-1 became available later with clock frequency limit up to 3.125 MHz.
The Intel 8088 microprocessor is a variant of the Intel 8086. Introduced on July 1, 1979, the 8088 had an eight-bit external data bus instead of the 16-bit bus of the 8086. The 16-bit registers and the one megabyte address range were unchanged, however. In fact, according to the Intel documentation, the 8086 and 8088 have the same execution unit (EU)—only the bus interface unit (BIU) is different. The original IBM PC was based on the 8088.
The Motorola 68000 is a 16/32-bit CISC microprocessor, which implements a 32-bit instruction set, with 32-bit registers and 32-bit internal data bus, but with a 16-bit data ALU and two 16-bit arithmetic ALUs and a 16-bit external data bus, designed and marketed by Motorola Semiconductor Products Sector. Introduced in 1979 with HMOS technology as the first member of the successful 32-bit Motorola 68000 series, it is generally software forward-compatible with the rest of the line despite being limited to a 16-bit wide external bus. After 39 years in production, the 68000 architecture is still in use.
The MOS Technology 65xx series is a family of 8-bit microprocessors from MOS Technology, based on the Motorola 6800. The 65xx family included the 6502, used in home computers such as the Commodore PET and VIC-20, the Apple II, the Atari 800, and the British BBC Micro.
The MOS Technology 6510 is an 8-bit microprocessor designed by MOS Technology. It is a modified form of the very successful 6502. The 6510 was only widely used in the Commodore 64 home computer and its variants.
The Motorola 6809 ("sixty-eight-oh-nine") is an 8-bit microprocessor CPU with some 16-bit features from Motorola. It was designed by Terry Ritter and Joel Boney and introduced in 1978. It was a major advance over both its predecessor, the Motorola 6800, and the related MOS Technology 6502. Among the systems to use the 6809 are the Dragon home computers, TRS-80 Color Computer, the Vectrex home console, and early 1980s arcade machines including Defender, Robotron: 2084, Joust, and Gyruss.
The 6507 is an 8-bit microprocessor from MOS Technology, Inc.
The KIM-1, short for Keyboard Input Monitor, is a small 6502-based single-board computer developed and produced by MOS Technology, Inc. and launched in 1976. It was very successful in that period, due to its low price and easy-access expandability.
In computer engineering, Halt and Catch Fire, known by the assembly mnemonic HCF, is an idiom referring to a computer machine code instruction that causes the computer's central processing unit (CPU) to cease meaningful operation, typically requiring a restart of the computer. It originally referred to a fictitious instruction in IBM System/360 computers, making joke about its numerous non-obvious instruction mnemonics.
The zero page is the series of memory addresses at the very beginning of a computer's address space; that is, the page whose starting address is zero. The size of a "page" depends on the context, and the significance of zero-page memory versus higher addressed memory is highly dependent on machine architecture. For example, the Motorola 6800 and MOS Technology 6502 processor families treat the first 256 bytes of memory specially, whereas many other processors do not.
The Western Design Center (WDC) 65C02 microprocessor is an enhanced CMOS version of the popular NMOS-based 8-bit MOS Technology 6502 microprocessor—the CMOS redesign being made by Bill Mensch in 1978. Over various periods of time, the 65C02 has been second-sourced by NCR, GTE, Rockwell, Synertek and Sanyo. The 65C02 has been used in some home computers, as well as in embedded applications, including medical-grade implanted devices.
Ohio Scientific Inc. was an Ohio-based computer company that built and marketed microcomputers from 1975 to 1981. Their best-known products were the Challenger series of microcomputers, but they also sold a variety of computer kits, single-board computers and various peripherals.
The CSG 65CE02 is an 8/16-bit microprocessor developed by Commodore Semiconductor Group in 1988. It is a member of the MOS Technology 6502 family.
The W65C816S is an 8/16-bit microprocessor (MPU) developed and sold by the Western Design Center (WDC). Introduced in 1983, the W65C816S is an enhanced version of the WDC 65C02 8-bit MPU, itself a CMOS enhancement of the venerable MOS Technology 6502 NMOS MPU. The 65 in the part's designation comes from its 65C02 compatibility mode, and the 816 signifies that the MPU has selectable 8– and 16–bit register sizes.
The first 6502 was fabricated with 8 micron technology, ran at one megahertz and had a maximum memory of 64k.
With the 65GZ032 Gideo Zweijtzer has built a VHDL core that is 6502 compatible, but extends the 8 bit core with a 32 bit design.
|Wikibooks has a book on the topic of: 6502 Assembly|
|Wikimedia Commons has media related to 6502 microprocessor .|
This article is based on material taken from the Free On-line Dictionary of Computing prior to 1 November 2008 and incorporated under the "relicensing" terms of the GFDL, version 1.3 or later.