Intel 8080

Last updated

Intel 8080
Intel 8080 open-closed.jpg
Closed and open Intel 8080 processor
General information
LaunchedApril 1974;50 years ago (1974-04)
Discontinued1990;35 years ago (1990) [1]
Marketed by Intel
Designed byIntel
Common manufacturer
  • Intel
Performance
Max. CPU clock rate 2 MHz to 3.125 MHz
Data width 8 bits
Address width16 bits
Architecture and classification
Technology node 6 μm
Instruction set 8080
Physical specifications
Transistors
  • 4,500 or 6,000 [2]
Cores
  • 1
Package
Socket
History
Predecessor Intel 8008
Successor Intel 8085
Support status
Unsupported

The Intel 8080 (pronounced "eighty-eighty") is Intel's second 8-bit microprocessor that played an important role in the evolution of early computing. Introduced in April 1974, the 8080 was an enhanced successor to the earlier Intel 8008 microprocessor, although without binary compatibility. [3] Originally intended for use in embedded systems such as calculators, cash registers, computer terminals, and industrial robots, [4] its robust performance soon led to adoption in a broader range of systems, ultimately helping to launch the microcomputer industry.

Contents

Several key design choices contributed to the 8080’s success. Its 40‑pin package simplified interfacing compared to the 8008’s 18‑pin design, enabling a more efficient data bus. The transition to NMOS technology provided faster transistor speeds than the 8008's PMOS while also simplifying interfacing by making it TTL compatible. An expanded instruction set and a full 16-bit address bus allowed the 8080 to access up to 64 KB of memory, quadrupling the capacity of its predecessor. A broader selection of support chips further enhanced its functionality. Many of these improvements stemmed from customer feedback, as designer Federico Faggin and others at Intel heard about shortcomings in the 8008 architecture.

The 8080 found its way into early personal computers such as the Altair 8800 and subsequent S-100 bus systems, and it served as the original target CPU for the CP/M operating systems. It also directly influenced the later x86 architecture which was designed so that its assembly language closely resembled that of the 8080, permitting many instructions to map directly from one to the other. [5]

Originally operating at a clock rate of 2  MHz, with common instructions taking between 4 and 11 clock cycles, the 8080 was capable of executing several hundred thousand instructions per second. Later, two faster variants, the 8080A-1 and 8080A-2, offered improved clock speeds of 3.125 MHz and 2.63 MHz, respectively. [6] In most applications, the processor was paired with two support chips, the 8224 clock generator/driver and the 8228 bus controller, to manage its timing and data flow.

History

Microprocessor customers were reluctant to adopt the 8008 because of limitations such as the single addressing mode, low clock speed, low pin count, and small on-chip stack, which restricted the scale and complexity of software. There were several proposed designs for the 8080, ranging from simply adding stack instructions to the 8008 to a complete departure from all previous Intel architectures. [7] The final design was a compromise between the proposals.

The conception of the 8080 began in the summer of 1971, when Intel wrapped up development of the 4004 and were still working on the 8008. After rumors about the "CPU on a chip" came out, Intel started to see interest in the microprocessor from all sorts of customers. At the same time, Federico Faggin – who led the design of the 4004 and became the primary architect of the 8080 – was giving some technical seminars on both of the aforementioned microprocessors and visiting customers. He found that they were complaining about the architecture and performance of said microprocessors, especially the 8008 – as its speed at 0.5 MHz was "not adequate." [7]

Faggin later proposed the chip to Intel's management and pushed for its implementation in the spring of 1972, as development of the 8008 was wrapping up. However, much to his surprise and frustration, Intel didn't approve the project. Faggin says that Intel wanted to see how the market would react to the 4004 and 8008 first, while others noted the problems Intel was having getting its latest generation of memory chips out the door and wanted to focus on that. As a result, Intel didn't approve of the project until fall of that year. [7] Faggin hired Masatoshi Shima, who helped design the logic of the 4004 with him, from Japan in November 1972. Shima did the detailed design under Faggin's direction, [8] using the design methodology for random logic with silicon gate that Faggin had created for the 4000 family and the 8008.

The 8080 was explicitly designed to be a general-purpose microprocessor for a larger number of customers. Much of the development effort was spent trying to integrate the functionalities of the 8008's supplemental chips into one package. It was decided early in development that the 8080 was not to be binary-compatible with the 8008, instead opting for source compatibility once run through a transpiler, to allow new software to not be subject to the same restrictions as the 8008. For the same reason, as well as to expand the capabilities of stack-based routines and interrupts, the stack was moved to external memory.

Noting the specialized use of general-purpose registers by programmers in mainframe systems, Faggin with Shima and Stanley Mazor decided the 8080's registers would be specialized, with register pairs having a different set of uses. [9] This also allowed the engineers to more effectively use transistors for other purposes.

Shima finished the layout in August 1973. Production of the chip later began in December of that year. [7] After the development of NMOS logic fabrication, a prototype of the 8080 was completed in January 1974. It had a flaw, in that driving with standard TTL devices increased the ground voltage because high current flowed into the narrow line. Intel had already produced 40,000 units of the 8080 at the direction of the sales section before Shima characterized the prototype. After working out some typical last-minute issues, Intel introduced the product in March 1974. [7] It was released a month later as requiring Low-power Schottky TTL (LS TTL) devices. The 8080A fixed this flaw. [10]

Intel offered an instruction set simulator for the 8080 named INTERP/80 to run compiled PL/M programs. It was written in FORTRAN IV by Gary Kildall while he worked as a consultant for Intel. [11] [12]

There is only one patent on the 8080 with the following names: Federico Faggin, Masatoshi Shima, Stanley Mazor.

Description

Programming model

i8080 microarchitecture Intel 8080 arch.svg
i8080 microarchitecture
Intel 8080 registers
15141312111009080706050403020100(bit position)
Main registers
AFlagsProgram Status Word
BCB
DED
HLH (indirect address)
Index registers
SPStack Pointer
Program counter
PCProgram Counter
Status register
  S Z 0 AC 0 P 1 C Flags [13]

The Intel 8080 is the successor to the 8008. It uses the same basic instruction set and register model as the 8008, although it is neither source code compatible nor binary code compatible with its predecessor. Every instruction in the 8008 has an equivalent instruction in the 8080. The 8080 also adds 16-bit operations in its instruction set. Whereas the 8008 required the use of the HL register pair to indirectly access its 14-bit memory space, the 8080 added addressing modes to allow direct access to its full 16-bit memory space. The internal 7-level push-down call stack of the 8008 was replaced by a dedicated 16-bit stack-pointer (SP) register. The 8080's 40-pin DIP packaging permits it to provide a 16-bit address bus and an 8-bit data bus, enabling access to 64  KiB (216 bytes) of memory.

Registers

The processor has seven 8-bit registers (A, B, C, D, E, H, and L), where A is the primary 8-bit accumulator. The other six registers can be used as either individual 8-bit registers or in three 16-bit register pairs (BC, DE, and HL, referred to as B, D and H in Intel documents) depending on the particular instruction. Some instructions also enable the HL register pair to be used as a (limited) 16-bit accumulator. A pseudo-register M, which refers to the dereferenced memory location pointed to by HL, can be used almost anywhere other registers can be used. The 8080 has a 16-bit stack pointer to memory, replacing the 8008's internal stack, and a 16-bit program counter.

Flags

The processor maintains internal flag bits (a status register), which indicate the results of arithmetic and logical instructions. Only certain instructions affect the flags. The flags are:

  • Sign (S), set if the result is negative.
  • Zero (Z), set if the result is zero.
  • Parity (P), set if the number of 1 bits in the result is even.
  • Carry (C), set if the last addition operation resulted in a carry or if the last subtraction operation required a borrow.
  • Auxiliary carry (AC or H), used for binary-coded decimal arithmetic (BCD).

The carry bit can be set or complemented by specific instructions. Conditional-branch instructions test the various flag status bits. The accumulator and the flags together are called the PSW, or program status word. PSW can be pushed to or popped from the stack.

Commands, instructions

As with many other 8-bit processors, all instructions are encoded in one byte (including register numbers, but excluding immediate data), for simplicity. Some can be followed by one or two bytes of data, which can be an immediate operand, a memory address, or a port number. Like more advanced processors, it has automatic CALL and RET instructions for multi-level procedure calls and returns (which can even be conditionally executed, like jumps) and instructions to save and restore any 16-bit register pair on the machine stack. Eight one-byte call instructions (RST) for subroutines exist at the fixed addresses 00h, 08h, 10h, ..., 38h. These are intended to be supplied by external hardware in order to invoke a corresponding interrupt service routine, but are also often employed as fast system calls. The instruction that executes slowest is XTHL, which is used for exchanging the register pair HL with the value stored at the address indicated by the stack pointer.

8-bit instructions

All 8-bit operations with two operands can only be performed on the 8-bit accumulator (the A register). The other operand can be either an immediate value, another 8-bit register, or a memory byte addressed by the 16-bit register pair HL. Increments and decrements can be performed on any 8 bit register or an HL-addressed memory byte. Direct copying is supported between any two 8-bit registers and between any 8-bit register and an HL-addressed memory byte. Due to the regular encoding of the MOV instruction (using a quarter of available opcode space), there are redundant codes to copy a register into itself (MOV B,B, for instance), which are of little use, except for delays. However, the systematic opcode for MOV M,M is instead used to encode the halt (HLT) instruction, halting execution until an external reset or interrupt occurs.

16-bit operations

Although the 8080 is generally an 8-bit processor, it has limited abilities to perform 16-bit operations. Any of the three 16-bit register pairs (BC, DE, or HL, referred to as B, D, H in Intel documents) or SP can be loaded with an immediate 16-bit value (using LXI), incremented or decremented (using INX and DCX), or added to HL (using DAD). By adding HL to itself, it is possible to achieve the same result as a 16-bit arithmetical left shift with one instruction. The only 16-bit instructions that affect any flag is DAD, which sets the CY (carry) flag in order to allow for programmed 24-bit or 32-bit arithmetic (or larger), needed to implement floating-point arithmetic. BC, DE, HL, or PSW can be copied to and from the stack using PUSH and POP. A stack frame can be allocated using DAD SP and SPHL. A branch to a computed pointer can be executed with PCHL. LHLD loads HL from directly addressed memory and SHLD stores HL likewise. The XCHG [14] instruction exchanges the values of the HL and DE register pairs. XTHLexchanges last item pushed on stack with HL.

Instruction set
OpcodeOperandsMnemonicClocksDescription
76543210b2b3
00000000——NOP4No operation
00RP0001datlodathiLXI rp,data10RP ← data
00RP0010——STAX rp7(RP) ← A [BC or DE only]
00RP0011——INX rp5RP ← RP + 1
00DDD100——INR ddd5/10DDD ← DDD + 1
00DDD101——DCR ddd5/10DDD ← DDD - 1
00DDD110data—MVI ddd,data7/10DDD ← data
00RP1001——DAD rp10HL ← HL + RP
00RP1010——LDAX rp7A ← (RP) [BC or DE only]
00RP1011——DCX rp5RP ← RP - 1
00000111——RLC4A1-7 ← A0-6; A0 ← Cy ← A7
00001111——RRC4A0-6 ← A1-7; A7 ← Cy ← A0
00010111——RAL4A1-7 ← A0-6; Cy ← A7; A0 ← Cy
00011111——RAR4A0-6 ← A1-7; Cy ← A0; A7 ← Cy
00100010addloaddhiSHLD add16(add) ← HL
00100111——DAA4If A0-3 > 9 OR AC = 1 then A ← A + 6;

then if A4-7 > 9 OR Cy = 1 then A ← A + 0x60

00101010addloaddhiLHLD add16HL ← (add)
00101111——CMA4A ← ¬A
00110010addloaddhiSTA add13(add) ← A
00110111——STC4Cy ← 1
00111010addloaddhiLDA add13A ← (add)
00111111——CMC4Cy ← ¬Cy
01DDDSSS——MOV ddd,sss5/7DDD ← SSS
01110110——HLT7Halt
10ALUSSS——ADD ADC SUB SBB ANA XRA ORA CMP sss4/7A ← A [ALU operation] SSS
11CC000——Rcc (RET conditional)5/11If cc true, PC ← (SP), SP ← SP + 2
11RP0001——POP rp10RP ← (SP), SP ← SP + 2
11CC010addloaddhiJcc add (JMP conditional)10If cc true, PC ← add
11000011addloaddhiJMP add10PC ← add
11CC100addloaddhiCcc add (CALL conditional)11/17If cc true, SP ← SP - 2, (SP) ← PC, PC ← add
11RP0101——PUSH rp11SP ← SP - 2, (SP) ← RP
11ALU110data—ADI ACI SUI SBI ANI XRI ORI CPI data7A ← A [ALU operation] data
11N111——RST n11SP ← SP - 2, (SP) ← PC, PC ← N x 8
11001001——RET10PC ← (SP), SP ← SP + 2
11001101addloaddhiCALL add17SP ← SP - 2, (SP) ← PC, PC ← add
11010011port—OUT port10Port ← A
11011011port—IN port10A ← Port
11100011——XTHL18HL ↔ (SP)
11101001——PCHL5PC ← HL
11101011——XCHG4HL ↔ DE
11110011——DI4Disable interrupts
11111001——SPHL5SP ← HL
11111011——EI4Enable interrupts
76543210b2b3MnemonicClocksDescription
SSS DDD210CCALURP
B000NZADD ADI (A ← A + arg)BC
C001ZADC ACI (A ← A + arg + Cy)DE
D010NCSUB SUI (A ← A - arg)HL
E011CSBB SBI (A ← A - arg - Cy)SP or PSW
H100POANA ANI (A ← A ∧ arg)
L101PEXRA XRI (A ← A ⊻ arg)
M110PORA ORI (A ← A ∨ arg)
A111NCMP CPI (A - arg)
SSS DDD210CCALU

Input/output scheme

Input output port space

The 8080 supports 256 input/output (I/O) ports, [15] accessed via dedicated I/O instructions taking port addresses as operands. [16] This I/O mapping scheme is regarded as an advantage, as it frees up the processor's limited address space. Many CPU architectures instead use so-called memory-mapped I/O (MMIO), in which a common address space is used for both RAM and peripheral chips. This removes the need for dedicated I/O instructions, although a drawback in such designs may be that special hardware must be used to insert wait states, as peripherals are often slower than memory. However, in some simple 8080 computers, I/O is indeed addressed as if they were memory cells, "memory-mapped", leaving the I/O commands unused. I/O addressing can also sometimes employ the fact that the processor outputs the same 8-bit port address to both the lower and the higher address byte (i.e., IN 05h would put the address 0505h on the 16-bit address bus). Similar I/O-port schemes are used in the backward-compatible Zilog Z80 and Intel 8085, and the closely related x86 microprocessor families.

Separate stack space

One of the bits in the processor state word (see below) indicates that the processor is accessing data from the stack. Using this signal, it is possible to implement a separate stack memory space. This feature is seldom used.

Status word

For more advanced systems, during the beginning of each machine cycle, the processor places an eight bit status word on the data bus. This byte contains flags that determine whether the memory or I/O port is accessed and whether it is necessary to handle an interrupt.

The interrupt system state (enabled or disabled) is also output on a separate pin. For simple systems, where the interrupts are not used, it is possible to find cases where this pin is used as an additional single-bit output port (the popular Radio-86RK computer made in the Soviet Union, for instance).

Example code

The following 8080/8085 assembler source code is for a subroutine named memcpy that copies a block of data bytes of a given size from one location to another. The data block is copied one byte at a time, and the data movement and looping logic utilizes 16-bit operations.

                      1000 1000 1000  78 1001  B1 1002  C8 1003  1A 1004  77 1005  13 1006  23 1007  0B 1008  78 1009  B1 100A  C2 03 10 100D  C9 
; memcpy --; Copy a block of memory from one location to another.;; Entry registers;       BC - Number of bytes to copy;       DE - Address of source data block;       HL - Address of target data block;; Return registers;       BC - Zeroorg1000h;Origin at 1000hmemcpypublicmova,b;Copy register B to register Aorac;Bitwise OR of A and C into register Arz;Return if the zero-flag is set high.loop:ldaxd;Load A from the address pointed by DEmovm,a;Store A into the address pointed by HLinxd;Increment DEinxh;Increment HLdcxb;Decrement BC   (does not affect Flags)mova,b;Copy B to A    (so as to compare BC with zero)orac;A = A | C      (are both B and C zero?)jnzloop;Jump to 'loop:' if the zero-flag is not set.   ret;Return

Pin use

8080 pinout Intel 8080 Microprocessor.png
8080 pinout

The address bus has its own 16 pins, and the data bus has 8 pins that are usable without any multiplexing. Using the two additional pins (read and write signals), it is possible to assemble simple microprocessor devices very easily. Only the separate IO space, interrupts, and DMA need added chips to decode the processor pin signals. However, the pin load capacity is limited; even simple computers often require bus amplifiers.

The processor needs three power sources (−5, +5, and +12 V) and two non-overlapping high-amplitude synchronizing signals. However, at least the late Soviet version КР580ВМ80А was able to work with a single +5 V power source, the +12 V pin being connected to +5 V and the −5 V pin to ground.

The pin-out table, from the chip's accompanying documentation, describes the pins as follows:

Pin number Signal Type Comment
1A10 OutputAddress bus 10
2GND —Ground
3D4 Bidirectional Bidirectional data bus. The processor also transiently sets here the "processor state", providing information about what the processor is currently doing:
  • D0 reading interrupt command. In response to the interrupt signal, the processor is reading and executing a single arbitrary command with this flag raised. Normally the supporting chips provide the subroutine call command (CALL or RST), transferring control to the interrupt handling code.
  • D1 reading (low level means writing)
  • D2 accessing stack (probably a separate stack memory space was initially planned)
  • D3 doing nothing, has been halted by the HLT instruction
  • D4 writing data to an output port
  • D5 reading the first byte of an executable instruction
  • D6 reading data from an input port
  • D7 reading data from memory
4D5
5D6
6D7
7D3
8D2
9D1
10D0
11−5 V —The −5 V power supply. This must be the first power source connected and the last disconnected, otherwise the processor will be damaged.
12RESET InputReset. This active low signal forces execution of commands located at address 0000. The content of other processor registers is not modified.
13HOLD InputDirect memory access request. The processor is requested to switch the data and address bus to the high impedance ("disconnected") state.
14INT InputInterrupt request
15φ2 InputThe second phase of the clock generator signal
16INTE OutputThe processor has two commands for setting 0 or 1 level on this pin. The pin normally is supposed to be used for interrupt control. However, in simple computers it was sometimes used as a single bit output port for various purposes.
17DBIN OutputRead (the processor reads from memory or input port)
18WR OutputWrite (the processor writes to memory or output port). This is an active low output.
19SYNC OutputActive level indicates that the processor has put the "state word" on the data bus. The various bits of this state word provide added information to support the separate address and memory spaces, interrupts, and direct memory access. This signal is required to pass through additional logic before it can be used to write the processor state word from the data bus into some external register, e.g., 8238 Archived September 18, 2023, at the Wayback Machine -System Controller and Bus Driver.
20+5 V—The + 5 V power supply
21HLDA OutputDirect memory access confirmation. The processor switches data and address pins into the high impedance state, allowing another device to manipulate the bus
22φ1 InputThe first phase of the clock generator signal
23READY InputWait. With this signal it is possible to suspend the processor's work. It is also used to support the hardware-based step-by step debugging mode.
24WAIT OutputWait (indicates that the processor is in the waiting state)
25A0 Output Address bus
26A1
27A2
2812 V —The +12 V power supply. This must be the last connected and first disconnected power source.
29A3 Output The address bus; can switch into high impedance state on demand
30A4
31A5
32A6
33A7
34A8
35A9
36A15
37A12
38A13
39A14
40A11

Support chips

A key factor in the success of the 8080 was the broad range of support chips available, providing serial communications, counter/timing, input/output, direct memory access, and programmable interrupt control amongst other functions:

Physical implementation

The 8080 integrated circuit has an NMOS design, which employed non‑saturated enhancement mode transistors as loads, [18] [19] which demanded supplementary voltage levels (+12  V and −5 V) alongside the standard TTL compatible +5 V.

It was manufactured in a silicon gate process using a minimal feature size of 6 μm. A single layer of metal is used to interconnect the approximately 4,500 transistors [20] in the design, but the higher resistance polysilicon layer, which required higher voltage for some interconnects, is implemented with transistor gates. The die size is approximately 20 mm2.

Commercial impact

Applications and successors

The 8080 was used in many early microcomputers, such as the MITS Altair 8800 Computer, Processor Technology SOL-20 Terminal Computer and IMSAI 8080 Microcomputer, forming the basis for machines running the CP/M operating system (the later, almost fully compatible and more able, Zilog Z80 processor would capitalize on this, with Z80 and CP/M becoming the dominant CPU and OS combination of the period c. 1976 to 1983 much as did the x86 and DOS for the PC a decade later).

In 1979, even after the introduction of the Z80 and 8085 processors, five manufacturers of the 8080 were selling an estimated 500,000 units per month at a price around $3 to $4 each. [21]

The first single-board microcomputers, such as MYCRO-1 and the dyna-micro / MMD-1 (see: Single-board computer) were based on the Intel 8080. One of the early uses of the 8080 was made in the late 1970s by Cubic-Western Data of San Diego, California, in its Automated Fare Collection Systems custom designed for mass transit systems around the world. An early industrial use of the 8080 is as the "brain" of the DatagraphiX Auto-COM (Computer Output Microfiche) line of products which takes large amounts of user data from reel-to-reel tape and images it onto microfiche. The Auto-COM instruments also include an entire automated film cutting, processing, washing, and drying sub-system.

Several early video arcade games were built around the 8080 microprocessor. The first commercially-available arcade video game to incorporate a microprocessor was Gun Fight , Midway Games' 8080-based reimplementation of Taito's discrete-logic Western Gun , which was released in November 1975. [22] [23] [24] [25] (A pinball machine which incorporated a Motorola 6800 processor, The Spirit of '76 , had already been released the previous month. [26] [27] ) The 8080 was then used in later Midway arcade video games [28] and in Taito's 1978 Space Invaders , one of the most successful and well-known of all arcade video games. [29] [30]

Zilog introduced the Z80, which has a compatible machine language instruction set and initially used the same assembly language as the 8080, but for legal reasons, Zilog developed a syntactically-different (but code compatible) alternative assembly language for the Z80. At Intel, the 8080 was followed by the compatible and electrically more elegant 8085.

Later, Intel issued the assembly-language compatible (but not binary-compatible) 16-bit 8086 and then the 8/16-bit 8088, which was selected by IBM for its new PC to be launched in 1981. Later NEC made the NEC V20 (an 8088 clone with Intel 80186 instruction set compatibility) which also supports an 8080 emulation mode. This is also supported by NEC's V30 (a similarly enhanced 8086 clone). Thus, the 8080, via its instruction set architecture (ISA), made a lasting impact on computer history.

A number of processors compatible with the Intel 8080A were manufactured in the Eastern Bloc: the KR580VM80A (initially marked as КР580ИК80) in the Soviet Union, the MCY7880 [31] made by Unitra CEMI in Poland, the MHB8080A [32] made by TESLA in Czechoslovakia, the 8080APC [32] made by Tungsram / MEV in Hungary, and the MMN8080 [32] made by Microelectronica Bucharest in Romania.

As of 2017, the 8080 is still in production at Lansdale Semiconductors. [33]

Industry change

The 8080 also changed how computers were created. When the 8080 was introduced, computer systems were usually created by computer manufacturers such as Digital Equipment Corporation, Hewlett-Packard, or IBM. A manufacturer would produce the whole computer, including processor, terminals, and system software such as compilers and operating system. The 8080 was designed for almost any application except a complete computer system. Hewlett-Packard developed the HP 2640 series of smart terminals around the 8080. The HP 2647 is a terminal which runs the programming language BASIC on the 8080. Microsoft's founding product, Microsoft BASIC, was originally programmed for the 8080.

The 8080 and 8085 gave rise to the 8086, which was designed as a source code compatible, albeit not binary compatible, extension of the 8080. [34] This design, in turn, later spawned the x86 family of chips, which continue to be Intel's primary line of processors. Many of the 8080's core machine instructions and concepts survive in the widespread x86 platform. Examples include the registers named A, B, C, and D and many of the flags used to control conditional jumps. 8080 assembly code can still be directly translated into x86 instructions,[ vague ] since all of its core elements are still present.

Cultural impact

See also

References

  1. ↑ "CPU History – The CPU Museum – Life Cycle of the CPU". Archived from the original on January 16, 2010.
  2. ↑ Lewnes, Ann, "The Intel386 Architecture Here to Stay", Intel Corporation, Microcomputer Solutions, July/August 1989, page 2
  3. ↑ "From CPU to software, the 8080 Microcomputer is here". Electronic News. New York: Fairchild Publications. April 15, 1974. pp. 44–45. Electronic News was a weekly trade newspaper. The same advertisement appeared in the May 2, 1974, issue of Electronics magazine.
  4. ↑ The 8008 (1972) was used for interpolation and control in ASEA's (now ABB) first line of general industrial robots, introduced October 1973.
  5. ↑ Mazor, Stanley (June 1978). "The Intel 8086 Microprocessor: a 16-bit Evolution of the 8080". IEEE Computer. 11 (6): 18–27. doi:10.1109/C-M.1978.218219. S2CID   16962774. Archived from the original on September 19, 2021. Retrieved November 18, 2021.
  6. ↑ "8080A/8080A-1/8080A-2 8-Bit N Channel Microprocessor" (PDF). Intel. Archived (PDF) from the original on November 15, 2021. Retrieved November 16, 2021.
  7. 1 2 3 4 5 Miller, Michael. "Creating the 8080: The Processor That Started the PC Revolution". PCMag. Zaff Davis. Archived from the original on November 14, 2021. Retrieved November 14, 2021.
  8. ↑ Faggin, Federico. "8008 and 8080 Q&A". Microprocessor Intel 4004. Archived from the original on November 15, 2021. Retrieved November 15, 2021.
  9. ↑ Mazor, Stanley (April–June 2007). "Intel 8080 CPU Chip Development". IEEE Annals of the History of Computing. 29 (2): 70–73. doi:10.1109/MAHC.2007.25. S2CID   14755544.
  10. ↑ Shima, Masatoshi; Nishimura, Hirohiko; Ishida, Haruhisa (1979). "座談会 マイクロコンピュータの誕生 開発者 嶋 正利氏に聞く". Bit (in Japanese). 11 (11). 共立出版: 4–12. ISSN   0385-6984.
  11. ↑ Kildall, Gary Arlen (June 27, 1974). "High-level language simplifies microcomputer programming" (PDF). Electronics . McGraw-Hill Education. pp. 103–109 [108]. Archived (PDF) from the original on November 14, 2021. Retrieved November 14, 2021.
  12. ↑ "8080 Simulator INTERP/80" (PDF). Microcomputer Software. Intel Corporation. March 1975. Product Code 98-119A. MCS-516-0375/27.5K. Archived (PDF) from the original on November 25, 2023. Retrieved November 25, 2023. (2 pages)
  13. ↑ 8080 Assembly Language Programming Manual (PDF) (Rev B ed.). Intel. 1975. p. 22. Retrieved February 29, 2024.
  14. ↑ 8080 instruction encoding Archived March 5, 2018, at the Wayback Machine . ClassicCMP.org. Retrieved on October 23, 2011.
  15. ↑ Note: Some Intel datasheets from the 1970s advertise 512 I/O ports, because they count input and output ports separately.
  16. ↑ HAYES, JOHN P. (1978). Computer Architecture and Organization. McGraw-Hill. pp. 420–423. ISBN   0-07-027363-4.
  17. ↑ Intel Corporation, "8214 Priorty Interrupt Control Unit", Intel 8080 Microcomputer Systems User's Manual, September 1975, page 5-153 Archived May 28, 2024, at the Wayback Machine from bitsaver.org in PDF
  18. ↑ similar to pull-up resistors
  19. ↑ Tohya, Hirokazu (2013). Switching Mode Circuit Analysis and Design: Innovative Methodology by Novel Solitary Electromagnetic Wave Theory. Bentham Science Publishers. p. 4. ISBN   9781608054497. Archived from the original on November 15, 2021. Retrieved November 28, 2020.
  20. ↑ "Intel Chips timeline" (PDF). Intel. Intel Corporation. Archived (PDF) from the original on November 14, 2021. Retrieved November 14, 2021.
  21. ↑ Libes, Sol (November 1979). "Byte News". Byte . 11. Vol. 4. p. 82. ISSN   0360-5280.
  22. ↑ "What was the first arcade game to use a microprocessor instead of discrete logic?". Archived from the original on April 11, 2023. Retrieved April 11, 2023.
  23. ↑ Steve L. Kent (2001), The ultimate history of video games: from Pong to Pokémon and beyond : the story behind the craze that touched our lives and changed the world , p. 64, Prima, ISBN   0-7615-3643-4
  24. ↑ Akagi, Masumi (October 13, 2006). アーケードTVゲームリスト国内•海外編(1971–2005) [Arcade TV Game List: Domestic • Overseas Edition (1971–2005)] (in Japanese). Japan: Amusement News Agency. p. 124. ISBN   978-4990251215.
  25. ↑ "Dave Needle and Jerry Lawson - Two Early Independent Video Game Designers". July 29, 2013. Archived from the original on April 11, 2023. Retrieved April 11, 2023.
  26. ↑ "Internet Pinball Machine Database: Mirco Games, Inc. 'Spirit of 76'". www.ipdb.org. Archived from the original on April 16, 2023. Retrieved April 11, 2023.
  27. ↑ wayout440. "Mirco Spirit of 76 for sale – THE first solid state pin?". Pinside.com. Archived from the original on April 11, 2023. Retrieved April 11, 2023.{{cite web}}: CS1 maint: numeric names: authors list (link)
  28. ↑ "Midway 8080 System Boards". Archived from the original on April 11, 2023. Retrieved April 11, 2023.
  29. ↑ "Space Invaders Videogame by Bally Midway (1978)". Killer List of Videogames. Archived from the original on November 25, 2010. Retrieved April 11, 2023.
  30. ↑ Edwards, Benj. "Ten Things Everyone Should Know About Space Invaders". 1UP.com . Archived from the original on February 26, 2009. Retrieved April 11, 2023.
  31. ↑ MCY7880—a Polish-made clone of 8080 Archived August 17, 2016, at the Wayback Machine . CPU World. Retrieved on October 23, 2011.
  32. 1 2 3 Soviet chips and their western analogs Archived February 9, 2017, at the Wayback Machine . CPU-world. Retrieved on October 23, 2011.
  33. ↑ "Intel – Microprocessor 8080A Family & 828X Series". Lansdale Semiconductor Inc. Archived from the original on October 14, 2015. Retrieved June 20, 2017.
  34. ↑ Morse, Stephen; Ravenel, Bruce; Mazor, Stanley; Pohlman, William (October 1980). "Intel Microprocessors: 8008 to 8086" (PDF). IEEE Computer. 13 (10): 42–60. doi:10.1109/MC.1980.1653375. S2CID   206445851. Archived (PDF) from the original on September 14, 2021. Retrieved November 5, 2021.
  35. ↑ "(8080) Intel = 1958 QC = 1987 WU2 = 1989 AS5". Minor Planet Center. International Astronomical Union. Archived from the original on September 25, 2019. Retrieved November 14, 2021.

Further reading

Patent on 8080

This page is based on this Wikipedia article
Text is available under the CC BY-SA 4.0 license; additional terms may apply.
Images, videos and audio are available under their respective licenses.