Goldmont

Goldmont
General information
Product code	80668 (Apollo Lake); 80765 (Denverton);
Architecture and classification
Technology node	14 nm
Instructions	x86-64, Intel 64
Extensions	MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2 ; AES-NI, RDRAND, CLMUL, SHA ; VT-x, VT-d ;
Physical specifications
Cores	2–4;
Products, models, variants
Brand name(s)	Atom ; Celeron ; Pentium ;
History
Predecessor(s)	Airmont (die shrink)
Successor(s)	Goldmont Plus (optimization)

Last updated January 31, 2024

Goldmont is a microarchitecture for low-power Atom, Celeron and Pentium branded processors used in systems on a chip (SoCs) made by Intel. They allow only one thread per core.

The Apollo Lake platform with 14 nm Goldmont core was unveiled at the Intel Developer Forum (IDF) in Shenzhen, China, April 2016.^[1] The Goldmont architecture borrows heavily from the Skylake Core processors, so it offers a more than 30 percent performance boost compared to the previous Braswell platform, and it can be used to implement power-efficient low-end devices including Cloudbooks, 2-in-1 netbooks, small PCs, IP cameras, and in-car entertainment systems.^[2]^[3]

Design

Goldmont is the 2nd generation out-of-order low-power Atom microarchitecture designed for the entry level desktop and notebook computers.^[4] Goldmont is built on the 14 nm manufacturing process and supports up to four cores for the consumer devices. It includes the Intel Gen9 graphics architecture introduced with the Skylake.

The Goldmont microarchitecture builds on the success of the Silvermont microarchitecture, and provides the following enhancements:

An out-of-order execution engine with a 3-wide superscalar pipeline.^[5] Specifically:
- The decoder can decode 3 instructions per cycle.
- The microcode sequencer can send 3 µops per cycle for allocation into the reservation stations.
- Retirement supports a peak rate of 3 per cycle.
Enhancement in branch prediction which de-couples the fetch pipeline from the instruction decoder.
Larger out-of-order execution window and buffers that enable deeper out-of-order execution across integer, FP/SIMD, and memory instruction types.
Fully out-of-order memory execution and disambiguation. The Goldmont microarchitecture can execute one load and one store per cycle (compared to one load or one store per cycle in the Silvermont microarchitecture). The memory execution pipeline also includes a second level TLB enhancement with 512 entries for 4KB pages.
Integer execution cluster in the Goldmont microarchitecture provides three pipelines and can execute up to three simple integer ALU operations per cycle.
SIMD integer and floating-point instructions execute in a 128-bit wide engine. Throughput and latency of many instructions have improved, including PSHUFB with 1-cycle throughput (versus 5 cycles for Silvermont microarchitecture) and many other SIMD instructions with doubled throughput.
Throughput and latency of instructions for accelerating encryption/decryption (AES) and carry-less multiplication (PCLMULQDQ) have been improved significantly in the Goldmont microarchitecture.
The Goldmont microarchitecture provides new instructions with hardware accelerated secure hashing algorithm, SHA1 and SHA256.
The Goldmont microarchitecture also adds support for the RDSEED instruction for random number generation meeting the NIST SP800-90C standard.
PAUSE instruction latency is optimized to enable better power efficiency.

Technology

A 14 nm manufacturing process
System on chip architecture
3D tri-gate transistors
Consumer chips up to quad-cores
Supports SSE4.2 instruction set
Supports Intel AESNI and PCLMUL instructions
Supports Intel RDRAND and RDSEED instructions
Supports Intel SHA extensions
Supports Intel MPX (Memory Protection Extensions)
Gen 9 Intel HD Graphics with DirectX 12, OpenGL 4.6 with latest Windows 10 driver update^[6] (OpenGL 4.5 on Linux^[7]), OpenGL ES 3.2 and OpenCL 2.0 support.
HEVC Main10 & VP9 Profile0 hardware decoding support
10 W thermal design power (TDP) Desktop or Server processors
4.0 to 6.0 W TDP mobile processors
eMMC 5.0 technology to connect to NAND flash storage
USB 3.1 & USB-C specification
Support for DDR3L, LPDDR3, and LPDDR4 memory
Integrated Sensor Hub (ISH) which can sample and combine data from individual sensors and operate independently when the host platform is in a low power state
Image Signal Processor (ISP) supporting four concurrent camera streams
Audio controller supporting HD Audio and LPE Audio
Trusted Execution Engine 3.0 security subsystem

Erratum

Similar to the previous Silvermont generation, design flaws were found in processor circuitry, resulting in cease of operation when processors are actively used for several years. An Erratum named APL46 "System May Experience Inability to Boot or May Cease Operation"^[8] was added to documentation in June 2017, stating that low pin count (LPC), real time clock (RTC), SD card and GPIO interfaces may stop functioning.

Mitigations^[9] were found to limit impact on systems. A firmware update for the LPC bus called LPC_CLKRUN# reduces the utilization of the LPC interface, which in turn decreases (but does not eliminate) LPC bus degradation – some systems are however not compatible with this new firmware. It is recommended not to use SD cards as boot devices, and to remove the card from the system when not in use; other possible solutions being using only UHS-I cards and operating them at 1.8 V.

Congatec also states the issues impacts USB buses and eMMC, although those are not mentioned in Intel's public documentation. USB should have a maximum of 12% active time and there is a 60TB transmit traffic life expectancy over the lifetime of the port. eMMC should have a maximum of 33% active time and should be set to D3 device low power state by the operating system when not in use. Newer designs such as Atom C3000 Denverton do not seem to be affected.^[10]

List of Goldmont processors

Desktop processors (Apollo Lake)

List of desktop processors as follows:^[3]^[11]

Target segment	Cores (threads = cores)	Processor branding & model		GPU model		TDP (W)	CPU freq. (GHz)		GPU freq. (MHz)		L2 cache	Release date	Price (USD)
Target segment	Cores (threads = cores)	Processor branding & model		Brand name & model number	EU	TDP (W)	Base	Turbo	Base	Turbo	L2 cache	Release date	Price (USD)
Desktop	4 (4)	Pentium	J4205	HD Graphics 505	18	10	1.5	2.6	250	800	2 MB	Q3 2016	$161
	4 (4)	Celeron	J3455	HD Graphics 500	12		1.5	2.3		750			$107
	2 (2)	Celeron	J3355	HD Graphics 500	12		2.0	2.5		700			$107

Server processors (Denverton)

Target segment	Cores (threads)	Processor branding & model		TDP (W)	CPU freq. (GHz)		L2 cache	DDR4 speed	Release date	Price (USD)
Target segment	Cores (threads)	Processor branding & model		TDP (W)	Base	Turbo	L2 cache	DDR4 speed	Release date	Price (USD)
Server	16 (16)	Atom	C3958 ^[12]^[13]	31	2.0		16 MB	2400	Q3 2017	$449
	16 (16)		C3955 ^[12]	32	2.1	2.4	16 MB			$434
	12 (12)		C3858 ^[12]	25	2.0		12 MB			$332
	12 (12)		C3850 ^[12]	25	2.1	2.4				$323
	12 (12)		C3830 ^[12]	21	1.9	2.3		2133		$289
	12 (12)		C3808 ^[12]	25	2.0			2133		$369
	8 (8)		C3758 ^[12]	25	2.2		16 MB	2400		$193
	8 (8)		C3750 ^[12]	21	2.2	2.4		2400		$171
	8 (8)		C3708 ^[12]	17	1.7			2133		$209
	4 (4)		C3558 ^[12]	16	2.2		8 MB			$86
	4 (4)		C3538 ^[12]	15	2.1					$75
	4 (4)		C3508 ^[12]	11.25	1.6			1866		$86
	2 (2)		C3338 ^[12]	9	1.5	2.2	4 MB		Q1 2017	$27
	2 (2)		C3308 ^[12]	9.5	1.6	2.1	4 MB		Q3 2017	$32

Mobile processors (Apollo Lake)

List of mobile processors as follows:^[3]^[11]

Target segment	Cores (Threads)	Processor branding & model		GPU model		TDP (W)	CPU freq. (GHz)		GPU freq. (MHz)		L2 cache	Release date	Price (USD)
Target segment	Cores (Threads)	Processor branding & model		Brand name & model number	EU	TDP (W)	Base	Turbo	Base	Turbo	L2 cache	Release date	Price (USD)
Mobile	4 (4)	Pentium	N4200	HD Graphics 505	18	6	1.1	2.5	200	750	2 MB	Q3 2016	$161
	4 (4)	Celeron	N3450	HD Graphics 500	12			2.2		700			$107
	2 (2)	Celeron	N3350	HD Graphics 500	12			2.4		650			$107

Embedded processors (Apollo Lake)

List of embedded processors as follows:

Target segment	Cores (threads)	Processor branding & model		GPU model		TDP (W)	CPU freq. (GHz)		GPU freq. (MHz)		L2 cache	Release date	Price (USD)
Target segment	Cores (threads)	Processor branding & model		Brand name & model number	EU	TDP (W)	Base	Turbo	Base	Turbo	L2 cache	Release date	Price (USD)
Embedded	4 (4)	Atom x7	E3950	HD Graphics 505	18	12	1.6	2.0	500	650	2 MB	Q3 2016	?
	4 (4)	Atom x5	E3940	HD Graphics 500	12	9.5	1.6	1.8	400	600
	2 (2)	Atom x5	E3930	HD Graphics 500	12	6.5	1.3	1.8	400	550

Automotive processors (Apollo Lake)

There is also an Atom A3900 series exclusively for automotive customers with AEC-Q100 qualification:^[14]

Target segment	Cores (threads)	Processor branding & model		GPU model		TDP (W)	CPU freq. (GHz)		GPU freq. (MHz)		L2 cache	Release date	Price (USD)
Target segment	Cores (threads)	Processor branding & model		Brand name & model number	EU	TDP (W)	Base	Turbo	Normal	Turbo	L2 cache	Release date	Price (USD)
Automotive	4 (4)	Atom x7	A3960	HD Graphics 505	18	12.5	1.9	2.4	600	750	2 MB	?
		Atom x7	A3950	HD Graphics 505	18	9.5	1.6	2.0	500	650
		Atom x5	A3940	HD Graphics 500	12	8	1.6	1.8	400	600
	2 (2)	Atom x5	A3930	HD Graphics 500	12	6	1.3	1.8	400	550

Tablet processors (Willow Trail)

Willow Trail platform was canceled. Apollo Lake will be offered instead.^[15]

Related Research Articles

Celeron is a discontinued series of low-end IA-32 and x86-64 computer microprocessor models targeted at low-cost personal computers, manufactured by Intel. The first Celeron-branded CPU was introduced on April 15, 1998, and was based on the Pentium II.

Pentium 4 is a series of single-core CPUs for desktops, laptops and entry-level servers manufactured by Intel. The processors were shipped from November 20, 2000 until August 8, 2008. It was removed from the official price lists starting in 2010, being replaced by Pentium Dual-Core.

The Pentium Pro is a sixth-generation x86 microprocessor developed and manufactured by Intel and introduced on November 1, 1995. It introduced the P6 microarchitecture and was originally intended to replace the original Pentium in a full range of applications. While the Pentium and Pentium MMX had 3.1 and 4.5 million transistors, respectively, the Pentium Pro contained 5.5 million transistors. Later, it was reduced to a more narrow role as a server and high-end desktop processor and was used in supercomputers like ASCI Red, the first computer to reach the trillion floating point operations per second (teraFLOPS) performance mark in 1996. The Pentium Pro was capable of both dual- and quad-processor configurations. It only came in one form factor, the relatively large rectangular Socket 8. The Pentium Pro was succeeded by the Pentium II Xeon in 1998.

SSE2 is one of the Intel SIMD processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier SSE instruction set, and is intended to fully replace MMX. Intel extended SSE2 to create SSE3 in 2004. SSE2 added 144 new instructions to SSE, which has 70 instructions. Competing chip-maker AMD added support for SSE2 with the introduction of their Opteron and Athlon 64 ranges of AMD64 64-bit CPUs in 2003.

SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revision of their Pentium 4 CPU. In April 2005, AMD introduced a subset of SSE3 in revision E of their Athlon 64 CPUs. The earlier SIMD instruction sets on the x86 platform, from oldest to newest, are MMX, 3DNow!, SSE, and SSE2.

The NetBurst microarchitecture, called P68 inside Intel, was the successor to the P6 microarchitecture in the x86 family of central processing units (CPUs) made by Intel. The first CPU to use this architecture was the Willamette-core Pentium 4, released on November 20, 2000 and the first of the Pentium 4 CPUs; all subsequent Pentium 4 and Pentium D variants have also been based on NetBurst. In mid-2001, Intel released the Foster core, which was also based on NetBurst, thus switching the Xeon CPUs to the new architecture as well. Pentium 4-based Celeron CPUs also use the NetBurst architecture.

The P6 microarchitecture is the sixth-generation Intel x86 microarchitecture, implemented by the Pentium Pro microprocessor that was introduced in November 1995. It is frequently referred to as i686. It was planned to be succeeded by the NetBurst microarchitecture used by the Pentium 4 in 2000, but was revived for the Pentium M line of microprocessors. The successor to the Pentium M variant of the P6 microarchitecture is the Core microarchitecture which in turn is also derived from P6.

Supplemental Streaming SIMD Extensions 3 is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology.

SSE4 is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more precise details of 47 instructions became available at the Spring 2007 Intel Developer Forum in Beijing, in the presentation. SSE4 is fully compatible with software written for previous generations of Intel 64 and IA-32 architecture microprocessors. All existing software continues to run correctly without modification on microprocessors that incorporate SSE4, as well as in the presence of existing and new applications that incorporate SSE4.

Advanced Vector Extensions are SIMD extensions to the x86 instruction set architecture for microprocessors from Intel and Advanced Micro Devices (AMD). They were proposed by Intel in March 2008 and first supported by Intel with the Sandy Bridge processor shipping in Q1 2011 and later by AMD with the Bulldozer processor shipping in Q3 2011. AVX provides new features, new instructions, and a new coding scheme.

Intel Core is a line of multi-core central processing units (CPUs) for midrange, embedded, workstation and enthusiast computer markets marketed by Intel Corporation. These processors displaced the existing mid- to high-end Pentium processors at the time of their introduction, moving the Pentium to the entry level. Identical or more capable versions of Core processors are also sold as Xeon processors for the server and workstation markets.

Intel Graphics Technology (GT) is the collective name for a series of integrated graphics processors (IGPs) produced by Intel that are manufactured on the same package or die as the central processing unit (CPU). It was first introduced in 2010 as Intel HD Graphics and renamed in 2017 as Intel UHD Graphics.

Intel Quick Sync Video is Intel's brand for its dedicated video encoding and decoding hardware core. Quick Sync was introduced with the Sandy Bridge CPU microarchitecture on 9 January 2011 and has been found on the die of Intel CPUs ever since.

Silvermont is a microarchitecture for low-power Atom, Celeron and Pentium branded processors used in systems on a chip (SoCs) made by Intel. Silvermont forms the basis for a total of four SoC families:

Goldmont Plus is a microarchitecture for low-power Atom, Celeron and Pentium Silver branded processors used in systems on a chip (SoCs) made by Intel. The Gemini Lake platform with 14 nm Goldmont Plus core was officially launched on December 11, 2017. Intel launched the Gemini Lake Refresh platform on November 4, 2019.

Tremont is a microarchitecture for low-power Atom, Celeron and Pentium Silver branded processors used in systems on a chip (SoCs) made by Intel. It is the successor to Goldmont Plus. Intel officially launched Elkhart Lake platform with 10 nm Tremont core on September 23, 2020. Intel officially launched Jasper Lake platform with 10 nm Tremont core on January 11, 2021.

<span class="mw-page-title-main">Gracemont (microarchitecture)</span> CPU microarchitecture by Intel

Gracemont is a microarchitecture for low-power processors used in systems on a chip (SoCs) made by Intel, and is the successor to Tremont. Like its predecessor, it is also implemented as low-power cores in a hybrid design of the Alder Lake, Raptor Lake and Raptor Lake Refresh processors.

Willow Cove is a codename for a CPU microarchitecture developed by Intel and released in September 2020. Willow Cove is the successor to the Sunny Cove microarchitecture, and is fabricated using Intel's enhanced 10 nm process node called 10 nm SuperFin (10SF). The microarchitecture powers 11th-generation Intel Core mobile processors.

References

↑ Eric Brown (2016-04-18). ""Apollo Lake" Atoms to offer graphics-rich Goldmont cores". Hackerboards.com. Archived from the original on 2016-06-20. Retrieved 2016-06-11.
↑ Anton Shilov (2016-04-15). "Intel Unveils New Low-Cost PC Platform: Apollo Lake with 14nm Goldmont Cores". Anandtech.com. Retrieved 2016-06-11.
1 2 3 Alexander Fagot/ Allen Ngo (2016-06-07). "Intel claims Apollo Lake will be 30 percent faster than Braswell". Notebookcheck.net. Retrieved 2016-06-11.
↑ Anton Shilov (2015-06-10). "Intel preps 'Apollo Lake' CPUs with 'Goldmont' cores, Gen9 graphics" . Retrieved 2016-06-11.
↑ Kanter, David. "Goldmont Takes Atom to 14nm". The Linley Group. The Linley Group. Retrieved 17 August 2017.
↑ "Release Notes : DRIVER VERSION: 31.0.101.2115" (PDF). Downloadmirror.intel.com. Retrieved 29 December 2022.
↑ "Mesa 13.0 Released With Intel OpenGL 4.5, RADV Radeon Vulkan Driver - Phoronix". Phoronix.com.
↑ "Intel® Pentium® and Celeron® Processor N- and J- Series Specification Update" (PDF). Retrieved 2018-04-13.
↑ "Errata sheet - congatec Apollo Lake designs" (PDF). congatec. 2017-07-26. Archived from the original (PDF) on 2018-04-15. Retrieved 2018-04-15.
↑ "Intel® Atom® Processor C3000 Product Family Specification Update" (PDF). Retrieved 2018-04-13.
1 2 Gennadiy Shvets (2016-06-09). "Model numbers of Apollo Lake processors revealed". cpu-world.com. Retrieved 2016-06-11.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 Kennedy, Patrick (15 August 2017). "Intel Atom C3000 Series Launch SKUs and Differentiation". Serve the Home. Retrieved 15 August 2017.
↑ Cutress, Ian (15 August 2017). "More Denverton Noise: Gigabyte's MA1-ST0 Features Unannounced 16-Core C3958". Anandtech. Retrieved 15 August 2017.
↑ "Intel Atom® Processor E3900 and A3900 Series Datasheet Addendum" (PDF). Intel. Retrieved 12 January 2018.
↑ Ryan Smith & Ian Cutress (2016-04-29). "Intel's Changing Future: Smartphone SoCs Broxton & SoFIA Officially Cancelled". Anandtech.com.

This page is based on this Wikipedia article
Text is available under the CC BY-SA 4.0 license; additional terms may apply.
Images, videos and audio are available under their respective licenses.

[hackerboards201604-1] Eric Brown (2016-04-18). ""Apollo Lake" Atoms to offer graphics-rich Goldmont cores". Hackerboards.com. Archived from the original on 2016-06-20. Retrieved 2016-06-11.

[anandtech201604-2] Anton Shilov (2016-04-15). "Intel Unveils New Low-Cost PC Platform: Apollo Lake with 14nm Goldmont Cores". Anandtech.com. Retrieved 2016-06-11.

[notebookcheck201604-3] 1 2 3 Alexander Fagot/ Allen Ngo (2016-06-07). "Intel claims Apollo Lake will be 30 percent faster than Braswell". Notebookcheck.net. Retrieved 2016-06-11.

[kitguru201506-4] Anton Shilov (2015-06-10). "Intel preps 'Apollo Lake' CPUs with 'Goldmont' cores, Gen9 graphics" . Retrieved 2016-06-11.

[5] Kanter, David. "Goldmont Takes Atom to 14nm". The Linley Group. The Linley Group. Retrieved 17 August 2017.

[6] "Release Notes : DRIVER VERSION: 31.0.101.2115" (PDF). Downloadmirror.intel.com. Retrieved 29 December 2022.

[7] "Mesa 13.0 Released With Intel OpenGL 4.5, RADV Radeon Vulkan Driver - Phoronix". Phoronix.com.

[8] "Intel® Pentium® and Celeron® Processor N- and J- Series Specification Update" (PDF). Retrieved 2018-04-13.

[9] "Errata sheet - congatec Apollo Lake designs" (PDF). congatec. 2017-07-26. Archived from the original (PDF) on 2018-04-15. Retrieved 2018-04-15.

[10] "Intel® Atom® Processor C3000 Product Family Specification Update" (PDF). Retrieved 2018-04-13.

[cpuworld201606-11] 1 2 Gennadiy Shvets (2016-06-09). "Model numbers of Apollo Lake processors revealed". cpu-world.com. Retrieved 2016-06-11.

[sth_denverton-12] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Kennedy, Patrick (15 August 2017). "Intel Atom C3000 Series Launch SKUs and Differentiation". Serve the Home. Retrieved 15 August 2017.

[13] Cutress, Ian (15 August 2017). "More Denverton Noise: Gigabyte's MA1-ST0 Features Unannounced 16-Core C3958". Anandtech. Retrieved 15 August 2017.

[intele3900a390020181201-14] "Intel Atom® Processor E3900 and A3900 Series Datasheet Addendum" (PDF). Intel. Retrieved 12 January 2018.

[anandtech20160429-15] Ryan Smith & Ian Cutress (2016-04-29). "Intel's Changing Future: Smartphone SoCs Broxton & SoFIA Officially Cancelled". Anandtech.com.

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

[11]

[12]

[13]

[14]

[15]