|L1 cache||80 KB per core (32 KB instructions + 48 data)|
|L2 cache||1.25 MB per core (client) or 2 MB per core (server)|
|L3 cache||3 MB per core|
|Architecture and classification|
|Min. feature size||Intel 7|
|Products, models, variants|
|Product code name(s)|
|Predecessor|| Sunny Cove (server, 10 nm)|
Willow Cove (mobile, 10 nm)
Cypress Cove (desktop, 14 nm)
Golden Cove is a codename for a CPU microarchitecture developed by Intel and scheduled to be released in 2021. It will succeed three microarchitectures: Sunny Cove, Willow Cove, and Cypress Cove.It will be fabricated using Intel's 7 nm class process node called Intel 7, previously referred to as 10 nm Enhanced SuperFin (10ESF).
The microarchitecture will power the high-performance cores (P-core) of the upcoming 12th-generation Intel Core processors (codenamed "Alder Lake") and 4th-generation Xeon Scalable server processors (codenamed "Sapphire Rapids").
Intel first unveiled Golden Cove during their Architecture Day 2020.Further details were released by Intel in August 2021, during their next Architecture Day.
Similar to Skylake, Golden Cove is a major update to the core microarchitecture, with Intel stating that will "allow performance for the next decade of compute". Intel considers Golden Cove to be the largest microarchitectural upgrade to the Core family in a decade. Intel touts a 19% IPC increase over Cypress Cove.
The microarchitecture will be implemented in the high-performance cores of the twelfth generation of Intel Core hybrid processors (codenamed "Alder Lake") and the fourth generation of Xeon scalable processors (codenamed "Sapphire Rapids").
Tick–tock was a production model adopted in 2007 by chip manufacturer Intel. Under this model, every microarchitecture change (tock) was followed by a die shrink of the process technology (tick). It was replaced by the process–architecture–optimization model, which was announced in 2016 and is like a tick–tock cycle followed by an optimization phase. As a general engineering model, tick–tock is a model that refreshes one side of a binary system each release cycle.
Haswell is the codename for a processor microarchitecture developed by Intel as the "fourth-generation core" successor to the Ivy Bridge. Intel officially announced CPUs based on this microarchitecture on June 4, 2013, at Computex Taipei 2013, while a working Haswell chip was demonstrated at the 2011 Intel Developer Forum. With Haswell, which uses a 22 nm process, Intel also introduced low-power processors designed for convertible or "hybrid" ultrabooks, designated by the "U" suffix.
Intel Core are streamlined midrange consumer, workstation and enthusiast computers central processing units (CPU) marketed by Intel Corporation. These processors displaced the existing mid- to high-end Pentium processors at the time of their introduction, moving the Pentium to the entry level. Identical or more capable versions of Core processors are also sold as Xeon processors for the server and workstation markets.
Skylake is the codename used by Intel for a processor microarchitecture that was launched in August 2015 succeeding the Broadwell microarchitecture. Skylake is a microarchitecture redesign using the same 14 nm manufacturing process technology as its predecessor, serving as a "tock" in Intel's "tick–tock" manufacturing and design model. According to Intel, the redesign brings greater CPU and GPU performance and reduced power consumption. Skylake CPUs share their microarchitecture with Kaby Lake, Coffee Lake, Cannon Lake, Whiskey Lake, and Comet Lake CPUs.
Xeon Phi is a series of x86 manycore processors designed and made by Intel. It is intended for use in supercomputers, servers, and high-end workstations. Its architecture allows use of standard programming languages and application programming interfaces (APIs) such as OpenMP.
Cannon Lake is Intel's codename for the 10-nanometer die shrink of the Kaby Lake microarchitecture. As a die shrink, Cannon Lake is a new process in Intel's "Process-Architecture-Optimization" execution plan as the next step in semiconductor fabrication. Cannon Lake CPUs are the first mainstream CPUs to include the AVX-512 instruction set.
AVX-512 are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD instructions for x86 instruction set architecture (ISA) proposed by Intel in July 2013, and implemented in Intel's Xeon Phi x200 and Skylake-X CPUs; this includes the Core-X series, as well as the new Xeon Scalable Processor Family and Xeon D-2100 Embedded Series.
The Xeon D is a brand of x86 system on a chip designed, manufactured, and marketed by Intel, targeted at the microserver market. It was announced in 2014, with the first products released in 2015. Related to the Xeon brand of workstation and server processors are based on the same architecture as server-grade CPUs, with support for ECC memory, higher core counts, support for larger amounts of RAM, larger cache memory. Unique to the Xeon D line, emphasis was also made on low power consumption, and integrated hardware blocks such as a network interface controllers, a PCI express root complex, and USB and SATA controllers.
Ice Lake is Intel's codename for the 10th generation Intel Core mobile and 3rd generation Xeon Scalable server processors based on the new Sunny Cove microarchitecture. Ice Lake represents an Architecture step in Intel's Process-Architecture-Optimization model. Produced on the second generation of Intel's 10 nm process, 10 nm+, Ice Lake is Intel's second microarchitecture to be manufactured on the 10 nm process, following the limited launch of Cannon Lake in 2018. However, Intel altered their naming scheme in 2020 for the 10 nm process. In this new naming scheme, Ice Lake's manufacturing process is called simply 10 nm, without any appended pluses.
EPYC is a brand of x86-64 microprocessors designed and sold by AMD, based on the company's Zen microarchitecture. Introduced in June 2017, they are specifically targeted for the server and embedded system markets. Epyc processors share the same microarchitecture as their regular desktop-grade counterparts, but have enterprise-grade features such as higher core counts, more PCI Express lanes, support for larger amounts of RAM, and larger cache memory. They also support multi-chip and dual-socket system configurations by using Infinity Fabric interchip interconnect.
Sapphire Rapids is a codename for Intel's next generation Xeon server processors based on Intel 7, which is rebranded 10 Enhanced SuperFin process. Sapphire Rapids CPUs are designed for data centers; the roughly contemporary Alder Lake is intended for the wider public.
Intel Xe, earlier known unofficially as Gen12, is GPU architecture developed by Intel.
Cooper Lake is Intel's codename for the third-generation of their Xeon scalable processors, developed as the successor to Cascade Lake. Cascade Lake processors are targeted at the 4S and 8S segments of the server market; Ice Lake-SP serves the 1S and 2S segment.
Sunny Cove is a codename for a CPU microarchitecture developed by Intel, first released in September 2019. It succeeds the Palm Cove microarchitecture and is fabricated using Intel's 10 nm process node. The microarchitecture is implemented in 10th-generation Intel Core processors for mobile and third generation Xeon scalable server processors. 10th-generation Intel Core mobile processors were released in September 2019, while the Xeon server processors were released in April 6, 2021.
Rocket Lake is Intel's codename for its 11th generation Core microprocessors. Released on March 30, 2021, it is based on the new Cypress Cove microarchitecture, a variant of Sunny Cove backported to Intel's 14 nm process node. Rocket Lake cores contain significantly more transistors than current Skylake-derived Comet Lake cores.
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Alder Lake is Intel's codename for the 12th-generation of Intel Core processors based on a hybrid architecture utilizing Golden Cove high-performance cores and Gracemont power-efficient cores. Intel expects to launch Alder Lake on November 19th, 2021. It is to be fabricated using Intel's Intel 7 process, previously referred to as Intel 10 nm Enhanced SuperFin (10ESF).
Gracemont is an upcoming microarchitecture for low-power processors used in systems on a chip (SoCs) made by Intel, and is the successor to Tremont. Like its predecessor, it will also be implemented as low-power cores in a hybrid design of the upcoming Alder Lake processors.
Willow Cove is a codename for a CPU microarchitecture developed by Intel and released on September 2020. Willow Cove is the successor to the Sunny Cove microarchitecture, and is fabricated using Intel's enhanced 10 nm process node called 10 nm SuperFin (10SF). The microarchitecture powers 11th-generation Intel Core mobile processors.