SSE4

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SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; [1] more precise details of 47 instructions became available at the Spring 2007 Intel Developer Forum in Beijing, in the presentation. [2] SSE4 is fully compatible with software written for previous generations of Intel 64 and IA-32 architecture microprocessors. All existing software continues to run correctly without modification on microprocessors that incorporate SSE4, as well as in the presence of existing and new applications that incorporate SSE4. [3]

Contents

SSE4 subsets

Intel SSE4 consists of 54 instructions. A subset consisting of 47 instructions, referred to as SSE4.1 in some Intel documentation, is available in Penryn. Additionally, SSE4.2, a second subset consisting of the seven remaining instructions, is first available in Nehalem-based Core i7. Intel credits feedback from developers as playing an important role in the development of the instruction set.

Starting with Barcelona-based processors, AMD introduced the SSE4a instruction set, which has four SSE4 instructions and four new SSE instructions. These instructions are not found in Intel's processors supporting SSE4.1 and AMD processors only started supporting Intel's SSE4.1 and SSE4.2 (the full SSE4 instruction set) in the Bulldozer-based FX processors. With SSE4a the misaligned SSE feature was also introduced which meant unaligned load instructions were as fast as aligned versions on aligned addresses. It also allowed disabling the alignment check on non-load SSE operations accessing memory. [4] Intel later introduced similar speed improvements to unaligned SSE in their Nehalem processors, but did not introduce misaligned access by non-load SSE instructions until AVX. [5]

Name confusion

What is now known as SSSE3 (Supplemental Streaming SIMD Extensions 3), introduced in the Intel Core 2 processor line, was referred to as SSE4 by some media until Intel came up with the SSSE3 moniker. Internally dubbed Merom New Instructions, Intel originally did not plan to assign a special name to them, which was criticized by some journalists. [6] Intel eventually cleared up the confusion and reserved the SSE4 name for their next instruction set extension. [7]

Intel is using the marketing term HD Boost to refer to SSE4. [8]

New instructions

Unlike all previous iterations of SSE, SSE4 contains instructions that execute operations which are not specific to multimedia applications. It features a number of instructions whose action is determined by a constant field and a set of instructions that take XMM0 as an implicit third operand.

Several of these instructions are enabled by the single-cycle shuffle engine in Penryn. (Shuffle operations reorder bytes within a register.)

SSE4.1

These instructions were introduced with Penryn microarchitecture, the 45 nm shrink of Intel's Core microarchitecture. Support is indicated via the CPUID.01H:ECX.SSE41[Bit 19] flag.

InstructionDescription
MPSADBWCompute eight offset sums of absolute differences, four at a time (i.e., |x0−y0|+|x1−y1|+|x2−y2|+|x3−y3|, |x0−y1|+|x1−y2|+|x2−y3|+|x3−y4|, ..., |x0−y7|+|x1−y8|+|x2−y9|+|x3−y10|); this operation is important for some HD codecs, and allows an 8×8 block difference to be computed in fewer than seven cycles. [9] One bit of a three-bit immediate operand indicates whether y0 .. y10 or y4 .. y14 should be used from the destination operand, the other two whether x0..x3, x4..x7, x8..x11 or x12..x15 should be used from the source.
PHMINPOSUWSets the bottom unsigned 16-bit word of the destination to the smallest unsigned 16-bit word in the source, and the next-from-bottom to the index of that word in the source.
PMULDQPacked 32-bit signed "long" multiplication, two (1st and 3rd) out of four packed integers multiplied giving two packed 64-bit results.
PMULLDPacked 32-bit signed "low" multiplication, four packed sets of integers multiplied giving four packed 32-bit results.
DPPS, DPPD Dot product for AOS (Array of Structs) data. This takes an immediate operand consisting of four (or two for DPPD) bits to select which of the entries in the input to multiply and accumulate, and another four (or two for DPPD) to select whether to put 0 or the dot-product in the appropriate field of the output.
BLENDPS, BLENDPD, BLENDVPS, BLENDVPD, PBLENDVB, PBLENDWConditional copying of elements in one location with another, based (for non-V form) on the bits in an immediate operand, and (for V form) on the bits in register XMM0.
PMINSB, PMAXSB, PMINUW, PMAXUW, PMINUD, PMAXUD, PMINSD, PMAXSDPacked minimum/maximum for different integer operand types
ROUNDPS, ROUNDSS, ROUNDPD, ROUNDSDRound values in a floating-point register to integers, using one of four rounding modes specified by an immediate operand
INSERTPS, PINSRB, PINSRD/​PINSRQ, EXTRACTPS, PEXTRB, PEXTRD/PEXTRQThe INSERTPS and PINSR instructions read 8, 16 or 32 bits from an x86 register or memory location and inserts it into a field in the destination register given by an immediate operand. EXTRACTPS and PEXTR read a field from the source register and insert it into an x86 register or memory location. For example, PEXTRD eax, [xmm0], 1; EXTRACTPS [addr+4*eax], xmm1, 1 stores the first field of xmm1 in the address given by the first field of xmm0.
PMOVSXBW, PMOVZXBW, PMOVSXBD, PMOVZXBD, PMOVSXBQ, PMOVZXBQ, PMOVSXWD, PMOVZXWD, PMOVSXWQ, PMOVZXWQ, PMOVSXDQ, PMOVZXDQPacked sign/zero extension to wider types
PTESTThis is similar to the TEST instruction, in that it sets the Z flag to the result of an AND between its operands: ZF is set, if DEST AND SRC is equal to 0. Additionally it sets the C flag if (NOT DEST) AND SRC equals zero.

This is equivalent to setting the Z flag if none of the bits masked by SRC are set, and the C flag if all of the bits masked by SRC are set.

PCMPEQQQuadword (64 bits) compare for equality
PACKUSDWConvert signed DWORDs into unsigned WORDs with saturation.
MOVNTDQAEfficient read from write-combining memory area into SSE register; this is useful for retrieving results from peripherals attached to the memory bus.

SSE4.2

SSE4.2 added STTNI (String and Text New Instructions), [10] several new instructions that perform character searches and comparison on two operands of 16 bytes at a time. These were designed (among other things) to speed up the parsing of XML documents. [11] It also added a CRC32 instruction to compute cyclic redundancy checks as used in certain data transfer protocols. These instructions were first implemented in the Nehalem-based Intel Core i7 product line and complete the SSE4 instruction set. Support is indicated via the CPUID.01H:ECX.SSE42[Bit 20] flag.

InstructionDescription
CRC32Accumulate CRC32C value using the polynomial 0x11EDC6F41 (or, without the high order bit, 0x1EDC6F41). [12] [13]
PCMPESTRIPacked Compare Explicit Length Strings, Return Index
PCMPESTRMPacked Compare Explicit Length Strings, Return Mask
PCMPISTRIPacked Compare Implicit Length Strings, Return Index
PCMPISTRMPacked Compare Implicit Length Strings, Return Mask
PCMPGTQCompare Packed Signed 64-bit data For Greater Than

POPCNT and LZCNT

These instructions operate on integer rather than SSE registers, because they are not SIMD instructions, but appear at the same time and although introduced by AMD with the SSE4a instruction set, they are counted as separate extensions with their own dedicated CPUID bits to indicate support. Intel implements POPCNT beginning with the Nehalem microarchitecture and LZCNT beginning with the Haswell microarchitecture. AMD implements both beginning with the Barcelona microarchitecture.

AMD calls this pair of instructions Advanced Bit Manipulation (ABM).

InstructionDescription
POPCNT Population count (count number of bits set to 1). Support is indicated via the CPUID.01H:ECX.POPCNT[Bit 23] flag. [14]
LZCNT Leading zero count. Support is indicated via the CPUID.80000001H:ECX.ABM[Bit 5] flag. [15]

The encoding of LZCNT takes the same encoding path as the encoding of the BSR (bit scan reverse) instruction. This results in an issue where LZCNT called on some CPUs not supporting it, such as Intel CPUs prior to Haswell, may incorrectly execute the BSR operation instead of raising an invalid instruction exception. This is an issue as the result values of LZCNT and BSR are different.

Trailing zeros can be counted using the BSF (bit scan forward) or TZCNT instructions.

Windows 11 24H2 requires the CPU must be support POPCNT and LZCNT, otherwise the Windows kernel is unbootable. [16]

SSE4a

The SSE4a instruction group was introduced in AMD's Barcelona microarchitecture. These instructions are not available in Intel processors. Support is indicated via the CPUID.80000001H:ECX.SSE4A[Bit 6] flag. [15]

InstructionDescription
EXTRQ/​INSERTQCombined mask-shift instructions. [17]
MOVNTSD/​MOVNTSSScalar streaming store instructions. [18]

Supporting CPUs

Related Research Articles

In computing, Streaming SIMD Extensions (SSE) is a single instruction, multiple data (SIMD) instruction set extension to the x86 architecture, designed by Intel and introduced in 1999 in their Pentium III series of central processing units (CPUs) shortly after the appearance of Advanced Micro Devices (AMD's) 3DNow!. SSE contains 70 new instructions, most of which work on single precision floating-point data. SIMD instructions can greatly increase performance when exactly the same operations are to be performed on multiple data objects. Typical applications are digital signal processing and graphics processing.

<span class="mw-page-title-main">Pentium III</span> Line of desktop and mobile microprocessors produced by Intel

The Pentium III brand refers to Intel's 32-bit x86 desktop and mobile CPUs based on the sixth-generation P6 microarchitecture introduced on February 28, 1999. The brand's initial processors were very similar to the earlier Pentium II-branded processors. The most notable differences were the addition of the Streaming SIMD Extensions (SSE) instruction set, and the introduction of a controversial serial number embedded in the chip during manufacturing. The Pentium III is also a single-core processor. This is also techically the oldest intel processor to support Windows 11, Since the Last Pentium lll processors can go up to 1.4 gigahertz, While Requirements for 32-bit Windows 11 are a 1 gigahertz CPU, Via mods like Tiny11.

SSE2 is one of the Intel SIMD processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier SSE instruction set, and is intended to fully replace MMX. Intel extended SSE2 to create SSE3 in 2004. SSE2 added 144 new instructions to SSE, which has 70 instructions. Competing chip-maker AMD added support for SSE2 with the introduction of their Opteron and Athlon 64 ranges of AMD64 64-bit CPUs in 2003.

SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revision of their Pentium 4 CPU. In April 2005, AMD introduced a subset of SSE3 in revision E of their Athlon 64 CPUs. The earlier SIMD instruction sets on the x86 platform, from oldest to newest, are MMX, 3DNow!, SSE, and SSE2.

The x86 instruction set refers to the set of instructions that x86-compatible microprocessors support. The instructions are usually part of an executable program, often stored as a computer file and executed on the processor.

<span class="mw-page-title-main">P6 (microarchitecture)</span> Intel processor microarchitecture

The P6 microarchitecture is the sixth-generation Intel x86 microarchitecture, implemented by the Pentium Pro microprocessor that was introduced in November 1995. It is frequently referred to as i686. It was planned to be succeeded by the NetBurst microarchitecture used by the Pentium 4 in 2000, but was revived for the Pentium M line of microprocessors. The successor to the Pentium M variant of the P6 microarchitecture is the Core microarchitecture which in turn is also derived from P6.

The Intel Core microarchitecture is a multi-core processor microarchitecture launched by Intel in mid-2006. It is a major evolution over the Yonah, the previous iteration of the P6 microarchitecture series which started in 1995 with Pentium Pro. It also replaced the NetBurst microarchitecture, which suffered from high power consumption and heat intensity due to an inefficient pipeline designed for high clock rate. In early 2004 the new version of NetBurst (Prescott) needed very high power to reach the clocks it needed for competitive performance, making it unsuitable for the shift to dual/multi-core CPUs. On May 7, 2004 Intel confirmed the cancellation of the next NetBurst, Tejas and Jayhawk. Intel had been developing Merom, the 64-bit evolution of the Pentium M, since 2001, and decided to expand it to all market segments, replacing NetBurst in desktop computers and servers. It inherited from Pentium M the choice of a short and efficient pipeline, delivering superior performance despite not reaching the high clocks of NetBurst.

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<span class="mw-page-title-main">Penryn (microprocessor)</span>

Penryn is the code name of a processor from Intel that is sold in varying configurations as Core 2 Solo, Core 2 Duo, Core 2 Quad, Pentium and Celeron.

<span class="mw-page-title-main">Wolfdale (microprocessor)</span>

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Bit manipulation instructions sets are extensions to the x86 instruction set architecture for microprocessors from Intel and AMD. The purpose of these instruction sets is to improve the speed of bit manipulation. All the instructions in these sets are non-SIMD and operate only on general-purpose registers.

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References

  1. ↑ Intel Streaming SIMD Extensions 4 (SSE4) Instruction Set Innovation Archived May 30, 2009, at the Wayback Machine , Intel.
  2. ↑ Tuning for Intel SSE4 for the 45nm Next Generation Intel Core Microarchitecture Archived March 8, 2021, at the Wayback Machine , Intel.
  3. ↑ "Intel SSE4 Programming Reference" (PDF). Archived (PDF) from the original on February 15, 2020. Retrieved December 26, 2014.
  4. ↑ ""Barcelona" Processor Feature: SSE Misaligned Access". AMD. Archived from the original on August 9, 2016. Retrieved March 3, 2015.
  5. ↑ "Inside Intel Nehalem Microarchitecture". Archived from the original on April 2, 2015. Retrieved March 3, 2015.
  6. ↑ My Experience With "Conroe" Archived October 15, 2013, at the Wayback Machine , DailyTech
  7. ↑ Extending the World’s Most Popular Processor Architecture Archived November 24, 2011, at the Wayback Machine , Intel
  8. ↑ "Intel - Data Center Solutions, IOT, and PC Innovation". Intel. Archived from the original on February 7, 2013. Retrieved September 17, 2009.
  9. ↑ Motion Estimation with Intel Streaming SIMD Extensions 4 (Intel SSE4) Archived June 16, 2018, at the Wayback Machine , Intel.
  10. ↑ "Schema Validation with Intel® Streaming SIMD Extensions 4 (Intel® SSE4)". Archived from the original on June 17, 2018. Retrieved February 6, 2012.
  11. ↑ "XML Parsing Accelerator with Intel® Streaming SIMD Extensions 4 (Intel® SSE4)". Archived from the original on June 17, 2018. Retrieved February 6, 2012.
  12. ↑ Intel SSE4 Programming Reference Archived February 15, 2020, at the Wayback Machine p. 61. See also RFC 3385 Archived June 19, 2008, at the Wayback Machine for discussion of the CRC32C polynomial.
  13. ↑ Fast, Parallelized CRC Computation Using the Nehalem CRC32 Instruction — Dr. Dobbs, April 12, 2011
  14. ↑ Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2B: Instruction Set Reference, N–Z Archived March 8, 2011, at the Wayback Machine .
  15. 1 2 "AMD CPUID Specification" (PDF). Archived (PDF) from the original on November 1, 2013. Retrieved October 30, 2013.
  16. ↑ Neowin ·, Sayan Sen (March 17, 2024). "Microsoft fixes a misfired PopCnt block but Windows 11 24H2 requirements may be here to stay". Neowin. Retrieved March 17, 2024.
  17. ↑ Rahul Chaturvedi (September 17, 2007). ""Barcelona" Processor Feature: SSE4a Instruction Set". Archived from the original on October 25, 2013.
  18. ↑ Rahul Chaturvedi (October 2, 2007). ""Barcelona" Processor Feature: SSE4a, part 2". Archived from the original on October 25, 2013.
  19. ↑ "AMD FX-Series FX-6300 - FD6300WMW6KHK / FD6300WMHKBOX". Archived from the original on August 17, 2017. Retrieved October 9, 2015.

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