DEC Alpha

Last updated
Designer Digital Equipment Corporation
Bits 64-bit
Design RISC
Encoding Fixed
Endianness Bi
ExtensionsByte/Word Extension (BWX), Square-root and Floating-point Convert Extension (FIX), Count Extension (CIX), Motion Video Instructions (MVI)
OpenYes [1]
General purpose 31 plus always-zero R31
Floating point 31 plus always-0.0 F31
DEC Alpha AXP 21064 microprocessor die photo Alpha AXP 21064 diephoto1.jpg
DEC Alpha AXP 21064 microprocessor die photo
Package for DEC Alpha AXP 21064 microprocessor DEC Alpha 21-35023-13 J40793-28 top.jpg
Package for DEC Alpha AXP 21064 microprocessor
Alpha AXP 21064 bare die mounted on a business card with some statistics Alpha AXP 21064 card1.jpg
Alpha AXP 21064 bare die mounted on a business card with some statistics
Compaq Alpha 21264C KL Compaq DEC ALPHA 21264C.jpg
Compaq Alpha 21264C

Alpha, originally known as Alpha AXP, is a 64-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC), designed to replace their 32-bit VAX complex instruction set computer (CISC) ISA. Alpha was implemented in microprocessors originally developed and fabricated by DEC. These microprocessors were most prominently used in a variety of DEC workstations and servers, which eventually formed the basis for almost all of their mid-to-upper-scale lineup. Several third-party vendors also produced Alpha systems, including PC form factor motherboards.


Operating systems that supported Alpha included OpenVMS (previously known as OpenVMS AXP), Tru64 UNIX (previously known as DEC OSF/1 AXP and Digital UNIX), Windows NT (discontinued after NT 4.0; and pre-release Windows 2000 RC1), [2] Linux (Debian, SUSE, [3] Gentoo and Red Hat), BSD UNIX (NetBSD, OpenBSD and FreeBSD up to 6.x), Plan 9 from Bell Labs, as well as the L4Ka::Pistachio kernel. The Alpha architecture was sold, along with most parts of DEC, to Compaq in 1998. [4] Compaq, already an Intel customer, phased out Alpha in favor of the forthcoming Hewlett-Packard/Intel Itanium architecture, and sold all Alpha intellectual property to Intel in 2001, effectively killing the product. Hewlett-Packard purchased Compaq later that same year, continuing development of the existing product line until 2004, and selling Alpha-based systems, largely to the existing customer base, until April 2007. [5]



Alpha was born out of an earlier RISC project named Prism (Parallel Reduced Instruction Set Machine), itself the product of several earlier projects. PRISM was intended to be a flexible design, supporting both Unix-like applications, as well as Digital's existing VMS programs from the VAX after minor conversion. A new Unix-like [6] [7] operating system known as Mica would run applications natively, supporting VMS under emulation running at the same time.

During development, the Palo Alto design team were working on a Unix-only workstation that originally included the PRISM. However, development of the workstation was well ahead of the PRISM, and the engineers proposed that they release the machines using the MIPS R2000 processor instead, [8] moving its release date up considerably. DEC management doubted the need to produce a new computer architecture to replace their existing VAX and DECstation lines, and eventually ended the PRISM project in 1988. [9]

By the time of cancellation, however, second-generation RISC chips (such as the newer SPARC architecture) were offering much better price/performance ratios than the VAX lineup. It was clear a third generation would completely outperform the VAX in all ways, not just on cost.


Another study was started to see if a new RISC architecture could be defined that could directly support the VMS operating system. The new design used most of the basic PRISM concepts, but was re-tuned to allow VMS and VMS programs to run at reasonable speed with no conversion at all. The decision was also made to upgrade the design to a full 64-bit implementation from PRISM's 32-bit, a conversion all of the major RISC vendors were undertaking. Eventually that new architecture became Alpha. The primary Alpha instruction set architects were Richard L. Sites and Richard T. Witek. [10] The PRISM's Epicode was developed into the Alpha's PALcode, providing an abstracted interface to platform- and processor implementation-specific features.

The main contribution of Alpha to the microprocessor industry, and the main reason for its performance, was not so much the architecture but rather its implementation. [11] At that time (as it is now), the microchip industry was dominated by automated design and layout tools. The chip designers at Digital continued pursuing sophisticated manual circuit design in order to deal with the overly complex VAX architecture. The Alpha chips showed that manual circuit design applied to a simpler, cleaner architecture allowed for much higher operating frequencies than those that were possible with the more automated design systems. These chips caused a renaissance of custom circuit design within the microprocessor design community.

Originally, the Alpha processors were designated the DECchip 21x64 series, [12] with "DECchip" replaced in the mid-1990s with "Alpha". The first two digits, "21" signifies the 21st century, and the last two digits, "64" signifies 64 bits. [12] The Alpha was designed as 64-bit from the start and there is no 32-bit version. The middle digit corresponded to the generation of the Alpha architecture. Internally, Alpha processors were also identified by EV numbers, EV officially standing for "Extended VAX" but having an alternative humorous meaning of "Electric Vlasic", giving homage to the Electric Pickle experiment at Western Research Lab. [13]

Improved models

The first few generations of the Alpha chips were some of the most innovative of their time.

A persistent report attributed to DEC insiders suggests the choice of the AXP tag for the processor was made by DEC's legal department, which was still smarting from the VAX trademark fiasco. [17] After a lengthy search the tag "AXP" was found to be entirely unencumbered. Within the computer industry, a joke got started that the acronym AXP meant "Almost eXactly PRISM".

Design principles

The Alpha architecture was intended to be a high-performance design. Digital intended the architecture to support a one-thousandfold increase in performance over twenty-five years. To ensure this, any architectural feature that impeded multiple instruction issue, clock rate or multiprocessing was removed. As a result, the Alpha does not have:

Condition codes

The Alpha does not have condition codes for integer instructions [20] to remove a potential bottleneck at the condition status register. Instructions resulting in an overflow, such as adding two numbers whose result does not fit in 64 bits, write the 32 or 64 least significant bits to the destination register. The carry is generated by performing an unsigned compare on the result with either operand to see if the result is smaller than either operand. If the test was true, the value one is written to the least significant bit of the destination register to indicate the condition.


DEC Alpha registers
63. . .47. . .31. . .15. . .0100(bit position)
General-purpose registers
R31 (zero)R31, always zero
Floating-point registers
F31 (zero)F31, always zero
Program counter
PC00Program Counter
Control registers
LR0Lock Register 0
LR1Lock Register 1
FPCRFPControl Register

The architecture defined a set of 32 integer registers and a set of 32 floating-point registers in addition to a program counter, two lock registers and a floating-point control register (FPCR). It also defined registers that were optional, implemented only if the implementation required them. Lastly, registers for PALcode were defined.

The integer registers were denoted by R0 to R31 and floating-point registers were denoted by F0 to F31. The R31 and F31 registers were hardwired to zero and writes to those registers by instructions are ignored. Digital considered using a combined register file, but a split register file was determined to be better as it enabled two-chip implementations to have a register file located on each chip and integer-only implementations to omit the floating-point register file containing the floating point registers. A split register file was also determined to be more suitable for multiple instruction issue due to the reduced number of read and write ports. The number of registers per register file was also considered, with 32 and 64 being contenders. Digital concluded that 32 registers was more suitable as it required less die space, which improved clock frequencies. This number of registers was deemed not to be a major issue in respect to performance and future growth, as thirty-two registers could support at least eight-way instruction issue.

The program counter is a 64-bit register which contains a longword-aligned virtual byte address, that is, the low two bits of the program counter are always zero. The PC is incremented by four to the address of the next instruction when an instruction is decoded. A lock flag and locked physical address register are used by the load-locked and store-conditional instructions for multiprocessor support. The floating-point control register (FPCR) is a 64-bit register defined by the architecture intended for use by Alpha implementations with IEEE 754-compliant floating-point hardware.

Data types

In the Alpha architecture, a byte was defined as an 8-bit datum (octet), a word as a 16-bit datum, a longword as a 32-bit datum, a quadword as a 64-bit datum, and an octaword as a 128-bit datum.

The Alpha architecture originally defined six data types:

To maintain a level of compatibility with the VAX, the 32-bit architecture that preceded the Alpha, two other floating-point data types were included:


The Alpha has a 64-bit linear virtual address space with no memory segmentation. Implementations can implement a smaller virtual address space with a minimum size of 43 bits. Although the unused bits were not implemented in hardware such as TLBs, the architecture required implementations to check whether they are zero to ensure software compatibility with implementations with a larger (or full) virtual address space.

Instruction formats

The Alpha ISA has a fixed instruction length of 32 bits. It has six instruction formats.

OpcodeRaRbUnused0FunctionRcInteger operate
OpcodeRaLiteral1FunctionRcInteger operate, literal
OpcodeRaRbFunctionRcFloating-point operate
OpcodeRaRbDisplacementMemory format
OpcodeRaDisplacementBranch format
OpcodeFunctionCALL_PAL format

The integer operate format is used by integer instructions. It contains a 6-bit opcode field, followed by the Ra field, which specifies the register containing the first operand and the Rb field, specifies the register containing the second operand. Next is a 3-bit field which is unused and reserved. A 1-bit field contains a "0", which distinguished this format from the integer literal format. A 7-bit function field follows, which is used in conjunction with the opcode to specify an operation. The last field is the Rc field, which specifies the register which the result of a computation should be written to. The register fields are all 5 bits long, required to address 32 unique locations, the 32 integer registers.

The integer literal format is used by integer instructions which use a literal as one of the operands. The format is the same as the integer operate format except for the replacement of the 5-bit Rb field and the 3 bits of unused space with an 8-bit literal field which is zero-extended to a 64-bit operand.

The floating-point operate format is used by floating-point instructions. It is similar to the integer operate format, but has an 11-bit function field made possible by using the literal and unused bits which are reserved in integer operate format.

The memory format is used mostly by load and store instructions. It has a 6-bit opcode field, a 5-bit Ra field, a 5-bit Rb field and a 16-bit displacement field.

Branch instructions have a 6-bit opcode field, a 5-bit Ra field and a 21-bit displacement field. The Ra field specifies a register to be tested by a conditional branch instruction, and if the condition is met, the program counter is updated by adding the contents of the displacement field with the program counter. The displacement field contains a signed integer and if the value of the integer is positive, if the branch is taken then the program counter is incremented. If the value of the integer is negative, then program counter is decremented if the branch is taken. The range of a branch thus is ±1 Mi instructions, or ±4 MiB. The Alpha Architecture was designed with a large range as part of the architecture's forward-looking goal.

The CALL_PAL format is used by the CALL_PAL instruction, which is used to call PALcode subroutines. The format retains the opcode field but replaces the others with a 26-bit function field, which contains an integer specifying a PAL subroutine.

Instruction set

Control instructions

The control instructions consist of conditional and unconditional branches, and jumps. The conditional and unconditional branch instructions use the branch instruction format, while the jump instructions use the memory instruction format.

Conditional branches test whether the least significant bit of a register is set or clear, or compare a register as a signed quadword to zero, and branch if the specified condition is true. The conditions available for comparing a register to zero are equality, inequality, less than, less than or equal to, greater than or equal to, and greater than. The new address is computed by longword aligning and sign extending the 21-bit displacement and adding it to the address of the instruction following the conditional branch.

Unconditional branches update the program counter with a new address computed in the same way as conditional branches. They also save the address of the instruction following the unconditional branch to a register. There are two such instructions, and they differ only in the hints provided for the branch prediction hardware.

There are four jump instructions. These all perform the same operation, saving the address of the instruction following the jump, and providing the program counter with a new address from a register. They differ in the hints provided to the branch prediction hardware. The unused displacement field is used for this purpose.

Integer arithmetic

The integer arithmetic instructions perform addition, multiplication, and subtraction on longwords and quadwords; and comparison on quadwords. There is no instruction(s) for division as the architects considered the implementation of division in hardware to be adverse to simplicity. In addition to the standard add and subtract instructions, there are scaled versions. These versions shift the second operand to the left by two or three bits before adding or subtracting. The Multiply Longword and Multiply Quadword instructions write the least significant 32 or 64 bits of a 64- or 128-bit result to the destination register, respectively. Since it is useful to obtain the most significant half, the Unsigned Multiply Quadword High (UMULH) instruction is provided. UMULH is used for implementing multi-precision arithmetic and division algorithms. The concept of a separate instruction for multiplication that returns the most significant half of a result was taken from PRISM.

The instructions that operate on longwords ignore the most significant half of the register and the 32-bit result is sign-extended before it is written to the destination register. By default, the add, multiply, and subtract instructions, with the exception of UMULH and scaled versions of add and subtract, do not trap on overflow. When such functionality is required, versions of these instructions that perform overflow detection and trap on overflow are provided.

The compare instructions compare two registers or a register and a literal and write '1' to the destination register if the specified condition is true or '0' if not. The conditions are equality, inequality, less than or equal to, and less than. With the exception of the instructions that specify the former two conditions, there are versions that perform signed and unsigned compares.

The integer arithmetic instructions use the integer operate instruction formats.

Logical and shift

The logical instructions consist of those for performing bitwise logical operations and conditional moves on the integer registers. The bitwise logical instructions perform AND, NAND, NOR, OR, XNOR, and XOR between two registers or a register and literal. The conditional move instructions test a register as a signed quadword to zero and move if the specified condition is true. The specified conditions are equality, inequality, less than or equal to, less than, greater than or equal to, and greater than. The shift instructions perform arithmetic right shift, and logical left and right shifts. The shift amount is given by a register or literal. Logical and shift instructions use the integer operate instruction formats.


Byte-Word Extensions (BWX)

Later, the Alpha included byte-word extensions, a set of instructions to manipulate 8-bit and 16-bit data types. These instructions were first introduced in the 21164A (EV56) microprocessor and are present in all subsequent implementations. These instructions performed operations that previously required multiple instructions to implement, which improved code density and the performance of certain applications. BWX also made the emulation of x86 machine code and the writing of device drivers easier. [23]

LDBULoad Zero-Extended Byte from Memory to Register
LDWULoad Zero-Extended Word from Memory to Register
SEXTBSign Extend Byte
SEXTWSign Extend Word
STBStore Byte from Register to Memory
STWStore Word from Register to Memory

Motion Video Instructions (MVI)

Motion Video Instructions (MVI) was an instruction set extension to the Alpha ISA that added instructions for single instruction, multiple data (SIMD) operations. [24] Alpha implementations that implement MVI, in chronological order, are the Alpha 21164PC (PCA56 and PCA57), Alpha 21264 (EV6) and Alpha 21364 (EV7). Unlike most other SIMD instruction sets of the same period, such as MIPS' MDMX or SPARC's Visual Instruction Set, but like PA-RISC's Multimedia Acceleration eXtensions (MAX-1, MAX-2), MVI was a simple instruction set composed of a few instructions that operate on integer data types stored in existing integer registers.

MVI's simplicity was due to two reasons. Firstly, Digital had determined that the Alpha 21164 was already capable of performing DVD decoding through software, therefore not requiring hardware provisions for the purpose, but was inefficient in MPEG-2 encoding. The second reason was the requirement to retain the fast cycle times of implementations. Adding many instructions would have complicated and enlarged the instruction decode logic, reducing an implementation's clock frequency.

MVI consisted of 13 instructions:

MAXSB8Vector Signed Byte Maximum
MAXSW4Vector Signed Word Maximum
MAXUB8Vector Unsigned Byte Maximum
MAXUW4Vector Unsigned Word Maximum
MINSB8Vector Signed Byte Minimum
MINSW4Vector Signed Word Minimum
MINUB8Vector Unsigned Byte Minimum
MINUW4Vector Unsigned Word Minimum
PERRPixel Error
PKLBPack Longwords to Bytes
PKWBPack Words to Bytes
UNPKBLUnpack Bytes to Longwords
UNPKBWUnpack Bytes to Words

Floating-point Extensions (FIX)

Floating-point extensions (FIX) was an extension the Alpha Architecture. It introduced nine instructions for floating-point square-root and for transferring data to and from the integer registers and floating-point registers. The Alpha 21264 (EV6) was the first microprocessor to implement these instructions.

FTOISFloating-point to Integer Register Move, S_floating
FTOITFloating-point to Integer Register Move, T_floating
ITOFFInteger to Floating-point Register Move, F_floating
ITOFSInteger to Floating-point Register Move, S_floating
ITOFTInteger to Floating-point Register Move, T_floating
SQRTFSquare root F_floating
SQRTGSquare root G_floating
SQRTSSquare root S_floating
SQRTTSquare root T_floating

Count Extensions (CIX)

Count Extensions (CIX) was an extension to the architecture which introduced three instructions for counting bits. These instructions were categorized as integer arithmetic instructions. They were first implemented on the Alpha 21264A (EV67).

CTLZCount Leading Zero
CTPOPCount Population
CTTZCount Trailing Zero


At the time of its announcement, Alpha was heralded as an architecture for the next 25 years. While this was not to be, Alpha has nevertheless had a reasonably long life. The first version, the Alpha 21064 (otherwise known as the EV4) was introduced in November 1992 running at up to 192 MHz; a slight shrink of the die (the EV4S, shrunk from 0.75 µm to 0.675 µm) ran at 200 MHz a few months later. The 64-bit processor was a superpipelined and superscalar design, like other RISC designs, but nevertheless outperformed them all and DEC touted it as the world's fastest processor. Careful attention to circuit design, a hallmark of the Hudson design team, like a huge centralized clock circuitry, allowed them to run the CPU at higher speeds, even though the microarchitecture was fairly similar to other RISC chips. In comparison, the less expensive Intel Pentium ran at 66 MHz when it was launched the following spring.

The Alpha 21164 or EV5 became available in 1995 at processor frequencies of up to 333 MHz. In July 1996 the line was speed bumped to 500 MHz, in March 1998 to 666 MHz. Also in 1998 the Alpha 21264 (EV6) was released at 450 MHz, eventually reaching (in 2001 with the 21264C/EV68CB) 1.25 GHz. In 2003, the Alpha 21364 or EV7Marvel was launched, essentially an EV68 core with four 1.6 GB/s [25] inter-processor communication links for improved multiprocessor system performance, running at 1 or 1.15 GHz.

In 1996, the production of Alpha chips was licensed to Samsung Electronics Company. Following the purchase of Digital by Compaq the majority of the Alpha products were placed with API NetWorks, Inc. (previously Alpha Processor Inc.), a private company funded by Samsung and Compaq. In October 2001, Microway became the exclusive sales and service provider of API NetWorks' Alpha-based product line.

On June 25, 2001, Compaq announced that Alpha would be phased out by 2004 in favor of Intel's Itanium, canceled the planned EV8 chip, and sold all Alpha intellectual property to Intel. [26] HP, new owner of Compaq later the same year, announced that development of the Alpha series would continue for a few more years, including the release of a 1.3 GHz EV7 variant called the EV7z. This would be the final iteration of Alpha, the 0.13 µm EV79 also being canceled.

Alpha was also implemented in the Piranha, a research prototype developed by Compaq's Corporate Research and Nonstop Hardware Development groups at the Western Research Laboratory and Systems Research Center. Piranha was a multicore design for transaction processing workloads that contained eight simple cores. It was described at the 27th Annual International Symposium on Computer Architecture in June 2000. [27]

Model history

ModelModel numberYearFrequency [MHz]Process [µm]Transistors [millions]Die size [mm2]IO PinsPower [W]VoltageDcache [KB] [28] Icache [KB]ScacheBcache ISA
EV4 21064 19921002000.751.68234290303.388128 KB16 MB 
EV4S2106419931002000.6751.68186290273.388128 KB16 MB 
EV4521064A19942003000.52.85164333.31616256 KB16 MB 
EV5 21164 19952665000.59.3299296563.3/2.58896 KBUp to 64 MBR
EV5621164A1996366666 [1] 0.359.66 [1] 2093155 [1] 3.3/2.5 [1] 8896 KBUp to 64 MBR,B
PCA5621164PC19974005330.353.514126426353.3/2.5816512 KB4 MBR,B,M
PCA5721164PC 6006660.285.710128318232.5/2.01632 [1] 512 KB4 MBR,B,M
EV6 21264 19984506000.3515.2314389732.0646428 MBR,B,M,F
EV6721264A19996007500.2515.2210389 2.0646428 MBR,B,M,F,C
EV68AL21264B20018008330.1815.2125  1.7646428 MBR,B,M,F,C,T
EV68CB21264C2001100012500.1815.2125 65751.65646428 MBR,B,M,F,C,T
EV68CX21264D       1.65646428 MBR,B,M,F,C,T
EV7 21364 2003100011500.181303971251.564641.75 MBR,B,M,F,C,T
EV7z21364200413000.181303971251.564641.75 MBR,B,M,F,C,T
EV78/EV7921364ASlated for 200417000.131523001201.264641.75 MBR,B,M,F,C,T
EV8 21464 Slated for 2003120020000.1252504201800??1.264643 MBR,B,M,F,C,T
ModelModel numberYearFrequency [MHz]Process [µm]Transistors [millions]Die size [mm²]IO PinsPower [W]VoltageDcache [KB]Icache [KB]ScacheBcache ISA
ISA extensions


To illustrate the comparative performance of Alpha-based systems, some SPEC performance numbers (SPECint95, SPECfp95) are listed below. Note that the SPEC results claim to report the measured performance of a whole computer system (CPU, bus, memory, compiler optimizer), not just the CPU. Also note that the benchmark and scale changed from 1992 to 1995. However, the figures give a rough impression of the performance of the Alpha architecture (64-bit), compared with the contemporary HP (64-bit) and Intel-based offerings (32-bit). Perhaps the most obvious trend is that while Intel could always get reasonably close to Alpha in integer performance, in floating point performance the difference was considerable. On the other side, HP (PA-RISC) is also reasonably close to Alpha, but these CPUs are running at significantly lower clock rates (MHz). The tables lack two important values: the power consumption and the price of a CPU.

Alpha-based systems

The first generation of DEC Alpha-based systems comprised the DEC 3000 AXP series workstations and low-end servers, DEC 4000 AXP series mid-range servers, and DEC 7000 AXP and 10000 AXP series high-end servers. The DEC 3000 AXP systems used the same TURBOchannel bus as the previous MIPS-based DECstation models, whereas the 4000 was based on FutureBus+ and the 7000/10000 shared an architecture with corresponding VAX models.

DEC also produced a PC-like Alpha workstation with an EISA bus, the DECpc AXP 150 (codename "Jensen", also known as the DEC 2000 AXP). This was the first Alpha system to support Windows NT. DEC later produced Alpha versions of their Celebris XL and Digital Personal Workstation PC lines, with 21164 processors.

Digital also produced single board computers based on the VMEbus for embedded and industrial use. The first generation included the 21068-based AXPvme 64 and AXPvme 64LC, and the 21066-based AXPvme 160. These were introduced on March 1, 1994. Later models such as the AXPvme 100, AXPvme 166 and AXPvme 230 were based on the 21066A processor, while the Alpha VME 4/224 and Alpha VME 4/288 were based on the 21064A processor. The last models, the Alpha VME 5/352 and Alpha VME 5/480, were based on the 21164 processor.

The 21066 chip was used in the DEC Multia VX40/41/42 compact workstation and the ALPHAbook 1 laptop from Tadpole Technology.

In 1994, DEC launched a new range of AlphaStation and AlphaServer systems. These used 21064 or 21164 processors and introduced the PCI bus, VGA-compatible frame buffers and PS/2-style keyboards and mice. The AlphaServer 8000 series superseded the DEC 7000/10000 AXP and also employed XMI and FutureBus+ buses.

The AlphaStation XP1000 was the first workstation based on the 21264 processor. Later AlphaServer/Station models based on the 21264 were categorised into DS (departmental server), ES (enterprise server) or GS (global server) families.

The final 21364 chip was used in the AlphaServer ES47, ES80 and GS1280 models and the AlphaStation ES47.

A number of OEM motherboards were produced by DEC, such as the 21066 and 21068-based AXPpci 33 "NoName", which was part of a major push into the OEM market by the company, [30] the 21164-based AlphaPC 164 and AlphaPC 164LX, the 21164PC-based AlphaPC 164SX and AlphaPC 164RX and the 21264-based AlphaPC 264DP. Several third parties such as Samsung and API also produced OEM motherboards such as the API UP1000 and UP2000.

To assist third parties in developing hardware and software for the platform, DEC produced Evaluation Boards, such as the EB64+ and EB164 for the Alpha 21064A and 21164 microprocessors respectively.

The 21164 and 21264 processors were used by NetApp in various network-attached storage systems, while the 21064 and 21164 processors were used by Cray in their T3D and T3E massively parallel supercomputers.


The fastest supercomputer based on Alpha processors was the ASCI Q at Los Alamos National Laboratory. The machine was built as an HP AlphaServer SC45/GS Cluster. It had 4096 Alpha (21264 EV-68, 1.25 GHz) CPUs, and reached an Rmax of 7.727 Teraflops. [31]

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The DEC 7000 AXP and DEC 10000 AXP are a series of high-end multiprocessor server computers developed and manufactured by Digital Equipment Corporation, introduced on 10 November 1992. These systems formed part of the first generation of systems based on the 64-bit Alpha AXP architecture and at the time of introduction, ran Digital's OpenVMS AXP operating system, with DEC OSF/1 AXP available in March 1993. They were designed in parallel with the VAX 7000 and VAX 10000 minicomputers, and are identical except for the processor module(s) and supported bus interfaces. A field upgrade from a VAX 7000/10000 to a DEC 7000/10000 AXP was possible by means of swapping the processor boards.

Alpha 21064

The Alpha 21064 is a microprocessor developed and fabricated by Digital Equipment Corporation that implemented the Alpha instruction set architecture (ISA). It was introduced as the DECchip 21064 before it was renamed in 1994. The 21064 is also known by its code name, EV4. It was announced in February 1992 with volume availability in September 1992. The 21064 was the first commercial implementation of the Alpha ISA, and the first microprocessor from Digital to be available commercially. It was succeeded by a derivative, the Alpha 21064A in October 1993.

Alpha 21164

The Alpha 21164, also known by its code name, EV5, is a microprocessor developed and fabricated by Digital Equipment Corporation that implemented the Alpha instruction set architecture (ISA). It was introduced in January 1995, succeeding the Alpha 21064A as Digital's flagship microprocessor. It was succeeded by the Alpha 21264 in 1998.

Alpha 21264

The Alpha 21264 is a Digital Equipment Corporation RISC microprocessor introduced in October, 1996. The 21264 implemented the Alpha instruction set architecture (ISA).

The Alpha 21364, code-named "Marvel", also known as EV7 is a microprocessor developed by Digital Equipment Corporation (DEC), later Compaq Computer Corporation, that implemented the Alpha instruction set architecture (ISA).

MicroVAX 78032 microprocessor

The MicroVAX 78032 is a microprocessor developed and fabricated by Digital Equipment Corporation (DEC) that implemented a subset of the VAX instruction set architecture (ISA). The 78032 was used exclusively in DEC's VAX-based systems, starting with the MicroVAX II in 1985. When clocked at a frequency of 5 MHz, the 78032's integer performance is comparable to the VAX-11/780 superminicomputer, which was introduced on 25 October 1977. The microprocessor could be paired with the MicroVAX 78132 floating point accelerator for improved floating point performance. The 78032 represented a number of firsts for DEC. It was DEC's first single-chip microprocessor implementation of the VAX ISA and DEC's first self-fabricated microprocessor. The MicroVAX 78032 is also notable as it was the first semiconductor device to be registered for protection under the Semiconductor Chip Protection Act of 1984.

The Alpha 21464 is an unfinished microprocessor that implements the Alpha instruction set architecture (ISA) developed by Digital Equipment Corporation and later by Compaq after it acquired Digital. The microprocessor was also known as EV8 or Araña, the latter being its code-name. Slated for a 2004 release, it was canceled on 25 June 2001 when Compaq announced that Alpha would be phased out in favor of Itanium by 2004. When it was canceled, the Alpha 21464 was at a late stage of development but had not been taped out.

Sunway, or ShenWei,, is a series of computer microprocessors, developed by Jiāngnán Computing Lab (江南计算技术研究所) in Wuxi, China. It uses a reduced instruction set computing (RISC) architecture, but details are still sparse.


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