XOP instruction set

The XOP (eXtended Operations ^[1] ) instruction set, announced by AMD on May 1, 2009, is an extension to the 128-bit SSE core instructions in the x86 and AMD64 instruction set for the Bulldozer processor core, which was released on October 12, 2011. ^[2] However AMD removed support for XOP from Zen (microarchitecture) onward. ^[3]

The XOP instruction set contains several different types of vector instructions since it was originally intended as a major upgrade to SSE. Most of the instructions are integer instructions, but it also contains floating point permutation and floating point fraction extraction instructions. See the index for a list of instruction types.

History

Main article: SSE5

XOP is a revised subset of what was originally intended as SSE5. It was changed to be similar but not overlapping with AVX, parts that overlapped with AVX were removed or moved to separate standards such as FMA4 (floating-point vector multiply–accumulate) and CVT16 (Half-precision floating-point conversion implemented as F16C by Intel). ^[1]

All SSE5 instructions that were equivalent or similar to instructions in the AVX and FMA4 instruction sets announced by Intel have been changed to use the coding proposed by Intel. Integer instructions without equivalents in AVX were classified as the XOP extension. ^[1] The XOP instructions have an opcode byte 8F (hexadecimal), but otherwise almost identical coding scheme as AVX with the 3-byte VEX prefix.

Commentators ^[4] have seen this as evidence that Intel has not allowed AMD to use any part of the large VEX coding space. AMD has been forced to use different codes in order to avoid using any code combination that Intel might possibly be using in its development pipeline for something else. The XOP coding scheme is as close to the VEX scheme as technically possible without risking that the AMD codes overlap with future Intel codes. This inference is speculative, since no public information is available about negotiations between the two companies on this issue.

The use of the 8F byte requires that the m-bits (see VEX coding scheme) have a value larger than or equal to 8 in order to avoid overlap with existing instructions. ^{[Note 1]} The C4 byte used in the VEX scheme has no such restriction. This may prevent the use of the m-bits for other purposes in the future in the XOP scheme, but not in the VEX scheme. Another possible problem is that the pp bits have the value 00 in the XOP scheme, while they have the value 01 in the VEX scheme for instructions that have no legacy equivalent. This may complicate the use of the pp bits for other purposes in the future.

A similar compatibility issue is the difference between the FMA3 and FMA4 instruction sets. Intel initially proposed FMA4 in AVX/FMA specification version 3 to supersede the 3-operand FMA proposed by AMD in SSE5. After AMD adopted FMA4, Intel canceled FMA4 support and reverted to FMA3 in the AVX/FMA specification version 5 (See FMA history). ^{[1] [5] [6]}

In March 2015, AMD explicitly revealed in the description of the patch for the GNU Binutils package that Zen, its third-generation x86-64 architecture in its first iteration (znver1 – Zen, version 1), will not support TBM, FMA4, XOP and LWP instructions developed specifically for the "Bulldozer" family of micro-architectures. ^{[7] [8]}

Integer vector multiply–accumulate instructions

These are integer version of the FMA instruction set. These are all four operand instructions similar to FMA4 and they all operate on signed integers.

Instruction	Description [9]	Operation
VPMACSWW VPMACSSWW	Multiply Accumulate (with Saturation) Word to Word	2x8 words (a0-a7, b0-b7) + 8 words (c0-c7) → 8 words (r0-r7) r0 = a0 * b0 + c0, r1 = a1 * b1 + c1, ..
VPMACSWD VPMACSSWD	Multiply Accumulate (with Saturation) Low Word to Doubleword	2x8 words (a0-a7, b0-b7) + 4 doublewords (c0-c3) → 4 doublewords (r0-r3) r0 = a0 * b0 + c0, r1 = a2 * b2 + c1, . [2]
VPMACSDD VPMACSSDD	Multiply Accumulate (with Saturation) Doubleword to Doubleword	2x4 doublewords (a0-a3, b0-b3) + 4 doublewords (c0-c3) → 4 doublewords (r0-r3) r0 = a0 * b0 + c0, r1 = a1 * b1 + c1, ..
VPMACSDQL VPMACSSDQL	Multiply Accumulate (with Saturation) Low Doubleword to Quadword	2x4 doublewords (a0-a3, b0-b3) + 2 quadwords (c0-c1) → 2 quadwords (r0-r3) r0 = a0 * b0 + c0, r1 = a2 * b2 + c1
VPMACSDQH VPMACSSDQH	Multiply Accumulate (with Saturation) High Doubleword to Quadword	2x4 doublewords (a0-a3, b0-b3) + 2 quadwords (c0-c1) → 2 quadwords (r0-r3) r0 = a1 * b1 + c0, r1 = a3 * b3 + c1
VPMADCSWD VPMADCSSWD	Multiply Add Accumulate (with Saturation) Word to Doubleword	2x8 words (a0-a7, b0-b7) + 4 doublewords (c0-c3) → 4 doublewords (r0-r3) r0 = a0 * b0 + a1 * b1 + c0, r1 = a2 * b2 + a3 * b3 + c1, ..

Integer vector horizontal addition

Horizontal addition instructions adds adjacent values in the input vector to each other. The output size in the instructions below describes how wide the horizontal addition performed is. For instance horizontal byte to word adds two bytes at a time and returns the result as vector of words, but byte to quadword adds eight bytes together at a time and returns the result as vector of quadwords. Six additional horizontal addition and subtraction instructions can be found in SSSE3, but they operate on two input vectors and only does two and two operations.

Instruction	Description [9]	Operation
VPHADDBW VPHADDUBW	Horizontal add two signed/unsigned bytes to word	16 bytes (a0-a15) → 8 words (r0-r7) r0 = a0+a1, r1 = a2+a3, r2 = a4+a5, ...
VPHADDBD VPHADDUBD	Horizontal add four signed/unsigned bytes to doubleword	16 bytes (a0-a15) → 4 doublewords (r0-r3) r0 = a0+a1+a2+a3, r1 = a4+a5+a6+a7, ...
VPHADDBQ VPHADDUBQ	Horizontal add eight signed/unsigned bytes to quadword	16 bytes (a0-a15) → 2 quadwords (r0-r1) r0 = a0+a1+a2+a3+a4+a5+a6+a7, ...
VPHADDWD VPHADDUWD	Horizontal add two signed/unsigned words to doubleword	8 words (a0-a7) → 4 doublewords (r0-r3) r0 = a0+a1, r1 = a2+a3, r2 = a4+a5, ...
VPHADDWQ VPHADDUWQ	Horizontal add four signed/unsigned words to quadword	8 words (a0-a7) → 2 quadwords (r0-r1) r0 = a0+a1+a2+a3, r1 = a4+a5+a6+a7
VPHADDDQ VPHADDUDQ	Horizontal add two signed/unsigned doublewords to quadword	4 doublewords (a0-a3) → 2 quadwords (r0-r1) r0 = a0+a1, r1 = a2+a3
VPHSUBBW	Horizontal subtract two signed bytes to word	16 bytes (a0-a15) → 8 words (r0-r7) r0 = a0-a1, r1 = a2-a3, r2 = a4-a5, ...
VPHSUBWD	Horizontal subtract two signed words to doubleword	8 words (a0-a7) → 4 doublewords (r0-r3) r0 = a0-a1, r1 = a2-a3, r2 = a4-a5, ...
VPHSUBDQ	Horizontal subtract two signed doublewords to quadword	4 doublewords (a0-a3) → 2 quadwords (r0-r1) r0 = a0-a1, r1 = a2-a3

Integer vector compare

This set of vector compare instructions all take an immediate as an extra argument. The immediate controls what kind of comparison is performed. There are eight comparison possible for each instruction. The vectors are compared and all comparisons that evaluate to true set all corresponding bits in the destination to 1, and false comparisons sets all the same bits to 0. This result can be used directly in VPCMOV instruction for a vectorized conditional move.

Instruction	Description [9]		Immediate	Comparison
VPCOMB	Compare Vector Signed Bytes		000	Less Than
VPCOMW	Compare Vector Signed Words		001	Less Than or Equal
VPCOMD	Compare Vector Signed Doublewords		010	Greater Than
VPCOMQ	Compare Vector Signed Quadwords		011	Greater Than or Equal
VPCOMUB	Compare Vector Unsigned Bytes		100	Equal
VPCOMUW	Compare Vector Unsigned Words		101	Not Equal
VPCOMUD	Compare Vector Unsigned Doublewords		110	False
VPCOMUQ	Compare Vector Unsigned Quadwords		111	True

Vector conditional move

VPCMOV works as bitwise variant of the blend instructions in SSE4. For each bit in the selector 1 selects the same bit in the first source, and 0 selects the same in the second source. When used together with the XOP vector comparison instructions above this can be used to implement a vectorized ternary move, or if the second input is the same as the destination, a conditional move (CMOV).

Instruction	Description [9]
VPCMOV	Vector Conditional Move

Integer vector shift and rotate instructions

The shift instructions here differ from those in SSE2 in that they can shift each unit with a different amount using a vector register interpreted as packed signed integers. The sign indicates the direction of shift or rotate, with positive values causing left shift and negative right shift ^[10] Intel has specified a different incompatible set of variable vector shift instructions in AVX2. ^[11]

Instruction	Description [9]
VPROTB	Packed Rotate Bytes
VPROTW	Packed Rotate Words
VPROTD	Packed Rotate Doublewords
VPROTQ	Packed Rotate Quadwords
VPSHAB	Packed Shift Arithmetic Bytes
VPSHAW	Packed Shift Arithmetic Words
VPSHAD	Packed Shift Arithmetic Doublewords
VPSHAQ	Packed Shift Arithmetic Quadwords
VPSHLB	Packed Shift Logical Bytes
VPSHLW	Packed Shift Logical Words
VPSHLD	Packed Shift Logical Doublewords
VPSHLQ	Packed Shift Logical Quadwords

Vector permute

VPPERM is a single instruction that combines the SSSE3 instruction PALIGNR and PSHUFB and adds more to both. Some compare it the Altivec instruction VPERM. ^[12] It takes three registers as input, the first two are source registers and the third the selector register. Each byte in the selector selects one of the bytes in one of the two input registers for the output. The selector can also apply effects on the selected bytes such as setting it to 0, reverse the bit order, and repeating most signicating bit. All of the effects or the input can in addition be inverted.

The VPERMIL2PD and VPERMIL2PS instructions are two source versions of the VPERMILPD and VPERMILPS instructions in AVX which means like VPPERM they can select output from any of the fields in the two inputs.

Instruction	Description [9]
VPPERM	Packed Permute Byte
VPERMIL2PD	Permute Two-Source Double-Precision Floating-Point
VPERMIL2PS	Permute Two-Source Single-Precision Floating-Point

Floating-point fraction extraction

These instructions extracts the fractional part of floating point, that is the part that would be lost in conversion to integer.

Instruction	Description [9]
VFRCZPD	Extract Fraction Packed Double-Precision Floating-Point
VFRCZPS	Extract Fraction Packed Single-Precision Floating-Point
VFRCZSD	Extract Fraction Scalar Double-Precision Floating-Point
VFRCZSS	Extract Fraction Scalar Single-Precision Floating Point

CPUs with XOP

• AMD:
  • "Heavy Equipment" processors
    • Bulldozer-based processors, Q4 2011 ^[13]
    • Piledriver-based processors, Q4 2012 ^[14]
    • Steamroller-based processors, Q1 2014
    • Excavator-based processors (including "v2"), 2015

See also

• AVX
• CVT16
• FMA4
• SSE5
• x86

Notes

1. Byte value 0x8F is an exising opcode for a POP instruction. This instruction uses the ModR/M byte, which follows the opcode, but it does not make use of the "reg" (register) field, which is bits 3-5. Some opcodes which don't use "reg" multiplex instructions by using these bits to signify eight different instructions (0x80-0x83 and 0xD0-0xDF, among others); 0x8F does not. This means, for a standard POP instruction, bits 3-5 should always be zero. Since the m-bits are bits 0-4, requiring a value 8 or higher sets bit 3 of the byte following 0x8F.

References

1. Dave Christie (2009-05-07), Striking a balance, AMD Developer blogs, archived from the original on 2013-11-04, retrieved 2013-11-04
2. AMD64 Architecture Programmer's Manual Volume 6: 128-Bit and 256-Bit XOP, FMA4 and CVT16 Instructions (PDF), AMD, May 1, 2009
3. Michael Larabel (March 3, 2017). "The Impact Of GCC Zen Compiler Tuning On AMD Ryzen Performance". Phoronix . But with Zen being a clean-sheet design, there are some instruction set extensions found in Bulldozer processors not found in Zen/znver1. Those no longer present include FMA4 and XOP.
4. Agner Fog (December 5, 2009), Stop the instruction set war
5. Intel AVX Programming Reference (PDF), March 2008, retrieved 2012-01-17
6. Intel Advanced Vector Extensions Programming Reference, January 2009, archived from the original on February 29, 2012, retrieved 2012-01-17
7. Ganesh Gopalasubramanian (March 10, 2015). "[PATCH] add znver1 processor". [e-mail] (Mailing list).
8. Amit Pawar (August 7, 2015). "[PATCH] Remove CpuFMA4 From Znver1 CPU Flags". [e-mail] (Mailing list).
9. "AMD64 Architecture Programmer's Manual, Volume4: 128-Bit and 256-Bit Media Instructions" (PDF). AMD . Retrieved 2014-01-13.
10. "New "Bulldozer" and "Piledriver" Instructions" (PDF). AMD . Retrieved 2014-01-13.
11. "Intel Architecture Instruction Set Extensions Programming Reference". Intel. Archived from the original (PDF) on February 1, 2014. Retrieved 2014-01-29.
12. "Buldozer x264 optimisations" . Retrieved 2014-01-13.
13. Dave Christie (2009-05-07), Striking a balance, AMD Developer blogs, archived from the original on 2013-11-09, retrieved 2012-01-17
14. New "Bulldozer" and "Piledriver" Instructions (PDF), AMD, October 2012