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Introduced | 2011 |
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Version | ARMv8-A , ARMv8-R , ARMv9-A |
Encoding | AArch64/A64 and AArch32/A32 use 32-bit instructions, AArch32/T32 (Thumb-2) uses mixed 16- and 32-bit instructions [1] |
Endianness | Bi for data only (little as default, instructions are little) |
Extensions | |
Registers | |
General-purpose | 31 × 64-bit integer registers [1] |
Floating-point | 32 × 128-bit registers [1] for scalar 32- and 64-bit FP or SIMD FP or integer; or cryptography |
AArch64, also known as ARM64, is a 64-bit version of the ARM architecture family, a widely used set of computer processor designs. It was introduced in 2011 with the ARMv8 architecture and later became part of the ARMv9 series. AArch64 allows processors to handle more memory and perform faster calculations than earlier 32-bit versions. It is designed to work alongside the older 32-bit mode, known as AArch32, allowing compatibility with a wide range of software. Devices that use AArch64 include smartphones, tablets, personal computers, and servers. The AArch64 architecture has continued to evolve through updates that improve performance, security, and support for advanced computing tasks. [2]
In ARMv8-A, ARMv8-R, and ARMv9-A, an "Execution state" defines key characteristics of the processor’s environment. This includes the number of bits used in the primary processor registers, the supported instruction sets, and other aspects of the processor's execution environment. These versions of the ARM architecture support two Execution states: the 64-bit AArch64 state and the 32-bit AArch32 state. [3]
Extension: Data gathering hint (ARMv8.0-DGH).
AArch64 was introduced in ARMv8-A and is included in subsequent versions of ARMv8-A, and in all versions of ARMv9-A. It was also introduced in ARMv8-R as an option, after its introduction in ARMv8-A; it is not included in ARMv8-M.
The main opcode for selecting which group an A64 instruction belongs to is at bits 25–28.
Type | Bit | |||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
Reserved | 0 | op0 | 0 | 0 | 0 | 0 | op1 | |||||||||||||||||||||||||
SME | 1 | op0 | 0 | 0 | 0 | 0 | Varies | |||||||||||||||||||||||||
Unallocated | 0 | 0 | 0 | 1 | ||||||||||||||||||||||||||||
SVE | 0 | 0 | 1 | 0 | Varies | |||||||||||||||||||||||||||
Unallocated | 0 | 0 | 1 | 1 | ||||||||||||||||||||||||||||
Data Processing — Immediate PC-rel. | op | immlo | 1 | 0 | 0 | 0 | 0 | immhi | Rd | |||||||||||||||||||||||
Data Processing — Immediate Others | sf | 1 | 0 | 0 | 01–11 | Rd | ||||||||||||||||||||||||||
Branches + System Instructions | op0 | 1 | 0 | 1 | op1 | op2 | ||||||||||||||||||||||||||
Load and Store Instructions | op0 | 1 | op1 | 0 | op2 | op3 | op4 | |||||||||||||||||||||||||
Data Processing — Register | sf | op0 | op1 | 1 | 0 | 1 | op2 | op3 | ||||||||||||||||||||||||
Data Processing — Floating Point and SIMD | op0 | 1 | 1 | 1 | op1 | op2 | op3 |
Announced in October 2011, [5] ARMv8-A represents a fundamental change to the ARM architecture. It adds an optional 64-bit Execution state, named "AArch64", and the associated new "A64" instruction set, in addition to a 32-bit Execution state, "AArch32", supporting the 32-bit "A32" (original 32-bit ARM) and "T32" (Thumb/Thumb-2) instruction sets. The latter instruction sets provide user-space compatibility with the existing 32-bit ARMv7-A architecture. ARMv8-A allows 32-bit applications to be executed in a 64-bit OS, and a 32-bit OS to be under the control of a 64-bit hypervisor. [1] ARM announced their Cortex-A53 and Cortex-A57 cores on 30 October 2012. [6] Apple was the first to release an ARMv8-A compatible core (Cyclone) in a consumer product (iPhone 5S). AppliedMicro, using an FPGA, was the first to demo ARMv8-A. [7] The first ARMv8-A SoC from Samsung is the Exynos 5433 used in the Galaxy Note 4, which features two clusters of four Cortex-A57 and Cortex-A53 cores in a big.LITTLE configuration; but it only runs in AArch32 mode. [8] ARMv8-A includes VFPv3/v4 and advanced SIMD (Neon) as standard features in both AArch32 and AArch64. It also adds cryptography instructions supporting AES, SHA-1/SHA-256 and finite field arithmetic. [9]
An ARMv8-A processor can support one or both of AArch32 and AArch64; it may support AArch32 and AArch64 at lower Exception levels and only AArch64 at higher Exception levels. [10] For example, the ARM Cortex-A32 supports only AArch32, [11] the ARM Cortex-A34 supports only AArch64, [12] and the ARM Cortex-A72 supports both AArch64 and AArch32. [13] An ARMv9-A processor must support AArch64 at all Exception levels, and may support AArch32 at EL0. [10]
In December 2014, ARMv8.1-A, [14] an update with "incremental benefits over v8.0", was announced. The enhancements fell into two categories: changes to the instruction set, and changes to the exception model and memory translation.
Instruction set enhancements included the following:
Enhancements for the exception model and memory translation system included the following:
ARMv8.2-A was announced in January 2016. [17] Its enhancements fall into four categories:
The Scalable Vector Extension (SVE) is licensed as "an optional extension to the ARMv8.2-A architecture and newer" developed specifically for vectorization of high-performance computing scientific workloads. [18] [19] The specification allows for ARM licensees to choose a hard-coded architectural register width between 128 and 2048 bits in multiples of 128. The extension is complementary to and does not replace the NEON extensions.
A 512-bit SVE variant has already been implemented on the Fugaku supercomputer using the Fujitsu A64FX ARM processor; this computer [20] was the fastest supercomputer in the world for two years, from June 2020 [21] to May 2022. [22] A more flexible version, 2x256 SVE, was implemented by the AWS Graviton3 ARM processor.
SVE is supported by GCC, with GCC 8 supporting automatic vectorization [19] and GCC 10 supporting C intrinsics. As of July 2020 [update] , LLVM and clang support C and IR intrinsics. ARM's own fork of LLVM supports auto-vectorization. [23]
In October 2016, ARMv8.3-A was announced. Its enhancements fell into six categories: [24]
ARMv8.3-A architecture is now supported by (at least) GCC 7.0. [29]
In November 2017, ARMv8.4-A was announced. Its enhancements fell into these categories: [30] [31] [32]
In September 2018, ARMv8.5-A was announced. Its enhancements fell into these categories: [34] [35] [36]
On 2 August 2019, Google announced Android will adopt Memory Tagging Extension (MTE). [38]
In March 2021, ARMv9-A was announced. ARMv9-A's baseline is all features from ARMv8.5. [39] [40] [41] ARMv9-A also adds:
In September 2019, ARMv8.6-A was announced. Its enhancements fell into these categories: [34] [47]
For example, fine-grained traps, Wait-for-Event (WFE) instructions, EnhancedPAC2 and FPAC. The bfloat16 extensions for SVE and Neon are mainly for deep learning use. [49]
In September 2020, ARMv8.7-A was announced. Its enhancements fell into these categories: [34] [50]
In September 2021, ARMv8.8-A and ARMv9.3-A were announced. Their enhancements fell into these categories: [34] [52]
In September 2022, ARMv8.9-A and ARMv9.4-A were announced, including: [54]
In October 2023, ARMv9.5-A was announced, including: [55]
In October 2024, ARMv9.6-A was announced, including: [56]
This section needs expansionwith: examples and additional citations. You can help by adding to it.(May 2021) |
The ARM-R architecture, specifically the Armv8-R profile, is designed to address the needs of real-time applications, where predictable and deterministic behavior is essential. This profile focuses on delivering high performance, reliability, and efficiency in embedded systems where real-time constraints are critical.
With the introduction of optional AArch64 support in the Armv8-R profile, the real-time capabilities have been further enhanced. The Cortex-R82 [57] is the first processor to implement this extended support, bringing several new features and improvements to the real-time domain. [58]
This article may incorporate text from a large language model .(September 2025) |
ADD X0, X1, X2
adds the values in 64-bit registers X1 and X2 and stores the result in X0. This 64-bit operation allows for larger and more complex calculations compared to the 32-bit operations of the previous A32 instruction set.pointer authentication extension is defined to be mandatory extension on ARMv8.3-A and is not optional
The ARMv8.3-A architecture is now supported. It can be used by specifying the -march=armv8.3-a option. [..] The option -msign-return-address= is supported to enable return address protection using ARMv8.3-A Pointer Authentication Extensions.