Half-precision floating-point format

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In computing, half precision (sometimes called FP16) is a binary floating-point computer number format that occupies 16 bits (two bytes in modern computers) in computer memory. It is intended for storage of floating-point values in applications where higher precision is not essential, in particular image processing and neural networks.


Almost all modern uses follow the IEEE 754-2008 standard, where the 16-bit base-2 format is referred to as binary16, and the exponent uses 5 bits. This can express values in the range ±65,504, with the minimum value above 1 being 1 + 1/1024.

Depending on the computer, half-precision can be over an order of magnitude faster than double precision, e.g. 550 PFLOPS for half-precision vs 37 PFLOPS for double precision on one cloud provider. [1]


Several earlier 16-bit floating point formats have existed including that of Hitachi's HD61810 DSP [2] of 1982, Scott's WIF [3] and the 3dfx Voodoo Graphics processor. [4]

ILM was searching for an image format that could handle a wide dynamic range, but without the hard drive and memory cost of single or double precision floating point. [5] The hardware-accelerated programmable shading group led by John Airey at SGI (Silicon Graphics) invented the s10e5 data type in 1997 as part of the 'bali' design effort. This is described in a SIGGRAPH 2000 paper [6] (see section 4.3) and further documented in US patent 7518615. [7] It was popularized by its use in the open-source OpenEXR image format.

Nvidia and Microsoft defined the half datatype in the Cg language, released in early 2002, and implemented it in silicon in the GeForce FX, released in late 2002. [8] Since then support for 16-bit floating point math in graphics cards has become very common.[ citation needed ]

The F16C extension in 2012 allows x86 processors to convert half-precision floats to and from single-precision floats with a machine instruction.

IEEE 754 half-precision binary floating-point format: binary16

The IEEE 754 standard [9] specifies a binary16 as having the following format:

The format is laid out as follows:

IEEE 754r Half Floating Point Format.svg

The format is assumed to have an implicit lead bit with value 1 unless the exponent field is stored with all zeros. Thus only 10 bits of the significand appear in the memory format but the total precision is 11 bits. In IEEE 754 parlance, there are 10 bits of significand, but there are 11 bits of significand precision (log10(211) ≈ 3.311 decimal digits, or 4 digits ± slightly less than 5 units in the last place).

Exponent encoding

The half-precision binary floating-point exponent is encoded using an offset-binary representation, with the zero offset being 15; also known as exponent bias in the IEEE 754 standard.

Thus, as defined by the offset binary representation, in order to get the true exponent the offset of 15 has to be subtracted from the stored exponent.

The stored exponents 000002 and 111112 are interpreted specially.

ExponentSignificand = zeroSignificand ≠ zeroEquation
000002 zero, −0 subnormal numbers (−1)signbit × 2−14 × 0.significantbits2
000012, ..., 111102normalized value(−1)signbit × 2exponent−15 × 1.significantbits2
111112±infinity NaN (quiet, signalling)

The minimum strictly positive (subnormal) value is 2−24 ≈ 5.96 × 10−8. The minimum positive normal value is 2−14 ≈ 6.10 × 10−5. The maximum representable value is (2−2−10) × 215 = 65504.

Half precision examples

These examples are given in bit representation of the floating-point value. This includes the sign bit, (biased) exponent, and significand.

0 00000 000000000000000
0 00000 000000000100012−14 × (0 + 1/1024 ) ≈ 0.000000059604645smallest positive subnormal number
0 00000 111111111103ff2−14 × (0 + 1023/1024 ) ≈ 0.000060975552largest subnormal number
0 00001 000000000004002−14 × (1 + 0/1024 ) ≈ 0.00006103515625smallest positive normal number
0 01101 010101010135552−2 × (1 + 341/1024 ) ≈ 0.33325195nearest value to 1/3
0 01110 11111111113bff2−1 × (1 + 1023/1024 ) ≈ 0.99951172largest number less than one
0 01111 00000000003c0020 × (1 + 0/1024 ) = 1one
0 01111 00000000013c0120 × (1 + 1/1024 ) ≈ 1.00097656smallest number larger than one
0 11110 11111111117bff215 × (1 + 1023/1024 ) = 65504largest normal number
0 11111 00000000007c00infinity
1 00000 00000000008000−0
1 10000 0000000000c000-2
1 11111 0000000000fc00−∞negative infinity

By default, 1/3 rounds down like for double precision, because of the odd number of bits in the significand. The bits beyond the rounding point are 0101... which is less than 1/2 of a unit in the last place.

Precision limitations


65519 is the largest number that will round to a finite number (65504), 65520 and larger will round to infinity. This is for round-to-even, other rounding strategies will change this cutoff.

ARM alternative half-precision

ARM processors support (via a floating point control register bit) an "alternative half-precision" format, which does away with the special case for an exponent value of 31 (111112). [10] It is almost identical to the IEEE format, but there is no encoding for infinity or NaNs; instead, an exponent of 31 encodes normalized numbers in the range 65536 to 131008.

Uses of half precision

This format is used in several computer graphics environments to store pixels, including MATLAB, OpenEXR, JPEG XR, GIMP, OpenGL, Cg, Direct3D, and D3DX. The advantage over 8-bit or 16-bit integers is that the increased dynamic range allows for more detail to be preserved in highlights and shadows for images, and the linear representation of intensity making calculations easier. The advantage over 32-bit single-precision floating point is that it requires half the storage and bandwidth (at the expense of precision and range). [5]

Hardware and software for machine learning or neural networks tend to use half precision: such applications usually do a large amount of calculation, but don't require a high level of precision.

If the hardware has instructions to compute half-precision math, it is often faster than single or double precision. If the systems has SIMD instructions that can handle multiple floating-point numbers within one instruction, half precision can be twice as fast by operating on twice as many numbers simultaneously. [11] However, if there is no hardware support, math must be done by emulation, or by conversion to single or double precision and then back, and is therefore slower.

Hardware support

Several versions of the ARM architecture have support for half precision. [12]

Support for half precision in the x86 instruction set is specified in the AVX-512_FP16 instruction set extension to be implemented in the future Intel Sapphire Rapids processor. [13]

See also

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Further reading