The chip contains 8 processor cores with a deep superscalarout-of-orderpipeline, running with more than 5 GHz clock frequency which is optimized for the demands of heterogenous enterprise-class workloads (e.g: finance, security sensitive applications, applications requiring extreme reliability). The cache and chip-interconnection infrastructure provides 32 MB cache per core and can scale to 32 Telum chips.[6][3][7] The cache design has been described as "revolutionary" in 2021, [6] by creating a system where the L2 cache of one core can be used as virtual L3 and L4 caches for another core.[3][1] The Telum processor can either be water cooled or air cooled, but water cooling is required for running more than a few Telum processors in a single IBM compute drawer.[8][9] Unlike other processors, the IBM Telum does not thermal throttle by reducing clock speed; instead it inserts sleep state instructions.[8][9]
Telum adds a new, NNP-Data-Type-1 Format, 16-bit floating point format and several new instructions. The Neural Network Processing Assists (NNPA)[10] instruction performs a variety of tensor instructions useful for neural networks.
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