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In computer architecture, a processor register is a quickly accessible location available to a computer's central processing unit (CPU). Registers usually consist of a small amount of fast storage, although some registers have specific hardware functions, and may be read-only or write-only. Registers are typically addressed by mechanisms other than main memory, but may in some cases be assigned a memory address e.g. DEC PDP-10, ICT 1900.
In computer engineering, computer architecture is a set of rules and methods that describe the functionality, organization, and implementation of computer systems. Some definitions of architecture define it as describing the capabilities and programming model of a computer but not a particular implementation. In other definitions computer architecture involves instruction set architecture design, microarchitecture design, logic design, and implementation.
A central processing unit (CPU), also called a central processor or main processor, is the electronic circuitry within a computer that carries out the instructions of a computer program by performing the basic arithmetic, logic, controlling, and input/output (I/O) operations specified by the instructions. The computer industry has used the term "central processing unit" at least since the early 1960s. Traditionally, the term "CPU" refers to a processor, more specifically to its processing unit and control unit (CU), distinguishing these core elements of a computer from external components such as main memory and I/O circuitry.
In computing, a memory address is a reference to a specific memory location used at various levels by software and hardware. Memory addresses are fixed-length sequences of digits conventionally displayed and manipulated as unsigned integers. Such numerical semantic bases itself upon features of CPU, as well upon use of the memory like an array endorsed by various programming languages.
Almost all computers, whether load/store architecture or not, load data from a larger memory into registers where it is used for arithmetic operations and is manipulated or tested by machine instructions. Manipulated data is then often stored back to main memory, either by the same instruction or by a subsequent one. Modern processors use either static or dynamic RAM as main memory, with the latter usually accessed via one or more cache levels.
Static random-access memory is a type of semiconductor memory that uses bistable latching circuitry (flip-flop) to store each bit. SRAM exhibits data remanence, but it is still volatile in the conventional sense that data is eventually lost when the memory is not powered.
Dynamic random-access memory (DRAM) is a type of random access semiconductor memory that stores each bit of data in a separate tiny capacitor within an integrated circuit. The capacitor can either be charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1. The electric charge on the capacitors slowly leaks off, so without intervention the data on the chip would soon be lost. To prevent this, DRAM requires an external memory refresh circuit which periodically rewrites the data in the capacitors, restoring them to their original charge. This refresh process is the defining characteristic of dynamic random-access memory, in contrast to static random-access memory (SRAM) which does not require data to be refreshed. Unlike flash memory, DRAM is volatile memory, since it loses its data quickly when power is removed. However, DRAM does exhibit limited data remanence.
Random-access memory is a form of computer data storage that stores data and machine code currently being used. A random-access memory device allows data items to be read or written in almost the same amount of time irrespective of the physical location of data inside the memory. In contrast, with other direct-access data storage media such as hard disks, CD-RWs, DVD-RWs and the older magnetic tapes and drum memory, the time required to read and write data items varies significantly depending on their physical locations on the recording medium, due to mechanical limitations such as media rotation speeds and arm movement.
Processor registers are normally at the top of the memory hierarchy, and provide the fastest way to access data. The term normally refers only to the group of registers that are directly encoded as part of an instruction, as defined by the instruction set. However, modern high-performance CPUs often have duplicates of these "architectural registers" in order to improve performance via register renaming, allowing parallel and speculative execution. Modern x86 design acquired these techniques around 1995 with the releases of Pentium Pro, Cyrix 6x86, Nx586, and AMD K5.
In computer architecture, the memory hierarchy separates computer storage into a hierarchy based on response time. Since response time, complexity, and capacity are related, the levels may also be distinguished by their performance and controlling technologies. Memory hierarchy affects performance in computer architectural design, algorithm predictions, and lower level programming constructs involving locality of reference.
In computer architecture, register renaming is a technique that abstracts logical registers from physical registers. Every logical register has a set of physical registers associated with it. While a programmer in assembly language refers for instance to a logical register
accu, the processor transposes this name to one specific physical register on the fly. The physical registers are opaque and can not be referenced directly but only via the canonical names.
Speculative execution is an optimization technique where a computer system performs some task that may not be needed. Work is done before it is known whether it is actually needed, so as to prevent a delay that would have to be incurred by doing the work after it is known that it is needed. If it turns out the work was not needed after all, most changes made by the work are reverted and the results are ignored.
A common property of computer programs is locality of reference, which refers to accessing the same values repeatedly and holding frequently used values in registers to improve performance; this makes fast registers and caches meaningful.Allocating frequently used variables to registers can be critical to a program's performance; this register allocation is performed either by a compiler in the code generation phase, or manually by an assembly language programmer.
A computer program is a collection of instructions that performs a specific task when executed by a computer. A computer requires programs to function.
In computer science, locality of reference, also known as the principle of locality, is the tendency of a processor to access the same set of memory locations repetitively over a short period of time. There are two basic types of reference locality – temporal and spatial locality. Temporal locality refers to the reuse of specific data, and/or resources, within a relatively small time duration. Spatial locality refers to the use of data elements within relatively close storage locations. Sequential locality, a special case of spatial locality, occurs when data elements are arranged and accessed linearly, such as, traversing the elements in a one-dimensional array.
In compiler optimization, register allocation is the process of assigning a large number of target program variables onto a small number of CPU registers.
Registers are normally measured by the number of bits they can hold, for example, an "8-bit register", "32-bit register" or a "64-bit register" or even more. In some instruction sets, the registers can operate in various modes breaking down its storage memory into smaller ones (32-bit into four 8-bit one for instance) to which multiple data (vector, or one dimensional array of data) can be loaded and operated upon at the same time. Typically it is implemented by adding extra registers that map their memory into bigger one. Processors that have the ability to execute single instruction on multiple data are called vector processors.
In computer architecture, 8-bit integers, memory addresses, or other data units are those that are 8 bits wide. Also, 8-bit CPU and ALU architectures are those that are based on registers, address buses, or data buses of that size. 8-bit is also a generation of microcomputers in which 8-bit microprocessors were the norm.
In computer architecture, 32-bit integers, memory addresses, or other data units are those that are 32 bits wide. Also, 32-bit CPU and ALU architectures are those that are based on registers, address buses, or data buses of that size. 32-bit microcomputers are computers in which 32-bit microprocessors are the norm.
In computer architecture, 64-bit computing is the use of processors that have datapath widths, integer size, and memory address widths of 64 bits. Also, 64-bit computer architectures for central processing units (CPUs) and arithmetic logic units (ALUs) are those that are based on processor registers, address buses, or data buses of that size. From the software perspective, 64-bit computing means the use of code with 64-bit virtual memory addresses. However, not all 64-bit instruction sets support full 64-bit virtual memory addresses; x86-64 and ARMv8, for example, support only 48 bits of virtual address, with the remaining 16 bits of the virtual address required to be all 0's or all 1's, and several 64-bit instruction sets support fewer than 64 bits of physical memory address.
A processor often contains several kinds of registers, which can be classified according to their content or instructions that operate on them:
Data is any sequence of one or more symbols given meaning by specific act(s) of interpretation.
In computer science, an integer is a datum of integral data type, a data type that represents some range of mathematical integers. Integral data types may be of different sizes and may or may not be allowed to contain negative values. Integers are commonly represented in a computer as a group of binary digits (bits). The size of the grouping varies so the set of integer sizes available varies between different types of computers. Computer hardware, including virtual machines, nearly always provide a way to represent a processor register or memory address as an integer.
In computer and machine-based telecommunications terminology, a character is a unit of information that roughly corresponds to a grapheme, grapheme-like unit, or symbol, such as in an alphabet or syllabary in the written form of a natural language.
Hardware registers are similar, but occur outside CPUs.
In some architectures (such as SPARC and MIPS), the first or last register in the integer register file is a pseudo-register in a way that it is hardwired to always return zero when read (mostly to simplify indexing modes), and it cannot be overwritten. In Alpha this is also done for the floating-point register file. As a result of this, register files are commonly quoted as having one register more than how many of them are actually usable; for example, 32 registers are quoted when only 31 of them fit within the above definition of a register.
The following table shows the number of registers in several mainstream CPU architectures. Note that in x86-compatible processors the stack pointer (ESP) is counted as an integer register, even though there are a limited number of instructions that may be used to operate on its contents. Similar caveats apply to most architectures.
Although all of the above listed architectures are different, almost all are a basic arrangement known as the Von Neumann architecture, first proposed by the Hungarian-American mathematician John von Neumann. It is also noteworthy that the number of registers on GPUs is much higher than that on CPUs.
|AT&T Hobbit||0||stack of 7||The AT&T Hobbit ATT92010 (around 1992) was a commercial version of the 32-bit CRISP (stack machine) processor with RISC style instruction, inspired by the Bell Labs C Machine project, aimed at a design optimized for the C language, Hobbit has no global registers. Addresses can be memory direct or indirect (for pointers) relative to the stack pointer without extra instructions or operand bits. The cache is not optimized for multiprocessors and FPU is consist with custom ASIC design in IEEE standard.|
|Cray-1||8 scalar data, 8 address||8 scalar, 8 vector (64 elements)||Scalar data registers can be integer or floating-point; also 64 scalar scratch-pad T registers and 64 address scratch-pad B registers|
|4004||1 accumulator, 16 others||0||Register A is for general purpose, while r0–r15 registers are for the address and segment.|
|8008||1 accumulator, 6 others||0||The A register is an accumulator to which all arithmetic is done; the H and L registers can be used in combination as an address register; all registers can be used as operands in load/store/move/increment/decrement instructions and as the other operand in arithmetic instructions. There is no FP unit available.|
|8080||1 accumulator, 6 others||0||Plus a stack pointer. The A register is an accumulator to which all arithmetic is done; the register pairs B+C, D+E, and H+L, can be used as address registers in some instructions; all registers can be used as operands in load/store/move/increment/decrement instructions and as the other operand in arithmetic instructions. Some instructions only use H+L; another instruction swaps H+L and D+E. Floating point processors intended for the 8080 were Intel 8231, AMD Am9511 and Intel 8232. They were also readily usable with the Z80 and similar processors.|
|iAPX432||0||stack of 6||The iAPX 432 was referred to as a micromainframe, designed to be programmed entirely in high-level languages. The instruction set architecture was also entirely new and a significant departure from Intel's previous 8008 and 8080 processors as the iAPX 432 programming model was a stack machine with no visible general-purpose registers. It supported object-oriented programming, garbage collection and multitasking as well as more conventional memory management directly in hardware and microcode. Direct support for various data structures was also intended to allow modern operating systems to be implemented using far less program code than for ordinary processors|
|16-bit x86||8||stack of 8 (if FP present)||8086/8088, 80186/80188, 80286, with 8087, 80187 or 80287 for floating-point, with an 80-bit wide, 8 deep register stack with some instructions able to use registers relative to the top of the stack as operands; without 8087/80187/80287, no floating-point registers|
|IA-32||8||stack of 8 (if FP present), 8 (if SSE/MMX present)||80386 required 80387 for floating-point, later processors had built-in floating point, with both having an 80-bit wide, 8 deep register stack with some instructions able to use registers relative to the top of the stack as operands. The Pentium III and later had the SSE with additional 128-bit XMM registers.|
|x86-64||16||16/32||FP registers are 128-bit XMM registers, later extended to 256-bit YMM registers with AVX/AVX2 and 512-bit ZMM0-ZMM31 registers with AVX-512.|
|Xeon Phi||16||32||Including 32 256/512-bit ZMM registers with AVX-512.|
|Geode GX||1 data, 1 address||8||Geode GX/Media GX/4x86/5x86 is the emulation of 486/Pentium compatible processor made by Cyrix/National Semiconductor. Like Transmeta, the processor had a translation layer that translated x86 code to native code and executed it.[ citation needed ] It does not support 128-bit SSE registers, just the 80387 stack of eight 80-bit floating point registers, and partially support 3DNow! from AMD. The native processor only contains 1 data and 1 address register for all purpose and translated into 4 paths of 32-bit naming register r1 (base), r2 (data), r3 (back pointer), and r4 (stack pointer) within scratchpad sram for integer operation and uses the L1 cache for x86 code emulation(note that it's not compatible with some 286/386/486 instructions in real mode).[ citation needed ] Later the design was abandoned after AMD acquired the IP from National Semiconductor and branded it with Athlon core in embedded market.|
|SunPlus SPG||0||6 stack + 4 SIMD||A 16-bit wide, 32-bit address space stack machine processor that made from Taiwanese semiconductor called "Sunplus", it can be found on Vtech's v'smile line for educational purpose and video game console like Mattel hyperscan, XaviXPORT. it does lack any general purpose register or internal register for naming/renaming but its Floating Point Unit has 80-bit 6 stage stack and four 128-bit VLIW SIMD register on a vertex shader co-processor.|
|VM Labs Nuon||0||1||a 32-bit stack machine processor that developed by VM labs for specialized on multimedia purpose. It can be found on the company's own Nuon DVD player console line and Game Wave Family Entertainment System from ZaPit games. The design was heavy influence by Intel's MMX technology, it contained a 128 bytes unified stack cache for both vector and scalar instructions. the unified cache can be divided as 8 128-bit vector register or 32 32bit SIMD scalar register through bank renaming, no integer register found in this architecture.|
|Nios II||31||8||Nios II is based on MIPS IV instruction set[ citation needed ] and has 31 32-bit GPRs, with register 0 being hardwired to zero and 8 64-bit floating point registers[ citation needed ]|
|Motorola 6800||2 data, 1 index||0||Plus a stack pointer|
|Motorola 68k||8 data (d0-d7), 8 address (a0-a7)||8 (if FP present)||Address register 8 (a7) is the stack pointer. 68000, 68010, 68012, 68020, and 68030 require an FPU for floating point; 68040 had FPU built in. FP registers are 80-bit.|
|Emotion Engine||3(VU0)+ 32(VU1)||32 SIMD(integrated in UV1) + 2x 32 Vector (dedicated vector co-processor that located near by its GPU)||The Emotion Engine's main core (VU0) is a heavily modified DSP general core that's for general background task and it contains one 64 bit accumulator, two general data registers and one 32 bit program counter. A modified MIPS III executable core(VU1) is for game data and protocol control and it contains 32 entries 32-bit general-purpose registers for integer computation and 32 entries 128-bit SIMD registers for storing SIMD instruction, streaming data value and some integer calculation value. one accumulator register for connecting general floating-point computation to vector register file on co-processor. The coprocessor is built via 32 entries 128-bit vector register file(can only store vector value that pass from accumulator in cpu. ) and no integer register is built in. Both vector co-processor(VPU 0/1) and emotion engine's entire main processor module(VU0 + VU1 + VPU0 + VPU1) are built based on modified MIPS instructions set and accumulator in this case is not general purpose but control status.|
|CUDA||1||8/16/32/64/128||Each CUDA core contains a single 32/64-bit integer data register while the floating point unit contains a much larger number of registers: |
|IBM/360||16||4 (if FP present)||This applies to S/360's successors, System/370 through System/390; FP was optional in System/360, and always present in S/370 and later. In processors with the Vector Facility, there are 16 vector registers containing a machine-dependent number of 32-bit elements.|
|z/Architecture||16||16||64-bit version of S/360 and successors|
|MMIX||256||256||An instruction set designed by Donald Knuth in the late 1990s for pedagogical purposes.|
|NS320xx||8||8 (if FP present)|
|Xelerated X10||1||32||a 32/40 bit stack machine based network processor with modified MIPS instruction and 128 bit floating point unit.|
|Parallax Propeller||0||2||An eight core 8/16 bit sliced stack machine controller with simple logic circus inside, have eight cog counter(core) and each contain three 8/16 bit special control registers with 32 bit x 512 stack ram however it does not carrying any general register for integer purpose. unlike most of shadow register file in modern processor and multi core system, all these stack ram in cog can be accessed in instruction level which all these cog can act as one big single general purpose core if necessary. Floating point unit is external and it contain two 80 bit vector register.|
|Itanium||128||128||And 64 1-bit predicate registers and 8 branch registers. The FP registers are 82-bit.|
|SPARC||31||32||Global register 0 is hardwired to 0. Uses register windows.|
|IBM POWER||32||32||And 1 link and 1 count register.|
|Power ISA||32||32||And 1 link and 1 count register. Processors supporting the Vector facility also have 32 128-bit vector registers,|
|Blackfin||8||16||containing two external uncore 40 bit accumulator, but non are general purpose. Support 64 bit RISC architecture ISA, vector register are 256 bit.|
|IBM Cell SPE||128||128 GPRs, which can hold integer, address, or floating-point values|
|PDP-10||16||0||All may be used generally (integer, float, stack pointer, jump, indexing, etc.). Every 36-bit memory (or register) word can also be manipulated as a half-word, which can be considered an (18-bit) address. Other word interpretations are used by certain instructions. In the original PDP-10 processors, these 16 GPRs also corresponded to main (i.e. core) memory locations 0-15; a hardware option called "fast memory" implemented the registers as separate ICs, and references to memory locations 0-15 referred to the IC registers. Later models implemented the registers as "fast memory" and continued to make memory locations 0-15 refer to them. Movement instructions take (register, memory) operands: |
|PDP-11||8||0||R7 is actually the Program Counter. Any register can be a stack pointer but R6 is used for hardware interrupts and traps.|
|VAX||16||0||Three of the registers have special uses: R12 (Argument Pointer), R13 (Frame Pointer), and R14 (Stack Pointer), while R15 refers to the Program Counter.|
|Alpha||31||31||Registers R31 (integer) and F31 (floating-point) are hardwired to zero.|
|6502||1 data, 2 index||0||6502's content A (Accumulator) register for main purpose data store and memory address (8-bit data/16-bit address), X,Y are indirect and direct index registers (respectively) and SP register are specific index only.|
|W65C816S||1||0||65C816 is the 16-bit successor of the 6502. X,Y, D (Direct Page register) are condition register and SP register are specific index only. main accumulator extended to 16-bit (B) while keep 8-bit (A) for compatibility and main register can now address up to 24-bit (16-bit wide data instruction/24-bit memory address).|
|65k||1||0||Direct successor of 6502, 65002 only content A (Accumulator) register for main purpose data store and extend data wide to 32-bit and 64-bit instruction wide, support 48-bit virtual address in software mode, X,Y are still condition register and remain 8-bit and SP register are specific index but increase to 16-bit wide.|
|MeP||4||8||Media-embedded processor was a 32 bit processor developed by toshiba, a modded 8080 instruction set with only A, B, C, D register available through all mode(8/16/32 bit) and incompatible with x86, however it contain 80 bit floating point unit that is x87 compatible.|
|ARM 32-bit (ARM/A32, Thumb/T32)||14||Varies (up to 32)||r15 is the program counter, and not usable as a GPR; r13 is the stack pointer; r8-r13 can be switched out for others (banked) on a processor mode switch. Older versions had 26-bit addressing, and used upper bits of the program counter (r15) for status flags, making that register 32-bit.|
|ARM 64-bit (A64)||31||32||Register r31 is the stack pointer or hardwired to 0, depending on the context.|
|MIPS||31||32||Register 0 is hardwired to 0.|
|Epiphany||64 (per core)||Each instruction controls whether registers are interpreted as integers or single precision floating point. Architecture is scalable to 4096 cores with 16 and 64 core implementations currently available.|
The number of registers available on a processor and the operations that can be performed using those registers has a significant impact on the efficiency of code generated by optimizing compilers. The Strahler number of an expression tree gives the minimum number of registers required to evaluate that expression tree.
The Intel 8080 ("eighty-eighty") was the second 8-bit microprocessor designed and manufactured by Intel and was released in April 1974. It is an extended and enhanced variant of the earlier 8008 design, although without binary compatibility. The initial specified clock frequency limit was 2 MHz, and with common instructions using 4, 5, 7, 10, or 11 cycles this meant that it operated at a typical speed of a few hundred thousand instructions per second. A faster variant 8080A-1 became available later with clock frequency limit up to 3.125 MHz.
The 8086 is a 16-bit microprocessor chip designed by Intel between early 1976 and June 8, 1978, when it was released. The Intel 8088, released July 1, 1979, is a slightly modified chip with an external 8-bit data bus, and is notable as the processor used in the original IBM PC design, including the widespread version called IBM PC XT.
Microcode is a computer hardware technique that imposes an interpreter between the CPU hardware and the programmer-visible instruction set architecture of the computer. As such, the microcode is a layer of hardware-level instructions that implement higher-level machine code instructions or internal state machine sequencing in many digital processing elements. Microcode is used in general-purpose central processing units, although in current desktop CPUs it is only a fallback path for cases that the faster hardwired control unit cannot handle.
The Motorola 68000 is a 16/32-bit CISC microprocessor, which implements a 32-bit instruction set, with 32-bit registers and 32-bit internal data bus, but with a 16-bit data ALU and two 16-bit arithmetic ALUs and a 16-bit external data bus, designed and marketed by Motorola Semiconductor Products Sector. Introduced in 1979 with HMOS technology as the first member of the successful 32-bit Motorola 68000 series, it is generally software forward-compatible with the rest of the line despite being limited to a 16-bit wide external bus. After 39 years in production, the 68000 architecture is still in use.
x86 is a family of instruction set architectures based on the Intel 8086 microprocessor and its 8088 variant. The 8086 was introduced in 1978 as a fully 16-bit extension of Intel's 8-bit 8080 microprocessor, with memory segmentation as a solution for addressing more memory than can be covered by a plain 16-bit address. The term "x86" came into being because the names of several successors to Intel's 8086 processor end in "86", including the 80186, 80286, 80386 and 80486 processors.
x86 memory segmentation refers to the implementation of memory segmentation in the Intel x86 computer instruction set architecture. Segmentation was introduced on the Intel 8086 in 1978 as a way to allow programs to address more than 64 KB (65,536 bytes) of memory. The Intel 80286 introduced a second version of segmentation in 1982 that added support for virtual memory and memory protection. At this point the original model was renamed real mode, and the new version was named protected mode. The x86-64 architecture, introduced in 2003, has largely dropped support for segmentation in 64-bit mode.
x86 assembly language is a family of backward-compatible assembly languages, which provide some level of compatibility all the way back to the Intel 8008 introduced in April 1972. x86 assembly languages are used to produce object code for the x86 class of processors. Like all assembly languages, it uses short mnemonics to represent the fundamental instructions that the CPU in a computer can understand and follow. Compilers sometimes produce assembly code as an intermediate step when translating a high level program into machine code. Regarded as a programming language, assembly coding is machine-specific and low level. Assembly languages are more typically used for detailed and time critical applications such as small real-time embedded systems or operating system kernels and device drivers.
x86-64 is the 64-bit version of the x86 instruction set. It introduces two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging mode. With 64-bit mode and the new paging mode, it supports vastly larger amounts of virtual memory and physical memory than is possible on its 32-bit predecessors, allowing programs to store larger amounts of data in memory. x86-64 also expands general-purpose registers to 64-bit, as well extends the number of them from 8 to 16, and provides numerous other enhancements. Floating point operations are supported via mandatory SSE2-like instructions, and x87/MMX style registers are generally not used ; instead, a set of 32 vector registers, 128 bits each, is used. In 64-bit mode, instructions are modified to support 64-bit operands and 64-bit addressing mode. The compatibility mode allows 16- and 32-bit user applications to run unmodified coexisting with 64-bit applications if the 64-bit operating system supports them. As the full x86 16-bit and 32-bit instruction sets remain implemented in hardware without any intervening emulation, these older executables can run with little or no performance penalty, while newer or modified applications can take advantage of new features of the processor design to achieve performance improvements. Also, a processor supporting x86-64 still powers on in real mode for full backward compatibility.
In computer science, computer engineering and programming language implementations, a stack machine is a type of computer. In some cases, the term refers to a software scheme that simulates a stack machine. The main difference from other computers is that most of its instructions operate on a pushdown stack of numbers rather than numbers in registers. Most computer systems implement a stack in some form to pass parameters and link to subroutines. This does not make these computers stack machines.
Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how machine language instructions in that architecture identify the operand(s) of each instruction. An addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere.
Introduced in June 1976, the TMS9900 was one of the first commercially available, single-chip 16-bit microprocessors. The TMS9900 found its most widespread use in the TI-99/4 and TI-99/4A home computers.
In computer engineering, an orthogonal instruction set is an instruction set architecture where all instruction types can use all addressing modes. It is "orthogonal" in the sense that the instruction type and the addressing mode vary independently. An orthogonal instruction set does not impose a limitation that requires a certain instruction to use a specific register.
The Clipper architecture is a 32-bit RISC-like instruction set architecture designed by Fairchild Semiconductor. The architecture never enjoyed much market success, and the only computer manufacturers to create major product lines using Clipper processors were Intergraph and High Level Hardware. The first processors using the Clipper architecture were designed and sold by Fairchild, but the division responsible for them was subsequently sold to Intergraph in 1987; Intergraph continued work on Clipper processors for use in its own systems.
The task state segment (TSS) is a special structure on x86-based computers which holds information about a task. It is used by the operating system kernel for task management. Specifically, the following information is stored in the TSS:
A stack register is a computer central processor register whose purpose is to keep track of a call stack. On an accumulator-based architecture machine, this may be a dedicated register such as SP on an Intel x86 machine. On a general register machine, it may be a register which is reserved by convention, such as on the PDP-11 or RISC machines. Some designs such as the Data General Eclipse had no dedicated register, but used a reserved hardware memory address for this function.
The PDP-11 architecture is an instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC). It is implemented by central processing units (CPUs) and microprocessors used in PDP-11 minicomputers. It was in wide use during the 1970s, but was eventually overshadowed by the more powerful VAX-11 architecture in the 1980s.
In computer architecture, 16-bit integers, memory addresses, or other data units are those that are 16 bits wide. Also, 16-bit CPU and ALU architectures are those that are based on registers, address buses, or data buses of that size. 16-bit microcomputers are computers in which 16-bit microprocessors were the norm.
RISC-V is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.