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Developer(s) | Nvidia |
---|---|
Initial release | June 23, 2007 |
Stable release | 12.6 / August 2024 |
Operating system | Windows, Linux |
Platform | Supported GPUs |
Type | GPGPU |
License | Proprietary |
Website | developer |
In computing, CUDA (originally Compute Unified Device Architecture) is a proprietary [1] parallel computing platform and application programming interface (API) that allows software to use certain types of graphics processing units (GPUs) for accelerated general-purpose processing, an approach called general-purpose computing on GPUs (GPGPU). CUDA API and its runtime: The CUDA API is an extension of the C programming language that adds the ability to specify thread-level parallelism in C and also to specify GPU device specific operations (like moving data between the CPU and the GPU). [2] CUDA is a software layer that gives direct access to the GPU's virtual instruction set and parallel computational elements for the execution of compute kernels. [3] In addition to drivers and runtime kernels, the CUDA platform includes compilers, libraries and developer tools to help programmers accelerate their applications.
CUDA is designed to work with programming languages such as C, C++, Fortran and Python. This accessibility makes it easier for specialists in parallel programming to use GPU resources, in contrast to prior APIs like Direct3D and OpenGL, which require advanced skills in graphics programming. [4] CUDA-powered GPUs also support programming frameworks such as OpenMP, OpenACC and OpenCL. [5] [3]
CUDA was created by Nvidia in 2006. [6] When it was first introduced, the name was an acronym for Compute Unified Device Architecture, [7] but Nvidia later dropped the common use of the acronym and now rarely expands it. [8]
The graphics processing unit (GPU), as a specialized computer processor, addresses the demands of real-time high-resolution 3D graphics compute-intensive tasks. By 2012, GPUs had evolved into highly parallel multi-core systems allowing efficient manipulation of large blocks of data. This design is more effective than general-purpose central processing unit (CPUs) for algorithms in situations where processing large blocks of data is done in parallel, such as:
Ian Buck, while at Stanford in 2000, created an 8K gaming rig using 32 GeForce cards, then obtained a DARPA grant to perform general purpose parallel programming on GPUs. He then joined Nvidia, where since 2004 he has been overseeing CUDA development. In pushing for CUDA, Jensen Huang aimed for the Nvidia GPUs to become a general hardware for scientific computing. CUDA was released in 2006. Around 2015, the focus of CUDA changed to neural networks. [9]
The following table offers a non-exact description for the ontology of CUDA framework.
memory (hardware) | memory (code, or variable scoping) | computation (hardware) | computation (code syntax) | computation (code semantics) |
---|---|---|---|---|
RAM | non-CUDA variables | host | program | one routine call |
VRAM, GPU L2 cache | global, const, texture | device | grid | simultaneous call of the same subroutine on many processors |
GPU L1 cache | local, shared | SM ("streaming multiprocessor") | block | individual subroutine call |
warp = 32 threads | SIMD instructions | |||
GPU L0 cache, register | thread (aka. "SP", "streaming processor", "cuda core", but these names are now deprecated) | analogous to individual scalar ops within a vector op |
The CUDA platform is accessible to software developers through CUDA-accelerated libraries, compiler directives such as OpenACC, and extensions to industry-standard programming languages including C, C++, Fortran and Python. C/C++ programmers can use 'CUDA C/C++', compiled to PTX with nvcc, Nvidia's LLVM-based C/C++ compiler, or by clang itself. [10] Fortran programmers can use 'CUDA Fortran', compiled with the PGI CUDA Fortran compiler from The Portland Group.[ needs update ] Python programmers can use the cuNumeric library to accelerate applications on Nvidia GPUs.
In addition to libraries, compiler directives, CUDA C/C++ and CUDA Fortran, the CUDA platform supports other computational interfaces, including the Khronos Group's OpenCL, [11] Microsoft's DirectCompute, OpenGL Compute Shader and C++ AMP. [12] Third party wrappers are also available for Python, Perl, Fortran, Java, Ruby, Lua, Common Lisp, Haskell, R, MATLAB, IDL, Julia, and native support in Mathematica.
In the computer game industry, GPUs are used for graphics rendering, and for game physics calculations (physical effects such as debris, smoke, fire, fluids); examples include PhysX and Bullet. CUDA has also been used to accelerate non-graphical applications in computational biology, cryptography and other fields by an order of magnitude or more. [13] [14] [15] [16] [17]
CUDA provides both a low level API (CUDA Driver API, non single-source) and a higher level API (CUDA Runtime API, single-source). The initial CUDA SDK was made public on 15 February 2007, for Microsoft Windows and Linux. Mac OS X support was later added in version 2.0, [18] which supersedes the beta released February 14, 2008. [19] CUDA works with all Nvidia GPUs from the G8x series onwards, including GeForce, Quadro and the Tesla line. CUDA is compatible with most standard operating systems.
CUDA 8.0 comes with the following libraries (for compilation & runtime, in alphabetical order):
CUDA 8.0 comes with these other software components:
CUDA 9.0–9.2 comes with these other components:
CUDA 10 comes with these other components:
CUDA 11.0–11.8 comes with these other components: [20] [21] [22] [23]
CUDA has several advantages over traditional general-purpose computation on GPUs (GPGPU) using graphics APIs:
This example code in C++ loads a texture from an image into an array on the GPU:
texture<float,2,cudaReadModeElementType>tex;voidfoo(){cudaArray*cu_array;// Allocate arraycudaChannelFormatDescdescription=cudaCreateChannelDesc<float>();cudaMallocArray(&cu_array,&description,width,height);// Copy image data to arraycudaMemcpyToArray(cu_array,image,width*height*sizeof(float),cudaMemcpyHostToDevice);// Set texture parameters (default)tex.addressMode[0]=cudaAddressModeClamp;tex.addressMode[1]=cudaAddressModeClamp;tex.filterMode=cudaFilterModePoint;tex.normalized=false;// do not normalize coordinates// Bind the array to the texturecudaBindTextureToArray(tex,cu_array);// Run kerneldim3blockDim(16,16,1);dim3gridDim((width+blockDim.x-1)/blockDim.x,(height+blockDim.y-1)/blockDim.y,1);kernel<<<gridDim,blockDim,0>>>(d_data,height,width);// Unbind the array from the texturecudaUnbindTexture(tex);}//end foo()__global__voidkernel(float*odata,intheight,intwidth){unsignedintx=blockIdx.x*blockDim.x+threadIdx.x;unsignedinty=blockIdx.y*blockDim.y+threadIdx.y;if(x<width&&y<height){floatc=tex2D(tex,x,y);odata[y*width+x]=c;}}
Below is an example given in Python that computes the product of two arrays on the GPU. The unofficial Python language bindings can be obtained from PyCUDA. [36]
importpycuda.compilerascompimportpycuda.driverasdrvimportnumpyimportpycuda.autoinitmod=comp.SourceModule("""__global__ void multiply_them(float *dest, float *a, float *b){ const int i = threadIdx.x; dest[i] = a[i] * b[i];}""")multiply_them=mod.get_function("multiply_them")a=numpy.random.randn(400).astype(numpy.float32)b=numpy.random.randn(400).astype(numpy.float32)dest=numpy.zeros_like(a)multiply_them(drv.Out(dest),drv.In(a),drv.In(b),block=(400,1,1))print(dest-a*b)
Additional Python bindings to simplify matrix multiplication operations can be found in the program pycublas. [37]
importnumpyfrompycublasimportCUBLASMatrixA=CUBLASMatrix(numpy.mat([[1,2,3],[4,5,6]],numpy.float32))B=CUBLASMatrix(numpy.mat([[2,3],[4,5],[6,7]],numpy.float32))C=A*Bprint(C.np_mat())
while CuPy directly replaces NumPy: [38]
importcupya=cupy.random.randn(400)b=cupy.random.randn(400)dest=cupy.zeros_like(a)print(dest-a*b)
Supported CUDA Compute Capability versions for CUDA SDK version and Microarchitecture (by code name):
CUDA SDK Version(s) | Tesla | Fermi | Kepler (Early) | Kepler (Late) | Maxwell | Pascal | Volta | Turing | Ampere | Ada Lovelace | Hopper | Blackwell |
---|---|---|---|---|---|---|---|---|---|---|---|---|
1.0 [39] | 1.0 – 1.1 | |||||||||||
1.1 | 1.0 – 1.1+x | |||||||||||
2.0 | 1.0 – 1.1+x | |||||||||||
2.1 – 2.3.1 [40] [41] [42] [43] | 1.0 – 1.3 | |||||||||||
3.0 – 3.1 [44] [45] | 1.0 | 2.0 | ||||||||||
3.2 [46] | 1.0 | 2.1 | ||||||||||
4.0 – 4.2 | 1.0 | 2.1 | ||||||||||
5.0 – 5.5 | 1.0 | 3.5 | ||||||||||
6.0 | 1.0 | 3.2 | 3.5 | |||||||||
6.5 | 1.1 | 3.7 | 5.x | |||||||||
7.0 – 7.5 | 2.0 | 5.x | ||||||||||
8.0 | 2.0 | 6.x | ||||||||||
9.0 – 9.2 | 3.0 | 7.0 – 7.2 | ||||||||||
10.0 – 10.2 | 3.0 | 7.5 | ||||||||||
11.0 [47] | 3.5 | 8.0 | ||||||||||
11.1 – 11.4 [48] | 3.5 | 8.6 | ||||||||||
11.5 – 11.7.1 [49] | 3.5 | 8.7 | ||||||||||
11.8 [50] | 3.5 | 8.9 | 9.0 | |||||||||
12.0 – 12.5 | 5.0 | 9.0 |
Note: CUDA SDK 10.2 is the last official release for macOS, as support will not be available for macOS in newer releases.
CUDA Compute Capability by version with associated GPU semiconductors and GPU card models (separated by their various application areas):
Compute capability (version) | Micro- architecture | GPUs | GeForce | Quadro, NVS | Tesla/Datacenter | Tegra, Jetson, DRIVE |
---|---|---|---|---|---|---|
1.0 | Tesla | G80 | GeForce 8800 Ultra, GeForce 8800 GTX, GeForce 8800 GTS(G80) | Quadro FX 5600, Quadro FX 4600, Quadro Plex 2100 S4 | Tesla C870, Tesla D870, Tesla S870 | |
1.1 | G92, G94, G96, G98, G84, G86 | GeForce GTS 250, GeForce 9800 GX2, GeForce 9800 GTX, GeForce 9800 GT, GeForce 8800 GTS(G92), GeForce 8800 GT, GeForce 9600 GT, GeForce 9500 GT, GeForce 9400 GT, GeForce 8600 GTS, GeForce 8600 GT, GeForce 8500 GT, GeForce G110M, GeForce 9300M GS, GeForce 9200M GS, GeForce 9100M G, GeForce 8400M GT, GeForce G105M | Quadro FX 4700 X2, Quadro FX 3700, Quadro FX 1800, Quadro FX 1700, Quadro FX 580, Quadro FX 570, Quadro FX 470, Quadro FX 380, Quadro FX 370, Quadro FX 370 Low Profile, Quadro NVS 450, Quadro NVS 420, Quadro NVS 290, Quadro NVS 295, Quadro Plex 2100 D4, Quadro FX 3800M, Quadro FX 3700M, Quadro FX 3600M, Quadro FX 2800M, Quadro FX 2700M, Quadro FX 1700M, Quadro FX 1600M, Quadro FX 770M, Quadro FX 570M, Quadro FX 370M, Quadro FX 360M, Quadro NVS 320M, Quadro NVS 160M, Quadro NVS 150M, Quadro NVS 140M, Quadro NVS 135M, Quadro NVS 130M, Quadro NVS 450, Quadro NVS 420, [51] Quadro NVS 295 | |||
1.2 | GT218, GT216, GT215 | GeForce GT 340*, GeForce GT 330*, GeForce GT 320*, GeForce 315*, GeForce 310*, GeForce GT 240, GeForce GT 220, GeForce 210, GeForce GTS 360M, GeForce GTS 350M, GeForce GT 335M, GeForce GT 330M, GeForce GT 325M, GeForce GT 240M, GeForce G210M, GeForce 310M, GeForce 305M | Quadro FX 380 Low Profile, Quadro FX 1800M, Quadro FX 880M, Quadro FX 380M, Nvidia NVS 300, NVS 5100M, NVS 3100M, NVS 2100M, ION | |||
1.3 | GT200, GT200b | GeForce GTX 295, GTX 285, GTX 280, GeForce GTX 275, GeForce GTX 260 | Quadro FX 5800, Quadro FX 4800, Quadro FX 4800 for Mac, Quadro FX 3800, Quadro CX, Quadro Plex 2200 D2 | Tesla C1060, Tesla S1070, Tesla M1060 | ||
2.0 | Fermi | GF100, GF110 | GeForce GTX 590, GeForce GTX 580, GeForce GTX 570, GeForce GTX 480, GeForce GTX 470, GeForce GTX 465, GeForce GTX 480M | Quadro 6000, Quadro 5000, Quadro 4000, Quadro 4000 for Mac, Quadro Plex 7000, Quadro 5010M, Quadro 5000M | Tesla C2075, Tesla C2050/C2070, Tesla M2050/M2070/M2075/M2090 | |
2.1 | GF104, GF106 GF108, GF114, GF116, GF117, GF119 | GeForce GTX 560 Ti, GeForce GTX 550 Ti, GeForce GTX 460, GeForce GTS 450, GeForce GTS 450*, GeForce GT 640 (GDDR3), GeForce GT 630, GeForce GT 620, GeForce GT 610, GeForce GT 520, GeForce GT 440, GeForce GT 440*, GeForce GT 430, GeForce GT 430*, GeForce GT 420*, GeForce GTX 675M, GeForce GTX 670M, GeForce GT 635M, GeForce GT 630M, GeForce GT 625M, GeForce GT 720M, GeForce GT 620M, GeForce 710M, GeForce 610M, GeForce 820M, GeForce GTX 580M, GeForce GTX 570M, GeForce GTX 560M, GeForce GT 555M, GeForce GT 550M, GeForce GT 540M, GeForce GT 525M, GeForce GT 520MX, GeForce GT 520M, GeForce GTX 485M, GeForce GTX 470M, GeForce GTX 460M, GeForce GT 445M, GeForce GT 435M, GeForce GT 420M, GeForce GT 415M, GeForce 710M, GeForce 410M | Quadro 2000, Quadro 2000D, Quadro 600, Quadro 4000M, Quadro 3000M, Quadro 2000M, Quadro 1000M, NVS 310, NVS 315, NVS 5400M, NVS 5200M, NVS 4200M | |||
3.0 | Kepler | GK104, GK106, GK107 | GeForce GTX 770, GeForce GTX 760, GeForce GT 740, GeForce GTX 690, GeForce GTX 680, GeForce GTX 670, GeForce GTX 660 Ti, GeForce GTX 660, GeForce GTX 650 Ti BOOST, GeForce GTX 650 Ti, GeForce GTX 650, GeForce GTX 880M, GeForce GTX 870M, GeForce GTX 780M, GeForce GTX 770M, GeForce GTX 765M, GeForce GTX 760M, GeForce GTX 680MX, GeForce GTX 680M, GeForce GTX 675MX, GeForce GTX 670MX, GeForce GTX 660M, GeForce GT 750M, GeForce GT 650M, GeForce GT 745M, GeForce GT 645M, GeForce GT 740M, GeForce GT 730M, GeForce GT 640M, GeForce GT 640M LE, GeForce GT 735M, GeForce GT 730M | Quadro K5000, Quadro K4200, Quadro K4000, Quadro K2000, Quadro K2000D, Quadro K600, Quadro K420, Quadro K500M, Quadro K510M, Quadro K610M, Quadro K1000M, Quadro K2000M, Quadro K1100M, Quadro K2100M, Quadro K3000M, Quadro K3100M, Quadro K4000M, Quadro K5000M, Quadro K4100M, Quadro K5100M, NVS 510, Quadro 410 | Tesla K10, GRID K340, GRID K520, GRID K2 | |
3.2 | GK20A | Tegra K1, Jetson TK1 | ||||
3.5 | GK110, GK208 | GeForce GTX Titan Z, GeForce GTX Titan Black, GeForce GTX Titan, GeForce GTX 780 Ti, GeForce GTX 780, GeForce GT 640 (GDDR5), GeForce GT 630 v2, GeForce GT 730, GeForce GT 720, GeForce GT 710, GeForce GT 740M (64-bit, DDR3), GeForce GT 920M | Quadro K6000, Quadro K5200 | Tesla K40, Tesla K20x, Tesla K20 | ||
3.7 | GK210 | Tesla K80 | ||||
5.0 | Maxwell | GM107, GM108 | GeForce GTX 750 Ti, GeForce GTX 750, GeForce GTX 960M, GeForce GTX 950M, GeForce 940M, GeForce 930M, GeForce GTX 860M, GeForce GTX 850M, GeForce 845M, GeForce 840M, GeForce 830M | Quadro K1200, Quadro K2200, Quadro K620, Quadro M2000M, Quadro M1000M, Quadro M600M, Quadro K620M, NVS 810 | Tesla M10 | |
5.2 | GM200, GM204, GM206 | GeForce GTX Titan X, GeForce GTX 980 Ti, GeForce GTX 980, GeForce GTX 970, GeForce GTX 960, GeForce GTX 950, GeForce GTX 750 SE, GeForce GTX 980M, GeForce GTX 970M, GeForce GTX 965M | Quadro M6000 24GB, Quadro M6000, Quadro M5000, Quadro M4000, Quadro M2000, Quadro M5500, Quadro M5000M, Quadro M4000M, Quadro M3000M | Tesla M4, Tesla M40, Tesla M6, Tesla M60 | ||
5.3 | GM20B | Tegra X1, Jetson TX1, Jetson Nano, DRIVE CX, DRIVE PX | ||||
6.0 | Pascal | GP100 | Quadro GP100 | Tesla P100 | ||
6.1 | GP102, GP104, GP106, GP107, GP108 | Nvidia TITAN Xp, Titan X, GeForce GTX 1080 Ti, GTX 1080, GTX 1070 Ti, GTX 1070, GTX 1060, GTX 1050 Ti, GTX 1050, GT 1030, GT 1010, MX350, MX330, MX250, MX230, MX150, MX130, MX110 | Quadro P6000, Quadro P5000, Quadro P4000, Quadro P2200, Quadro P2000, Quadro P1000, Quadro P400, Quadro P500, Quadro P520, Quadro P600, Quadro P5000(Mobile), Quadro P4000(Mobile), Quadro P3000(Mobile) | Tesla P40, Tesla P6, Tesla P4 | ||
6.2 | GP10B [52] | Tegra X2, Jetson TX2, DRIVE PX 2 | ||||
7.0 | Volta | GV100 | NVIDIA TITAN V | Quadro GV100 | Tesla V100, Tesla V100S | |
7.2 | GV10B [53] | Tegra Xavier, Jetson Xavier NX, Jetson AGX Xavier, DRIVE AGX Xavier, DRIVE AGX Pegasus, Clara AGX | ||||
7.5 | Turing | TU102, TU104, TU106, TU116, TU117 | NVIDIA TITAN RTX, GeForce RTX 2080 Ti, RTX 2080 Super, RTX 2080, RTX 2070 Super, RTX 2070, RTX 2060 Super, RTX 2060 12GB, RTX 2060, GeForce GTX 1660 Ti, GTX 1660 Super, GTX 1660, GTX 1650 Super, GTX 1650, MX550, MX450 | Quadro RTX 8000, Quadro RTX 6000, Quadro RTX 5000, Quadro RTX 4000, T1000, T600, T400 T1200(mobile), T600(mobile), T500(mobile), Quadro T2000(mobile), Quadro T1000(mobile) | Tesla T4 | |
8.0 | Ampere | GA100 | A100 80GB, A100 40GB, A30 | |||
8.6 | GA102, GA103, GA104, GA106, GA107 | GeForce RTX 3090 Ti, RTX 3090, RTX 3080 Ti, RTX 3080 12GB, RTX 3080, RTX 3070 Ti, RTX 3070, RTX 3060 Ti, RTX 3060, RTX 3050, RTX 3050 Ti(mobile), RTX 3050(mobile), RTX 2050(mobile), MX570 | RTX A6000, RTX A5500, RTX A5000, RTX A4500, RTX A4000, RTX A2000 RTX A5000(mobile), RTX A4000(mobile), RTX A3000(mobile), RTX A2000(mobile) | A40, A16, A10, A2 | ||
8.7 | GA10B | Jetson Orin Nano, Jetson Orin NX, Jetson AGX Orin, DRIVE AGX Orin, DRIVE AGX Pegasus OA, Clara Holoscan | ||||
8.9 | Ada Lovelace [56] | AD102, AD103, AD104, AD106, AD107 | GeForce RTX 4090, RTX 4080 Super, RTX 4080, RTX 4070 Ti Super, RTX 4070 Ti, RTX 4070 Super, RTX 4070, RTX 4060 Ti, RTX 4060 | RTX 6000 Ada, RTX 5880 Ada, RTX 5000 Ada, RTX 4500 Ada, RTX 4000 Ada, RTX 4000 SFF | L40S, L40, L20, L4, L2 | |
9.0 | Hopper | GH100 | H200, H100 | |||
10.0 | Blackwell | GB100 | B200, B100 | |||
10.x | GB202, GB203, GB205, GB206, GB207 | GeForce RTX 5090, RTX 5080 | B40 | |||
Compute capability (version) | Micro- architecture | GPUs | GeForce | Quadro, NVS | Tesla/Datacenter | Tegra, Jetson, DRIVE |
'*' – OEM-only products
This section needs to be updated. The reason given is: Missing CUDA compute capability 10.x (Blackwell).(March 2024) |
Feature support (unlisted features are supported for all compute capabilities) | Compute capability (version) | |||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1.0, 1.1 | 1.2, 1.3 | 2.x | 3.0 | 3.2 | 3.5, 3.7, 5.x, 6.x, 7.0, 7.2 | 7.5 | 8.x | 9.0 | ||||||
Warp vote functions (__all(), __any()) | No | Yes | ||||||||||||
Warp vote functions (__ballot()) | No | Yes | ||||||||||||
Memory fence functions (__threadfence_system()) | ||||||||||||||
Synchronization functions (__syncthreads_count(), __syncthreads_and(), __syncthreads_or()) | ||||||||||||||
Surface functions | ||||||||||||||
3D grid of thread blocks | ||||||||||||||
Warp shuffle functions | No | Yes | ||||||||||||
Unified memory programming | ||||||||||||||
Funnel shift | No | Yes | ||||||||||||
Dynamic parallelism | No | Yes | ||||||||||||
Uniform Datapath [57] | No | Yes | ||||||||||||
Hardware-accelerated async-copy | No | Yes | ||||||||||||
Hardware-accelerated split arrive/wait barrier | ||||||||||||||
Warp-level support for reduction ops | ||||||||||||||
L2 cache residency management | ||||||||||||||
DPX instructions for accelerated dynamic programming | No | Yes | ||||||||||||
Distributed shared memory | ||||||||||||||
Thread block cluster | ||||||||||||||
Tensor memory accelerator (TMA) unit | ||||||||||||||
Feature support (unlisted features are supported for all compute capabilities) | 1.0,1.1 | 1.2,1.3 | 2.x | 3.0 | 3.2 | 3.5, 3.7, 5.x, 6.x, 7.0, 7.2 | 7.5 | 8.x | 9.0 | |||||
Compute capability (version) |
Data type | Operation | Supported since | Atomic Operation | Supported since for global memory | Supported since for shared memory |
---|---|---|---|---|---|
8-bit integer signed/unsigned | loading, storing, conversion | 1.0 | — | — | |
16-bit integer signed/unsigned | general operations | 1.0 | atomicCAS() | 3.5 | |
32-bit integer signed/unsigned | general operations | 1.0 | atomic functions | 1.1 | 1.2 |
64-bit integer signed/unsigned | general operations | 1.0 | atomic functions | 1.2 | 2.0 |
any 128-bit trivially copyable type | general operations | No | atomicExch, atomicCAS | 9.0 | |
16-bit floating point FP16 | addition, subtraction, multiplication, comparison, warp shuffle functions, conversion | 5.3 | half2 atomic addition | 6.0 | |
atomic addition | 7.0 | ||||
16-bit floating point BF16 | addition, subtraction, multiplication, comparison, warp shuffle functions, conversion | 8.0 | atomic addition | 8.0 | |
32-bit floating point | general operations | 1.0 | atomicExch() | 1.1 | 1.2 |
atomic addition | 2.0 | ||||
32-bit floating point float2 and float4 | general operations | No | atomic addition | 9.0 | |
64-bit floating point | general operations | 1.3 | atomic addition | 6.0 |
Note: Any missing lines or empty entries do reflect some lack of information on that exact item. [59]
FMA per cycle per tensor core [60] | Supported since | 7.0 | 7.2 | 7.5 Workstation | 7.5 Desktop | 8.0 | 8.6 Workstation | 8.7 | 8.6 Desktop | 8.9 Desktop | 8.9 Workstation | 9.0 | 10.0 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Data Type | For dense matrices | For sparse matrices | 1st Gen (8x/SM) | 1st Gen? (8x/SM) | 2nd Gen (8x/SM) | 3rd Gen (4x/SM) | 4th Gen (4x/SM) | 5th Gen (4x/SM) | ||||||
1-bit values (AND) | 8.0 as experimental | No | No | 4096 | 2048 | speed tbd | ||||||||
1-bit values (XOR) | 7.5–8.9 as experimental | No | 1024 | Deprecated or removed? | ||||||||||
4-bit integers | 8.0–8.9 as experimental | 256 | 1024 | 512 | ||||||||||
4-bit floating point FP4 (E2M1?) | 10.0 | No | 4096 | |||||||||||
6-bit floating point FP6 (E3M2 and E2M3?) | 10.0 | No | 2048 | |||||||||||
8-bit integers | 7.2 | 8.0 | No | 128 | 128 | 512 | 256 | 1024 | 2048 | |||||
8-bit floating point FP8 (E4M3 and E5M2) with FP16 accumulate | 8.9 | No | 256 | |||||||||||
8-bit floating point FP8 (E4M3 and E5M2) with FP32 accumulate | ||||||||||||||
16-bit floating point FP16 with FP16 accumulate | 7.0 | 8.0 | 64 | 64 | 64 | 256 | 128 | 512 | 1024 | |||||
16-bit floating point FP16 with FP32 accumulate | 32 | 64 | 128 | |||||||||||
16-bit floating point BF16 with FP32 accumulate | 7.5 [61] | 8.0 | No | 64 [62] | ||||||||||
32-bit (19 bits used) floating point TF32 | speed tbd (32?) [63] | 128 | 32 | 64 | 256 | 512 | ||||||||
64-bit floating point | 8.0 | No | No | 16 | speed tbd | 32 | 16 |
Note: Any missing lines or empty entries do reflect some lack of information on that exact item. [64] [65] [66] [67] [68] [69]
Tensor Core Composition | 7.0 | 7.2, 7.5 | 8.0, 8.6 | 8.7 | 8.9 | 9.0 |
---|---|---|---|---|---|---|
Dot Product Unit Width in FP16 units (in bytes) [70] [71] [72] [73] | 4 (8) | 8 (16) | 4 (8) | 16 (32) | ||
Dot Product Units per Tensor Core | 16 | 32 | ||||
Tensor Cores per SM partition | 2 | 1 | ||||
Full throughput (Bytes/cycle) [74] per SM partition [75] | 256 | 512 | 256 | 1024 | ||
FP Tensor Cores: Minimum cycles for warp-wide matrix calculation | 8 | 4 | 8 | |||
FP Tensor Cores: Minimum Matrix Shape for full throughput (Bytes) [76] | 2048 | |||||
INT Tensor Cores: Minimum cycles for warp-wide matrix calculation | No | 4 | ||||
INT Tensor Cores: Minimum Matrix Shape for full throughput (Bytes) | No | 1024 | 2048 | 1024 |
FP64 Tensor Core Composition | 8.0 | 8.6 | 8.7 | 8.9 | 9.0 |
---|---|---|---|---|---|
Dot Product Unit Width in FP64 units (in bytes) | 4 (32) | tbd | 4 (32) | ||
Dot Product Units per Tensor Core | 4 | tbd | 8 | ||
Tensor Cores per SM partition | 1 | ||||
Full throughput (Bytes/cycle) [81] per SM partition [82] | 128 | tbd | 256 | ||
Minimum cycles for warp-wide matrix calculation | 16 | tbd | |||
Minimum Matrix Shape for full throughput (Bytes) [83] | 2048 |
Technical specifications | Compute capability (version) | ||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1.0 | 1.1 | 1.2 | 1.3 | 2.x | 3.0 | 3.2 | 3.5 | 3.7 | 5.0 | 5.2 | 5.3 | 6.0 | 6.1 | 6.2 | 7.0 | 7.2 | 7.5 | 8.0 | 8.6 | 8.7 | 8.9 | 9.0 | |
Maximum number of resident grids per device (concurrent kernel execution, can be lower for specific devices) | 1 | 16 | 4 | 32 | 16 | 128 | 32 | 16 | 128 | 16 | 128 | ||||||||||||
Maximum dimensionality of grid of thread blocks | 2 | 3 | |||||||||||||||||||||
Maximum x-dimension of a grid of thread blocks | 65535 | 231 − 1 | |||||||||||||||||||||
Maximum y-, or z-dimension of a grid of thread blocks | 65535 | ||||||||||||||||||||||
Maximum dimensionality of thread block | 3 | ||||||||||||||||||||||
Maximum x- or y-dimension of a block | 512 | 1024 | |||||||||||||||||||||
Maximum z-dimension of a block | 64 | ||||||||||||||||||||||
Maximum number of threads per block | 512 | 1024 | |||||||||||||||||||||
Warp size | 32 | ||||||||||||||||||||||
Maximum number of resident blocks per multiprocessor | 8 | 16 | 32 | 16 | 32 | 16 | 24 | 32 | |||||||||||||||
Maximum number of resident warps per multiprocessor | 24 | 32 | 48 | 64 | 32 | 64 | 48 | 64 | |||||||||||||||
Maximum number of resident threads per multiprocessor | 768 | 1024 | 1536 | 2048 | 1024 | 2048 | 1536 | 2048 | |||||||||||||||
Number of 32-bit regular registers per multiprocessor | 8 K | 16 K | 32 K | 64 K | 128 K | 64 K | |||||||||||||||||
Number of 32-bit uniform registers per multiprocessor | No | 2 K [84] | |||||||||||||||||||||
Maximum number of 32-bit registers per thread block | 8 K | 16 K | 32 K | 64 K | 32 K | 64 K | 32 K | 64 K | 32 K | 64 K | |||||||||||||
Maximum number of 32-bit regular registers per thread | 124 | 63 | 255 | ||||||||||||||||||||
Maximum number of 32-bit uniform registers per warp | No | 63 [86] | |||||||||||||||||||||
Amount of shared memory per multiprocessor (out of overall shared memory + L1 cache, where applicable) | 16 KiB | 16 / 48 KiB (of 64 KiB) | 16 / 32 / 48 KiB (of 64 KiB) | 80 / 96 / 112 KiB (of 128 KiB) | 64 KiB | 96 KiB | 64 KiB | 96 KiB | 64 KiB | 0 / 8 / 16 / 32 / 64 / 96 KiB (of 128 KiB) | 32 / 64 KiB (of 96 KiB) | 0 / 8 / 16 / 32 / 64 / 100 / 132 / 164 KiB (of 192 KiB) | 0 / 8 / 16 / 32 / 64 / 100 KiB (of 128 KiB) | 0 / 8 / 16 / 32 / 64 / 100 / 132 / 164 KiB (of 192 KiB) | 0 / 8 / 16 / 32 / 64 / 100 KiB (of 128 KiB) | 0 / 8 / 16 / 32 / 64 / 100 / 132 / 164 / 196 / 228 KiB (of 256 KiB) | |||||||
Maximum amount of shared memory per thread block | 16 KiB | 48 KiB | 96 KiB | 48 KiB | 64 KiB | 163 KiB | 99 KiB | 163 KiB | 99 KiB | 227 KiB | |||||||||||||
Number of shared memory banks | 16 | 32 | |||||||||||||||||||||
Amount of local memory per thread | 16 KiB | 512 KiB | |||||||||||||||||||||
Constant memory size accessible by CUDA C/C++ (1 bank, PTX can access 11 banks, SASS can access 18 banks) | 64 KiB | ||||||||||||||||||||||
Cache working set per multiprocessor for constant memory | 8 KiB | 4 KiB | 8 KiB | ||||||||||||||||||||
Cache working set per multiprocessor for texture memory | 16 KiB per TPC | 24 KiB per TPC | 12 KiB | 12 – 48 KiB [88] | 24 KiB | 48 KiB | 32 KiB [89] | 24 KiB | 48 KiB | 24 KiB | 32 – 128 KiB | 32 – 64 KiB | 28 – 192 KiB | 28 – 128 KiB | 28 – 192 KiB | 28 – 128 KiB | 28 – 256 KiB | ||||||
Maximum width for 1D texture reference bound to a CUDA array | 8192 | 65536 | 131072 | ||||||||||||||||||||
Maximum width for 1D texture reference bound to linear memory | 227 | 228 | 227 | 228 | 227 | 228 | |||||||||||||||||
Maximum width and number of layers for a 1D layered texture reference | 8192 × 512 | 16384 × 2048 | 32768 x 2048 | ||||||||||||||||||||
Maximum width and height for 2D texture reference bound to a CUDA array | 65536 × 32768 | 65536 × 65535 | 131072 x 65536 | ||||||||||||||||||||
Maximum width and height for 2D texture reference bound to a linear memory | 65000 x 65000 | 65536 x 65536 | 131072 x 65000 | ||||||||||||||||||||
Maximum width and height for 2D texture reference bound to a CUDA array supporting texture gather | — | 16384 x 16384 | 32768 x 32768 | ||||||||||||||||||||
Maximum width, height, and number of layers for a 2D layered texture reference | 8192 × 8192 × 512 | 16384 × 16384 × 2048 | 32768 x 32768 x 2048 | ||||||||||||||||||||
Maximum width, height and depth for a 3D texture reference bound to linear memory or a CUDA array | 20483 | 40963 | 163843 | ||||||||||||||||||||
Maximum width (and height) for a cubemap texture reference | — | 16384 | 32768 | ||||||||||||||||||||
Maximum width (and height) and number of layers for a cubemap layered texture reference | — | 16384 × 2046 | 32768 × 2046 | ||||||||||||||||||||
Maximum number of textures that can be bound to a kernel | 128 | 256 | |||||||||||||||||||||
Maximum width for a 1D surface reference bound to a CUDA array | Not supported | 65536 | 16384 | 32768 | |||||||||||||||||||
Maximum width and number of layers for a 1D layered surface reference | 65536 × 2048 | 16384 × 2048 | 32768 × 2048 | ||||||||||||||||||||
Maximum width and height for a 2D surface reference bound to a CUDA array | 65536 × 32768 | 16384 × 65536 | 131072 × 65536 | ||||||||||||||||||||
Maximum width, height, and number of layers for a 2D layered surface reference | 65536 × 32768 × 2048 | 16384 × 16384 × 2048 | 32768 × 32768 × 2048 | ||||||||||||||||||||
Maximum width, height, and depth for a 3D surface reference bound to a CUDA array | 65536 × 32768 × 2048 | 4096 × 4096 × 4096 | 16384 × 16384 × 16384 | ||||||||||||||||||||
Maximum width (and height) for a cubemap surface reference bound to a CUDA array | 32768 | 16384 | 32768 | ||||||||||||||||||||
Maximum width and number of layers for a cubemap layered surface reference | 32768 × 2046 | 16384 × 2046 | 32768 × 2046 | ||||||||||||||||||||
Maximum number of surfaces that can be bound to a kernel | 8 | 16 | 32 | ||||||||||||||||||||
Maximum number of instructions per kernel | 2 million | 512 million | |||||||||||||||||||||
Maximum number of Thread Blocks per Thread Block Cluster [90] | No | 16 | |||||||||||||||||||||
Technical specifications | 1.0 | 1.1 | 1.2 | 1.3 | 2.x | 3.0 | 3.2 | 3.5 | 3.7 | 5.0 | 5.2 | 5.3 | 6.0 | 6.1 | 6.2 | 7.0 | 7.2 | 7.5 | 8.0 | 8.6 | 8.7 | 8.9 | 9.0 |
Compute capability (version) |
Architecture specifications | Compute capability (version) | |||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1.0 | 1.1 | 1.2 | 1.3 | 2.0 | 2.1 | 3.0 | 3.2 | 3.5 | 3.7 | 5.0 | 5.2 | 5.3 | 6.0 | 6.1 | 6.2 | 7.0 | 7.2 | 7.5 | 8.0 | 8.6 | 8.7 | 8.9 | 9.0 | |
Number of ALU lanes for INT32 arithmetic operations | 8 | 32 | 48 | 192 [93] | 128 | 128 | 64 | 128 | 128 | 64 | 64 | 64 | ||||||||||||
Number of ALU lanes for any INT32 or FP32 arithmetic operation | — | — | ||||||||||||||||||||||
Number of ALU lanes for FP32 arithmetic operations | 64 | 64 | 128 | 128 | ||||||||||||||||||||
Number of ALU lanes for FP16x2 arithmetic operations | No | 1 | 128 [94] | 128 [95] | 64 [96] | |||||||||||||||||||
Number of ALU lanes for FP64 arithmetic operations | No | 1 | 16 by FP32 [97] | 4 by FP32 [98] | 8 | 8 / 64 [99] | 64 | 4 [100] | 32 | 4 | 32 | 2 | 32 | 2 | 2? | 2 | 64 | |||||||
Number of Load/Store Units | 4 per 2 SM | 8 per 2 SM | 8 per 2 SM / 3 SM [99] | 8 per 3 SM | 16 | 32 | 16 | 32 | 16 | 32 | ||||||||||||||
Number of special function units for single-precision floating-point transcendental functions | 2 [101] | 4 | 8 | 32 | 16 | 32 | 16 | |||||||||||||||||
Number of texture mapping units (TMU) | 4 per 2 SM | 8 per 2 SM | 8 per 2 / 3SM [99] | 8 per 3 SM | 4 | 4 / 8 [99] | 16 | 8 | 16 | 8 | 4 | |||||||||||||
Number of ALU lanes for uniform INT32 arithmetic operations | No | 2 [102] | ||||||||||||||||||||||
Number of tensor cores | No | 8 (1st gen.) [103] | 0 / 8 [99] (2nd gen.) | 4 (3rd gen.) | 4 (4th gen.) | |||||||||||||||||||
Number of raytracing cores | No | 0 / 1 [99] (1st gen.) | No | 1 (2nd gen.) | No | 1 (3rd gen.) | No | |||||||||||||||||
Number of SM Partitions = Processing Blocks [104] | 1 | 4 | 2 | 4 | ||||||||||||||||||||
Number of warp schedulers per SM partition | 1 | 2 | 4 | 1 | ||||||||||||||||||||
Max number of new instructions issued each cycle by a single scheduler [105] | 2 [106] | 1 | 2 [107] | 2 | 1 | |||||||||||||||||||
Size of unified memory for data cache and shared memory | 16 KiB [108] | 16 KiB [108] | 64 KiB | 128 KiB | 64 KiB SM + 24 KiB L1 (separate) [109] | 96 KiB SM + 24 KiB L1 (separate) [109] | 64 KiB SM + 24 KiB L1 (separate) [109] | 64 KiB SM + 24 KiB L1 (separate) [109] | 96 KiB SM + 24 KiB L1 (separate) [109] | 64 KiB SM + 24 KiB L1 (separate) [109] | 128 KiB | 96 KiB [110] | 192 KiB | 128 KiB | 192 KiB | 128 KiB | 256 KiB | |||||||
Size of L3 instruction cache per GPU | 32 KiB [111] | use L2 Data Cache | ||||||||||||||||||||||
Size of L2 instruction cache per Texture Processor Cluster (TPC) | 8 KiB | |||||||||||||||||||||||
Size of L1.5 instruction cache per SM [112] | 4 KiB | 32 KiB | 32 KiB | 48 KiB [113] | 128 KiB | 32 KiB | 128 KiB | ~46 KiB [114] | 128 KiB [115] | |||||||||||||||
Size of L1 instruction cache per SM | 8 KiB | 8 KiB | ||||||||||||||||||||||
Size of L0 instruction cache per SM partition | only 1 partition per SM | No | 12 KiB | 16 KiB? [116] | 32 KiB | |||||||||||||||||||
Instruction Width [117] | 32 bits instructions and 64 bits instructions [118] | 64 bits instructions + 64 bits control logic every 7 instructions | 64 bits instructions + 64 bits control logic every 3 instructions | 128 bits combined instruction and control logic | ||||||||||||||||||||
Memory Bus Width per Memory Partition in bits | 64 ((G)DDR) | 32 ((G)DDR) | 512 (HBM) | 32 ((G)DDR) | 512 (HBM) | 32 ((G)DDR) | 512 (HBM) | 32 ((G)DDR) | 512 (HBM) | |||||||||||||||
L2 Cache per Memory Partition | 16 KiB [119] | 32 KiB [119] | 128 KiB | 256 KiB | 1 MiB | 512 KiB | 128 KiB | 512 KiB | 256 KiB | 128 KiB | 768 KiB | 64 KiB | 512 KiB | 4 MiB | 512 KiB | 8 MiB [120] | 5 MiB | |||||||
Number of Render Output Units (ROP) per memory partition (or per GPC in later models) | 4 | 8 | 4 | 8 | 16 | 8 | 12 | 8 | 4 | 16 | 2 | 8 | 16 | 16 per GPC | 3 per GPC | 16 per GPC | ||||||||
Architecture specifications | 1.0 | 1.1 | 1.2 | 1.3 | 2.0 | 2.1 | 3.0 | 3.2 | 3.5 | 3.7 | 5.0 | 5.2 | 5.3 | 6.0 | 6.1 | 6.2 | 7.0 | 7.2 | 7.5 | 8.0 | 8.6 | 8.7 | 8.9 | 9.0 |
Compute capability (version) |
For more information read the Nvidia CUDA programming guide. [122]
CUDA competes with other GPU computing stacks: Intel OneAPI and AMD ROCm.
Whereas Nvidia's CUDA is closed-source, Intel's OneAPI and AMD's ROCm are open source.
oneAPI is an initiative based in open standards, created to support software development for multiple hardware architectures. [125] The oneAPI libraries must implement open specifications that are discussed publicly by the Special Interest Groups, offering the possibility for any developer or organization to implement their own versions of oneAPI libraries. [126] [127]
Originally made by Intel, other hardware adopters include Fujitsu and Huawei.
Unified Acceleration Foundation (UXL) is a new technology consortium working on the continuation of the OneAPI initiative, with the goal to create a new open standard accelerator software ecosystem, related open standards and specification projects through Working Groups and Special Interest Groups (SIGs). The goal is to offer open alternatives to Nvidia's CUDA. The main companies behind it are Intel, Google, ARM, Qualcomm, Samsung, Imagination, and VMware. [128]
ROCm [129] is an open source software stack for graphics processing unit (GPU) programming from Advanced Micro Devices (AMD).
A graphics processing unit (GPU) is a specialized electronic circuit initially designed for digital image processing and to accelerate computer graphics, being present either as a discrete video card or embedded on motherboards, mobile phones, personal computers, workstations, and game consoles. After their initial design, GPUs were found to be useful for non-graphic calculations involving embarrassingly parallel problems due to their parallel structure. Other non-graphical uses include the training of neural networks and cryptocurrency mining.
General-purpose computing on graphics processing units is the use of a graphics processing unit (GPU), which typically handles computation only for computer graphics, to perform computation in applications traditionally handled by the central processing unit (CPU). The use of multiple video cards in one computer, or large numbers of graphics chips, further parallelizes the already parallel nature of graphics processing.
Quadro was Nvidia's brand for graphics cards intended for use in workstations running professional computer-aided design (CAD), computer-generated imagery (CGI), digital content creation (DCC) applications, scientific calculations and machine learning from 2000 to 2020.
nouveau is a free and open-source graphics device driver for Nvidia video cards and the Tegra family of SoCs written by independent software engineers, with minor help from Nvidia employees.
In computing, Close To Metal is the name of a beta version of a low-level programming interface developed by ATI, now the AMD Graphics Product Group, aimed at enabling GPGPU computing. CTM was short-lived, and the first production version of AMD's GPGPU technology is now called AMD Stream SDK, or rather the current AMD APP SDK ) for Windows and Linux 32-bit and 64-bit, which also targets Heterogeneous System Architecture.
In the field of 3D computer graphics, the unified shader model refers to a form of shader hardware in a graphical processing unit (GPU) where all of the shader stages in the rendering pipeline have the same capabilities. They can all read textures and buffers, and they use instruction sets that are almost identical.
AMD FireStream was AMD's brand name for their Radeon-based product line targeting stream processing and/or GPGPU in supercomputers. Originally developed by ATI Technologies around the Radeon X1900 XTX in 2006, the product line was previously branded as both ATI FireSTREAM and AMD Stream Processor. The AMD FireStream can also be used as a floating-point co-processor for offloading CPU calculations, which is part of the Torrenza initiative. The FireStream line has been discontinued since 2012, when GPGPU workloads were entirely folded into the AMD FirePro line.
OpenCL is a framework for writing programs that execute across heterogeneous platforms consisting of central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs) and other processors or hardware accelerators. OpenCL specifies a programming language for programming these devices and application programming interfaces (APIs) to control the platform and execute programs on the compute devices. OpenCL provides a standard interface for parallel computing using task- and data-based parallelism.
Graphics Core Next (GCN) is the codename for a series of microarchitectures and an instruction set architecture that were developed by AMD for its GPUs as the successor to its TeraScale microarchitecture. The first product featuring GCN was launched on January 9, 2012.
GPULib is discontinued and unsupported software library developed by Tech-X Corporation for accelerating general-purpose scientific computations from within the Interactive Data Language (IDL) using Nvidia's CUDA platform for programming its graphics processing units (GPUs). GPULib provides basic arithmetic, array indexing, special functions, Fast Fourier Transforms (FFT), interpolation, BLAS matrix operations as well as LAPACK routines provided by MAGMA, and some image processing operations. All numeric data types provided by IDL are supported. GPULib is used in medical imaging, optics, astronomy, earth science, remote sensing, and other scientific areas.
Pascal is the codename for a GPU microarchitecture developed by Nvidia, as the successor to the Maxwell architecture. The architecture was first introduced in April 2016 with the release of the Tesla P100 (GP100) on April 5, 2016, and is primarily used in the GeForce 10 series, starting with the GeForce GTX 1080 and GTX 1070, which were released on May 27, 2016, and June 10, 2016, respectively. Pascal was manufactured using TSMC's 16 nm FinFET process, and later Samsung's 14 nm FinFET process.
Volta is the codename, but not the trademark, for a GPU microarchitecture developed by Nvidia, succeeding Pascal. It was first announced on a roadmap in March 2013, although the first product was not announced until May 2017. The architecture is named after 18th–19th century Italian chemist and physicist Alessandro Volta. It was Nvidia's first chip to feature Tensor Cores, specially designed cores that have superior deep learning performance over regular CUDA cores. The architecture is produced with TSMC's 12 nm FinFET process. The Ampere microarchitecture is the successor to Volta.
Metal is a low-level, low-overhead hardware-accelerated 3D graphic and compute shader API created by Apple, debuting in iOS 8. Metal combines functions similar to OpenGL and OpenCL in one API. It is intended to improve performance by offering low-level access to the GPU hardware for apps on iOS, iPadOS, macOS, and tvOS. It can be compared to low-level APIs on other platforms such as Vulkan and DirectX 12.
GPUOpen is a middleware software suite originally developed by AMD's Radeon Technologies Group that offers advanced visual effects for computer games. It was released in 2016. GPUOpen serves as an alternative to, and a direct competitor of Nvidia GameWorks. GPUOpen is similar to GameWorks in that it encompasses several different graphics technologies as its main components that were previously independent and separate from one another. However, GPUOpen is partially open source software, unlike GameWorks which is proprietary and closed.
SYCL is a higher-level programming model to improve programming productivity on various hardware accelerators. It is a single-source embedded domain-specific language (eDSL) based on pure C++17. It is a standard developed by Khronos Group, announced in March 2014.
AMD Instinct is AMD's brand of data center GPUs. It replaced AMD's FirePro S brand in 2016. Compared to the Radeon brand of mainstream consumer/gamer products, the Instinct product line is intended to accelerate deep learning, artificial neural network, and high-performance computing/GPGPU applications.
ROCm is an Advanced Micro Devices (AMD) software stack for graphics processing unit (GPU) programming. ROCm spans several domains: general-purpose computing on graphics processing units (GPGPU), high performance computing (HPC), heterogeneous computing. It offers several programming models: HIP, OpenMP, and OpenCL.
Ampere is the codename for a graphics processing unit (GPU) microarchitecture developed by Nvidia as the successor to both the Volta and Turing architectures. It was officially announced on May 14, 2020 and is named after French mathematician and physicist André-Marie Ampère.
oneAPI is an open standard, adopted by Intel, for a unified application programming interface (API) intended to be used across different computing accelerator (coprocessor) architectures, including GPUs, AI accelerators and field-programmable gate arrays. It is intended to eliminate the need for developers to maintain separate code bases, multiple programming languages, tools, and workflows for each architecture.
CuPy is an open source library for GPU-accelerated computing with Python programming language, providing support for multi-dimensional arrays, sparse matrices, and a variety of numerical algorithms implemented on top of them. CuPy shares the same API set as NumPy and SciPy, allowing it to be a drop-in replacement to run NumPy/SciPy code on GPU. CuPy supports Nvidia CUDA GPU platform, and AMD ROCm GPU platform starting in v9.0.