CUDA

Last updated
CUDA
Developer(s) Nvidia
Initial releaseJune 23, 2007;17 years ago (2007-06-23)
Stable release
12.6 / August 2024;3 months ago (2024-08)
Operating system Windows, Linux
Platform Supported GPUs
Type GPGPU
License Proprietary
Website developer.nvidia.com/cuda-zone

In computing, CUDA (originally Compute Unified Device Architecture) is a proprietary [1] parallel computing platform and application programming interface (API) that allows software to use certain types of graphics processing units (GPUs) for accelerated general-purpose processing, an approach called general-purpose computing on GPUs (GPGPU). CUDA API and its runtime: The CUDA API is an extension of the C programming language that adds the ability to specify thread-level parallelism in C and also to specify GPU device specific operations (like moving data between the CPU and the GPU). [2] CUDA is a software layer that gives direct access to the GPU's virtual instruction set and parallel computational elements for the execution of compute kernels. [3] In addition to drivers and runtime kernels, the CUDA platform includes compilers, libraries and developer tools to help programmers accelerate their applications.

Contents

CUDA is designed to work with programming languages such as C, C++, Fortran and Python. This accessibility makes it easier for specialists in parallel programming to use GPU resources, in contrast to prior APIs like Direct3D and OpenGL, which require advanced skills in graphics programming. [4] CUDA-powered GPUs also support programming frameworks such as OpenMP, OpenACC and OpenCL. [5] [3]

CUDA was created by Nvidia in 2006. [6] When it was first introduced, the name was an acronym for Compute Unified Device Architecture, [7] but Nvidia later dropped the common use of the acronym and now rarely expands it. [8]

Background

The graphics processing unit (GPU), as a specialized computer processor, addresses the demands of real-time high-resolution 3D graphics compute-intensive tasks. By 2012, GPUs had evolved into highly parallel multi-core systems allowing efficient manipulation of large blocks of data. This design is more effective than general-purpose central processing unit (CPUs) for algorithms in situations where processing large blocks of data is done in parallel, such as:

Ian Buck, while at Stanford in 2000, created an 8K gaming rig using 32 GeForce cards, then obtained a DARPA grant to perform general purpose parallel programming on GPUs. He then joined Nvidia, where since 2004 he has been overseeing CUDA development. In pushing for CUDA, Jensen Huang aimed for the Nvidia GPUs to become a general hardware for scientific computing. CUDA was released in 2006. Around 2015, the focus of CUDA changed to neural networks. [9]

Ontology

The following table offers a non-exact description for the ontology of CUDA framework.

The ontology of CUDA framework
memory
(hardware)
memory (code, or variable scoping)computation
(hardware)
computation
(code syntax)
computation
(code semantics)
RAM non-CUDA variableshostprogramone routine call
VRAM,
GPU L2 cache
global, const, texturedevicegridsimultaneous call of the same subroutine on many processors
GPU L1 cachelocal, sharedSM ("streaming multiprocessor")blockindividual subroutine call
warp = 32 threads SIMD instructions
GPU L0 cache,
register
thread (aka. "SP", "streaming processor", "cuda core", but these names are now deprecated)analogous to individual scalar ops within a vector op

Programming abilities

Example of CUDA processing flow
Copy data from main memory to GPU memory
CPU initiates the GPU compute kernel
GPU's CUDA cores execute the kernel in parallel
Copy the resulting data from GPU memory to main memory CUDA processing flow (En).PNG
Example of CUDA processing flow
  1. Copy data from main memory to GPU memory
  2. CPU initiates the GPU compute kernel
  3. GPU's CUDA cores execute the kernel in parallel
  4. Copy the resulting data from GPU memory to main memory

The CUDA platform is accessible to software developers through CUDA-accelerated libraries, compiler directives such as OpenACC, and extensions to industry-standard programming languages including C, C++, Fortran and Python. C/C++ programmers can use 'CUDA C/C++', compiled to PTX with nvcc, Nvidia's LLVM-based C/C++ compiler, or by clang itself. [10] Fortran programmers can use 'CUDA Fortran', compiled with the PGI CUDA Fortran compiler from The Portland Group.[ needs update ] Python programmers can use the cuNumeric library to accelerate applications on Nvidia GPUs.

In addition to libraries, compiler directives, CUDA C/C++ and CUDA Fortran, the CUDA platform supports other computational interfaces, including the Khronos Group's OpenCL, [11] Microsoft's DirectCompute, OpenGL Compute Shader and C++ AMP. [12] Third party wrappers are also available for Python, Perl, Fortran, Java, Ruby, Lua, Common Lisp, Haskell, R, MATLAB, IDL, Julia, and native support in Mathematica.

In the computer game industry, GPUs are used for graphics rendering, and for game physics calculations (physical effects such as debris, smoke, fire, fluids); examples include PhysX and Bullet. CUDA has also been used to accelerate non-graphical applications in computational biology, cryptography and other fields by an order of magnitude or more. [13] [14] [15] [16] [17]

CUDA provides both a low level API (CUDA Driver API, non single-source) and a higher level API (CUDA Runtime API, single-source). The initial CUDA SDK was made public on 15 February 2007, for Microsoft Windows and Linux. Mac OS X support was later added in version 2.0, [18] which supersedes the beta released February 14, 2008. [19] CUDA works with all Nvidia GPUs from the G8x series onwards, including GeForce, Quadro and the Tesla line. CUDA is compatible with most standard operating systems.

CUDA 8.0 comes with the following libraries (for compilation & runtime, in alphabetical order):

CUDA 8.0 comes with these other software components:

CUDA 9.0–9.2 comes with these other components:

CUDA 10 comes with these other components:

CUDA 11.0–11.8 comes with these other components: [20] [21] [22] [23]

Advantages

CUDA has several advantages over traditional general-purpose computation on GPUs (GPGPU) using graphics APIs:

Limitations

Example

This example code in C++ loads a texture from an image into an array on the GPU:

texture<float,2,cudaReadModeElementType>tex;voidfoo(){cudaArray*cu_array;// Allocate arraycudaChannelFormatDescdescription=cudaCreateChannelDesc<float>();cudaMallocArray(&cu_array,&description,width,height);// Copy image data to arraycudaMemcpyToArray(cu_array,image,width*height*sizeof(float),cudaMemcpyHostToDevice);// Set texture parameters (default)tex.addressMode[0]=cudaAddressModeClamp;tex.addressMode[1]=cudaAddressModeClamp;tex.filterMode=cudaFilterModePoint;tex.normalized=false;// do not normalize coordinates// Bind the array to the texturecudaBindTextureToArray(tex,cu_array);// Run kerneldim3blockDim(16,16,1);dim3gridDim((width+blockDim.x-1)/blockDim.x,(height+blockDim.y-1)/blockDim.y,1);kernel<<<gridDim,blockDim,0>>>(d_data,height,width);// Unbind the array from the texturecudaUnbindTexture(tex);}//end foo()__global__voidkernel(float*odata,intheight,intwidth){unsignedintx=blockIdx.x*blockDim.x+threadIdx.x;unsignedinty=blockIdx.y*blockDim.y+threadIdx.y;if(x<width&&y<height){floatc=tex2D(tex,x,y);odata[y*width+x]=c;}}

Below is an example given in Python that computes the product of two arrays on the GPU. The unofficial Python language bindings can be obtained from PyCUDA. [36]

importpycuda.compilerascompimportpycuda.driverasdrvimportnumpyimportpycuda.autoinitmod=comp.SourceModule("""__global__ void multiply_them(float *dest, float *a, float *b){  const int i = threadIdx.x;  dest[i] = a[i] * b[i];}""")multiply_them=mod.get_function("multiply_them")a=numpy.random.randn(400).astype(numpy.float32)b=numpy.random.randn(400).astype(numpy.float32)dest=numpy.zeros_like(a)multiply_them(drv.Out(dest),drv.In(a),drv.In(b),block=(400,1,1))print(dest-a*b)

Additional Python bindings to simplify matrix multiplication operations can be found in the program pycublas. [37]

importnumpyfrompycublasimportCUBLASMatrixA=CUBLASMatrix(numpy.mat([[1,2,3],[4,5,6]],numpy.float32))B=CUBLASMatrix(numpy.mat([[2,3],[4,5],[6,7]],numpy.float32))C=A*Bprint(C.np_mat())

while CuPy directly replaces NumPy: [38]

importcupya=cupy.random.randn(400)b=cupy.random.randn(400)dest=cupy.zeros_like(a)print(dest-a*b)

GPUs supported

Supported CUDA Compute Capability versions for CUDA SDK version and Microarchitecture (by code name):

Compute Capability (CUDA SDK support vs. Microarchitecture)
CUDA SDK
Version(s)
Tesla Fermi Kepler
(Early)
Kepler
(Late)
Maxwell Pascal Volta Turing Ampere Ada
Lovelace
Hopper Blackwell
1.0 [39] 1.0 – 1.1
1.11.0 – 1.1+x
2.01.0 – 1.1+x
2.1 – 2.3.1 [40] [41] [42] [43] 1.0 – 1.3
3.0 – 3.1 [44] [45] 1.02.0
3.2 [46] 1.02.1
4.0 – 4.21.02.1
5.0 – 5.51.03.5
6.01.03.23.5
6.51.13.75.x
7.0 – 7.52.05.x
8.02.06.x
9.0 – 9.23.07.0 – 7.2
10.0 – 10.23.07.5
11.0 [47] 3.58.0
11.1 – 11.4 [48] 3.58.6
11.5 – 11.7.1 [49] 3.58.7
11.8 [50] 3.58.99.0
12.0 – 12.55.09.0

Note: CUDA SDK 10.2 is the last official release for macOS, as support will not be available for macOS in newer releases.

CUDA Compute Capability by version with associated GPU semiconductors and GPU card models (separated by their various application areas):

Compute Capability, GPU semiconductors and Nvidia GPU board products
Compute
capability
(version)
Micro-
architecture
GPUs GeForce Quadro, NVS Tesla/Datacenter Tegra,
Jetson,
DRIVE
1.0 Tesla G80GeForce 8800 Ultra, GeForce 8800 GTX, GeForce 8800 GTS(G80)Quadro FX 5600, Quadro FX 4600, Quadro Plex 2100 S4Tesla C870, Tesla D870, Tesla S870
1.1G92, G94, G96, G98, G84, G86GeForce GTS 250, GeForce 9800 GX2, GeForce 9800 GTX, GeForce 9800 GT, GeForce 8800 GTS(G92), GeForce 8800 GT, GeForce 9600 GT, GeForce 9500 GT, GeForce 9400 GT, GeForce 8600 GTS, GeForce 8600 GT, GeForce 8500 GT,
GeForce G110M, GeForce 9300M GS, GeForce 9200M GS, GeForce 9100M G, GeForce 8400M GT, GeForce G105M
Quadro FX 4700 X2, Quadro FX 3700, Quadro FX 1800, Quadro FX 1700, Quadro FX 580, Quadro FX 570, Quadro FX 470, Quadro FX 380, Quadro FX 370, Quadro FX 370 Low Profile, Quadro NVS 450, Quadro NVS 420, Quadro NVS 290, Quadro NVS 295, Quadro Plex 2100 D4,
Quadro FX 3800M, Quadro FX 3700M, Quadro FX 3600M, Quadro FX 2800M, Quadro FX 2700M, Quadro FX 1700M, Quadro FX 1600M, Quadro FX 770M, Quadro FX 570M, Quadro FX 370M, Quadro FX 360M, Quadro NVS 320M, Quadro NVS 160M, Quadro NVS 150M, Quadro NVS 140M, Quadro NVS 135M, Quadro NVS 130M, Quadro NVS 450, Quadro NVS 420, [51] Quadro NVS 295
1.2GT218, GT216, GT215GeForce GT 340*, GeForce GT 330*, GeForce GT 320*, GeForce 315*, GeForce 310*, GeForce GT 240, GeForce GT 220, GeForce 210,
GeForce GTS 360M, GeForce GTS 350M, GeForce GT 335M, GeForce GT 330M, GeForce GT 325M, GeForce GT 240M, GeForce G210M, GeForce 310M, GeForce 305M
Quadro FX 380 Low Profile, Quadro FX 1800M, Quadro FX 880M, Quadro FX 380M,
Nvidia NVS 300, NVS 5100M, NVS 3100M, NVS 2100M, ION
1.3GT200, GT200bGeForce GTX 295, GTX 285, GTX 280, GeForce GTX 275, GeForce GTX 260Quadro FX 5800, Quadro FX 4800, Quadro FX 4800 for Mac, Quadro FX 3800, Quadro CX, Quadro Plex 2200 D2Tesla C1060, Tesla S1070, Tesla M1060
2.0 Fermi GF100, GF110GeForce GTX 590, GeForce GTX 580, GeForce GTX 570, GeForce GTX 480, GeForce GTX 470, GeForce GTX 465,
GeForce GTX 480M
Quadro 6000, Quadro 5000, Quadro 4000, Quadro 4000 for Mac, Quadro Plex 7000,
Quadro 5010M, Quadro 5000M
Tesla C2075, Tesla C2050/C2070, Tesla M2050/M2070/M2075/M2090
2.1GF104, GF106 GF108, GF114, GF116, GF117, GF119GeForce GTX 560 Ti, GeForce GTX 550 Ti, GeForce GTX 460, GeForce GTS 450, GeForce GTS 450*, GeForce GT 640 (GDDR3), GeForce GT 630, GeForce GT 620, GeForce GT 610, GeForce GT 520, GeForce GT 440, GeForce GT 440*, GeForce GT 430, GeForce GT 430*, GeForce GT 420*,
GeForce GTX 675M, GeForce GTX 670M, GeForce GT 635M, GeForce GT 630M, GeForce GT 625M, GeForce GT 720M, GeForce GT 620M, GeForce 710M, GeForce 610M, GeForce 820M, GeForce GTX 580M, GeForce GTX 570M, GeForce GTX 560M, GeForce GT 555M, GeForce GT 550M, GeForce GT 540M, GeForce GT 525M, GeForce GT 520MX, GeForce GT 520M, GeForce GTX 485M, GeForce GTX 470M, GeForce GTX 460M, GeForce GT 445M, GeForce GT 435M, GeForce GT 420M, GeForce GT 415M, GeForce 710M, GeForce 410M
Quadro 2000, Quadro 2000D, Quadro 600,
Quadro 4000M, Quadro 3000M, Quadro 2000M, Quadro 1000M,
NVS 310, NVS 315, NVS 5400M, NVS 5200M, NVS 4200M
3.0 Kepler GK104, GK106, GK107GeForce GTX 770, GeForce GTX 760, GeForce GT 740, GeForce GTX 690, GeForce GTX 680, GeForce GTX 670, GeForce GTX 660 Ti, GeForce GTX 660, GeForce GTX 650 Ti BOOST, GeForce GTX 650 Ti, GeForce GTX 650,
GeForce GTX 880M, GeForce GTX 870M, GeForce GTX 780M, GeForce GTX 770M, GeForce GTX 765M, GeForce GTX 760M, GeForce GTX 680MX, GeForce GTX 680M, GeForce GTX 675MX, GeForce GTX 670MX, GeForce GTX 660M, GeForce GT 750M, GeForce GT 650M, GeForce GT 745M, GeForce GT 645M, GeForce GT 740M, GeForce GT 730M, GeForce GT 640M, GeForce GT 640M LE, GeForce GT 735M, GeForce GT 730M
Quadro K5000, Quadro K4200, Quadro K4000, Quadro K2000, Quadro K2000D, Quadro K600, Quadro K420,
Quadro K500M, Quadro K510M, Quadro K610M, Quadro K1000M, Quadro K2000M, Quadro K1100M, Quadro K2100M, Quadro K3000M, Quadro K3100M, Quadro K4000M, Quadro K5000M, Quadro K4100M, Quadro K5100M,
NVS 510, Quadro 410
Tesla K10, GRID K340, GRID K520, GRID K2
3.2GK20ATegra K1,
Jetson TK1
3.5GK110, GK208GeForce GTX Titan Z, GeForce GTX Titan Black, GeForce GTX Titan, GeForce GTX 780 Ti, GeForce GTX 780, GeForce GT 640 (GDDR5), GeForce GT 630 v2, GeForce GT 730, GeForce GT 720, GeForce GT 710, GeForce GT 740M (64-bit, DDR3), GeForce GT 920MQuadro K6000, Quadro K5200Tesla K40, Tesla K20x, Tesla K20
3.7GK210Tesla K80
5.0 Maxwell GM107, GM108GeForce GTX 750 Ti, GeForce GTX 750, GeForce GTX 960M, GeForce GTX 950M, GeForce 940M, GeForce 930M, GeForce GTX 860M, GeForce GTX 850M, GeForce 845M, GeForce 840M, GeForce 830MQuadro K1200, Quadro K2200, Quadro K620, Quadro M2000M, Quadro M1000M, Quadro M600M, Quadro K620M, NVS 810Tesla M10
5.2GM200, GM204, GM206GeForce GTX Titan X, GeForce GTX 980 Ti, GeForce GTX 980, GeForce GTX 970, GeForce GTX 960, GeForce GTX 950, GeForce GTX 750 SE,
GeForce GTX 980M, GeForce GTX 970M, GeForce GTX 965M
Quadro M6000 24GB, Quadro M6000, Quadro M5000, Quadro M4000, Quadro M2000, Quadro M5500,
Quadro M5000M, Quadro M4000M, Quadro M3000M
Tesla M4, Tesla M40, Tesla M6, Tesla M60
5.3GM20BTegra X1,
Jetson TX1,
Jetson Nano,
DRIVE CX,
DRIVE PX
6.0 Pascal GP100Quadro GP100Tesla P100
6.1GP102, GP104, GP106, GP107, GP108Nvidia TITAN Xp, Titan X,
GeForce GTX 1080 Ti, GTX 1080, GTX 1070 Ti, GTX 1070, GTX 1060,
GTX 1050 Ti, GTX 1050, GT 1030, GT 1010,
MX350, MX330, MX250, MX230, MX150, MX130, MX110
Quadro P6000, Quadro P5000, Quadro P4000, Quadro P2200, Quadro P2000, Quadro P1000, Quadro P400, Quadro P500, Quadro P520, Quadro P600,
Quadro P5000(Mobile), Quadro P4000(Mobile), Quadro P3000(Mobile)
Tesla P40, Tesla P6, Tesla P4
6.2GP10B [52] Tegra X2, Jetson TX2, DRIVE PX 2
7.0 Volta GV100NVIDIA TITAN VQuadro GV100Tesla V100, Tesla V100S
7.2GV10B [53]

GV11B [54] [55]

Tegra Xavier,
Jetson Xavier NX,
Jetson AGX Xavier,
DRIVE AGX Xavier,
DRIVE AGX Pegasus,
Clara AGX
7.5 Turing TU102, TU104, TU106, TU116, TU117NVIDIA TITAN RTX,
GeForce RTX 2080 Ti, RTX 2080 Super, RTX 2080, RTX 2070 Super, RTX 2070, RTX 2060 Super, RTX 2060 12GB, RTX 2060,
GeForce GTX 1660 Ti, GTX 1660 Super, GTX 1660, GTX 1650 Super, GTX 1650, MX550, MX450
Quadro RTX 8000, Quadro RTX 6000, Quadro RTX 5000, Quadro RTX 4000, T1000, T600, T400
T1200(mobile), T600(mobile), T500(mobile), Quadro T2000(mobile), Quadro T1000(mobile)
Tesla T4
8.0 Ampere GA100A100 80GB, A100 40GB, A30
8.6GA102, GA103, GA104, GA106, GA107GeForce RTX 3090 Ti, RTX 3090, RTX 3080 Ti, RTX 3080 12GB, RTX 3080, RTX 3070 Ti, RTX 3070, RTX 3060 Ti, RTX 3060, RTX 3050, RTX 3050 Ti(mobile), RTX 3050(mobile), RTX 2050(mobile), MX570RTX A6000, RTX A5500, RTX A5000, RTX A4500, RTX A4000, RTX A2000
RTX A5000(mobile), RTX A4000(mobile), RTX A3000(mobile), RTX A2000(mobile)
A40, A16, A10, A2
8.7GA10BJetson Orin Nano,
Jetson Orin NX,
Jetson AGX Orin,
DRIVE AGX Orin,
DRIVE AGX Pegasus OA,
Clara Holoscan
8.9 Ada Lovelace [56] AD102, AD103, AD104, AD106, AD107GeForce RTX 4090, RTX 4080 Super, RTX 4080, RTX 4070 Ti Super, RTX 4070 Ti, RTX 4070 Super, RTX 4070, RTX 4060 Ti, RTX 4060RTX 6000 Ada, RTX 5880 Ada, RTX 5000 Ada, RTX 4500 Ada, RTX 4000 Ada, RTX 4000 SFFL40S, L40, L20, L4, L2
9.0 Hopper GH100H200, H100
10.0 Blackwell GB100B200, B100
10.xGB202, GB203, GB205, GB206, GB207GeForce RTX 5090, RTX 5080B40
Compute
capability
(version)
Micro-
architecture
GPUs GeForce Quadro, NVS Tesla/Datacenter Tegra,
Jetson,
DRIVE

'*' – OEM-only products

Version features and specifications

Feature support (unlisted features are supported for all compute capabilities)Compute capability (version)
1.0, 1.11.2, 1.32.x3.03.23.5, 3.7, 5.x, 6.x, 7.0, 7.27.58.x9.0
Warp vote functions (__all(), __any())NoYes
Warp vote functions (__ballot())NoYes
Memory fence functions (__threadfence_system())
Synchronization functions (__syncthreads_count(), __syncthreads_and(), __syncthreads_or())
Surface functions
3D grid of thread blocks
Warp shuffle functionsNoYes
Unified memory programming
Funnel shiftNoYes
Dynamic parallelismNoYes
Uniform Datapath [57] NoYes
Hardware-accelerated async-copyNoYes
Hardware-accelerated split arrive/wait barrier
Warp-level support for reduction ops
L2 cache residency management
DPX instructions for accelerated dynamic programmingNoYes
Distributed shared memory
Thread block cluster
Tensor memory accelerator (TMA) unit
Feature support (unlisted features are supported for all compute capabilities)1.0,1.11.2,1.32.x3.03.23.5, 3.7, 5.x, 6.x, 7.0, 7.27.58.x9.0
Compute capability (version)

[58]

Data types

Data typeOperationSupported since
Atomic OperationSupported since
for global memory
Supported since
for shared memory
8-bit integer
signed/unsigned
loading, storing, conversion1.0
16-bit integer
signed/unsigned
general operations1.0atomicCAS()3.5
32-bit integer
signed/unsigned
general operations1.0atomic functions1.11.2
64-bit integer
signed/unsigned
general operations1.0atomic functions1.22.0
any 128-bit trivially copyable typegeneral operationsNoatomicExch, atomicCAS9.0
16-bit floating point
FP16
addition, subtraction,
multiplication, comparison,
warp shuffle functions, conversion
5.3half2 atomic addition6.0
atomic addition7.0
16-bit floating point
BF16
addition, subtraction,
multiplication, comparison,
warp shuffle functions, conversion
8.0atomic addition8.0
32-bit floating pointgeneral operations1.0atomicExch()1.11.2
atomic addition2.0
32-bit floating point float2 and float4general operationsNoatomic addition9.0
64-bit floating pointgeneral operations1.3atomic addition6.0

Note: Any missing lines or empty entries do reflect some lack of information on that exact item. [59]

Tensor cores

FMA per cycle per tensor core [60] Supported since7.07.27.5 Workstation7.5 Desktop8.08.6 Workstation8.78.6 Desktop8.9 Desktop8.9 Workstation9.010.0
Data TypeFor dense matricesFor sparse matrices1st Gen (8x/SM)1st Gen? (8x/SM)2nd Gen (8x/SM)3rd Gen (4x/SM)4th Gen (4x/SM)5th Gen (4x/SM)
1-bit values (AND)8.0 as
experimental
NoNo40962048speed tbd
1-bit values (XOR)7.5–8.9 as
experimental
No1024Deprecated or removed?
4-bit integers8.0–8.9 as
experimental
2561024512
4-bit floating point FP4 (E2M1?)10.0No4096
6-bit floating point FP6 (E3M2 and E2M3?)10.0No2048
8-bit integers7.28.0No12812851225610242048
8-bit floating point FP8 (E4M3 and E5M2) with FP16 accumulate8.9No256
8-bit floating point FP8 (E4M3 and E5M2) with FP32 accumulate
16-bit floating point FP16 with FP16 accumulate7.08.06464642561285121024
16-bit floating point FP16 with FP32 accumulate3264128
16-bit floating point BF16 with FP32 accumulate7.5 [61] 8.0No64 [62]
32-bit (19 bits used) floating point TF32speed tbd (32?) [63] 1283264256512
64-bit floating point8.0NoNo16speed tbd3216

Note: Any missing lines or empty entries do reflect some lack of information on that exact item. [64] [65] [66] [67] [68] [69]

Tensor Core Composition7.07.2, 7.58.0, 8.68.78.99.0
Dot Product Unit Width in FP16 units (in bytes) [70] [71] [72] [73] 4 (8)8 (16)4 (8)16 (32)
Dot Product Units per Tensor Core1632
Tensor Cores per SM partition21
Full throughput (Bytes/cycle) [74] per SM partition [75] 2565122561024
FP Tensor Cores: Minimum cycles for warp-wide matrix calculation848
FP Tensor Cores: Minimum Matrix Shape for full throughput (Bytes) [76] 2048
INT Tensor Cores: Minimum cycles for warp-wide matrix calculationNo4
INT Tensor Cores: Minimum Matrix Shape for full throughput (Bytes)No102420481024

[77] [78] [79] [80]

FP64 Tensor Core Composition8.08.68.78.99.0
Dot Product Unit Width in FP64 units (in bytes)4 (32)tbd4 (32)
Dot Product Units per Tensor Core4tbd8
Tensor Cores per SM partition1
Full throughput (Bytes/cycle) [81] per SM partition [82] 128tbd256
Minimum cycles for warp-wide matrix calculation16tbd
Minimum Matrix Shape for full throughput (Bytes) [83] 2048

Technical specification

Technical specificationsCompute capability (version)
1.01.11.21.32.x3.03.23.53.75.05.25.36.06.16.27.07.27.58.08.68.78.99.0
Maximum number of resident grids per device
(concurrent kernel execution, can be lower for specific devices)
11643216128321612816128
Maximum dimensionality of grid of thread blocks23
Maximum x-dimension of a grid of thread blocks65535231 − 1
Maximum y-, or z-dimension of a grid of thread blocks65535
Maximum dimensionality of thread block3
Maximum x- or y-dimension of a block5121024
Maximum z-dimension of a block64
Maximum number of threads per block5121024
Warp size32
Maximum number of resident blocks per multiprocessor816321632162432
Maximum number of resident warps per multiprocessor2432486432644864
Maximum number of resident threads per multiprocessor7681024153620481024204815362048
Number of 32-bit regular registers per multiprocessor8 K16 K32 K64 K128 K64 K
Number of 32-bit uniform registers per multiprocessorNo2 K [84]

[85]

Maximum number of 32-bit registers per thread block8 K16 K32 K64 K32 K64 K32 K64 K32 K64 K
Maximum number of 32-bit regular registers per thread12463255
Maximum number of 32-bit uniform registers per warpNo63 [86]

[87]

Amount of shared memory per multiprocessor
(out of overall shared memory + L1 cache, where applicable)
16 KiB16 / 48 KiB (of 64 KiB)16 / 32 / 48 KiB (of 64 KiB)80 / 96 / 112 KiB (of 128 KiB)64 KiB96 KiB64 KiB96 KiB64 KiB0 / 8 / 16 / 32 / 64 / 96 KiB (of 128 KiB)32 / 64 KiB (of 96 KiB)0 / 8 / 16 / 32 / 64 / 100 / 132 / 164 KiB (of 192 KiB)0 / 8 / 16 / 32 / 64 / 100 KiB (of 128 KiB)0 / 8 / 16 / 32 / 64 / 100 / 132 / 164 KiB (of 192 KiB)0 / 8 / 16 / 32 / 64 / 100 KiB (of 128 KiB)0 / 8 / 16 / 32 / 64 / 100 / 132 / 164 / 196 / 228 KiB (of 256 KiB)
Maximum amount of shared memory per thread block16 KiB48 KiB96 KiB48 KiB64 KiB163 KiB99 KiB163 KiB99 KiB227 KiB
Number of shared memory banks1632
Amount of local memory per thread16 KiB512 KiB
Constant memory size accessible by CUDA C/C++
(1 bank, PTX can access 11 banks, SASS can access 18 banks)
64 KiB
Cache working set per multiprocessor for constant memory8 KiB4 KiB8 KiB
Cache working set per multiprocessor for texture memory16 KiB per TPC24 KiB per TPC12 KiB12 – 48 KiB [88] 24 KiB48 KiB32 KiB [89] 24 KiB48 KiB24 KiB32 – 128 KiB32 – 64 KiB28 – 192 KiB28 – 128 KiB28 – 192 KiB28 – 128 KiB28 – 256 KiB
Maximum width for 1D texture reference bound to a CUDA
array
819265536131072
Maximum width for 1D texture reference bound to linear
memory
227228227228227228
Maximum width and number of layers for a 1D layered
texture reference
8192 × 51216384 × 204832768 x 2048
Maximum width and height for 2D texture reference bound
to a CUDA array
65536 × 3276865536 × 65535131072 x 65536
Maximum width and height for 2D texture reference bound
to a linear memory
65000 x 6500065536 x 65536131072 x 65000
Maximum width and height for 2D texture reference bound
to a CUDA array supporting texture gather
16384 x 1638432768 x 32768
Maximum width, height, and number of layers for a 2D
layered texture reference
8192 × 8192 × 51216384 × 16384 × 204832768 x 32768 x 2048
Maximum width, height and depth for a 3D texture
reference bound to linear memory or a CUDA array
2048340963163843
Maximum width (and height) for a cubemap texture reference1638432768
Maximum width (and height) and number of layers
for a cubemap layered texture reference
16384 × 204632768 × 2046
Maximum number of textures that can be bound to a
kernel
128256
Maximum width for a 1D surface reference bound to a
CUDA array
Not
supported
655361638432768
Maximum width and number of layers for a 1D layered
surface reference
65536 × 204816384 × 204832768 × 2048
Maximum width and height for a 2D surface reference
bound to a CUDA array
65536 × 3276816384 × 65536131072 × 65536
Maximum width, height, and number of layers for a 2D
layered surface reference
65536 × 32768 × 204816384 × 16384 × 204832768 × 32768 × 2048
Maximum width, height, and depth for a 3D surface
reference bound to a CUDA array
65536 × 32768 × 20484096 × 4096 × 409616384 × 16384 × 16384
Maximum width (and height) for a cubemap surface reference bound to a CUDA array327681638432768
Maximum width and number of layers for a cubemap
layered surface reference
32768 × 204616384 × 204632768 × 2046
Maximum number of surfaces that can be bound to a
kernel
81632
Maximum number of instructions per kernel2 million512 million
Maximum number of Thread Blocks per Thread Block Cluster [90] No16
Technical specifications1.01.11.21.32.x3.03.23.53.75.05.25.36.06.16.27.07.27.58.08.68.78.99.0
Compute capability (version)
[91]

[92]

Multiprocessor architecture

Architecture specificationsCompute capability (version)
1.01.11.21.32.02.13.03.23.53.75.05.25.36.06.16.27.07.27.58.08.68.78.99.0
Number of ALU lanes for INT32 arithmetic operations83248192 [93] 12812864128128646464
Number of ALU lanes for any INT32 or FP32 arithmetic operation
Number of ALU lanes for FP32 arithmetic operations6464128128
Number of ALU lanes for FP16x2 arithmetic operationsNo1128 [94] 128 [95] 64 [96]
Number of ALU lanes for FP64 arithmetic operationsNo116 by FP32 [97] 4 by FP32 [98] 88 / 64 [99] 644 [100] 3243223222?264
Number of Load/Store Units4 per 2 SM8 per 2 SM8 per 2 SM / 3 SM [99] 8 per 3 SM163216321632
Number of special function units for single-precision floating-point transcendental functions2 [101] 4832163216
Number of texture mapping units (TMU)4 per 2 SM8 per 2 SM8 per 2 / 3SM [99] 8 per 3 SM44 / 8 [99] 1681684
Number of ALU lanes for uniform INT32 arithmetic operationsNo2 [102]
Number of tensor coresNo8 (1st gen.) [103] 0 / 8 [99] (2nd gen.)4 (3rd gen.)4 (4th gen.)
Number of raytracing coresNo0 / 1 [99] (1st gen.)No1 (2nd gen.)No1 (3rd gen.)No
Number of SM Partitions = Processing Blocks [104] 1424
Number of warp schedulers per SM partition1241
Max number of new instructions issued each cycle by a single scheduler [105] 2 [106] 12 [107] 21
Size of unified memory for data cache and shared memory16 KiB [108] 16 KiB [108] 64 KiB128 KiB64 KiB SM + 24 KiB L1 (separate) [109] 96 KiB SM + 24 KiB L1 (separate) [109] 64 KiB SM + 24 KiB L1 (separate) [109] 64 KiB SM + 24 KiB L1 (separate) [109] 96 KiB SM + 24 KiB L1 (separate) [109] 64 KiB SM + 24 KiB L1 (separate) [109] 128 KiB96 KiB [110] 192 KiB128 KiB192 KiB128 KiB256 KiB
Size of L3 instruction cache per GPU32 KiB [111] use L2 Data Cache
Size of L2 instruction cache per Texture Processor Cluster (TPC)8 KiB
Size of L1.5 instruction cache per SM [112] 4 KiB32 KiB32 KiB48 KiB [113] 128 KiB32 KiB128 KiB~46 KiB [114] 128 KiB [115]
Size of L1 instruction cache per SM8 KiB8 KiB
Size of L0 instruction cache per SM partitiononly 1 partition per SMNo12 KiB16 KiB? [116] 32 KiB
Instruction Width [117] 32 bits instructions and 64 bits instructions [118] 64 bits instructions + 64 bits control logic every 7 instructions64 bits instructions + 64 bits control logic every 3 instructions128 bits combined instruction and control logic
Memory Bus Width per Memory Partition in bits64 ((G)DDR)32 ((G)DDR)512 (HBM)32 ((G)DDR)512 (HBM)32 ((G)DDR)512 (HBM)32 ((G)DDR)512 (HBM)
L2 Cache per Memory Partition16 KiB [119] 32 KiB [119] 128 KiB256 KiB1 MiB512 KiB128 KiB512 KiB256 KiB128 KiB768 KiB64 KiB512 KiB4 MiB512 KiB8 MiB [120] 5 MiB
Number of Render Output Units (ROP) per memory partition (or per GPC in later models)4848168128416281616 per GPC3 per GPC16 per GPC
Architecture specifications1.01.11.21.32.02.13.03.23.53.75.05.25.36.06.16.27.07.27.58.08.68.78.99.0
Compute capability (version)
[121]

For more information read the Nvidia CUDA programming guide. [122]

Current and future usages of CUDA architecture

Comparison with competitors

CUDA competes with other GPU computing stacks: Intel OneAPI and AMD ROCm.

Whereas Nvidia's CUDA is closed-source, Intel's OneAPI and AMD's ROCm are open source.

Intel OneAPI

oneAPI is an initiative based in open standards, created to support software development for multiple hardware architectures. [125] The oneAPI libraries must implement open specifications that are discussed publicly by the Special Interest Groups, offering the possibility for any developer or organization to implement their own versions of oneAPI libraries. [126] [127]

Originally made by Intel, other hardware adopters include Fujitsu and Huawei.

Unified Acceleration Foundation (UXL)

Unified Acceleration Foundation (UXL) is a new technology consortium working on the continuation of the OneAPI initiative, with the goal to create a new open standard accelerator software ecosystem, related open standards and specification projects through Working Groups and Special Interest Groups (SIGs). The goal is to offer open alternatives to Nvidia's CUDA. The main companies behind it are Intel, Google, ARM, Qualcomm, Samsung, Imagination, and VMware. [128]

AMD ROCm

ROCm [129] is an open source software stack for graphics processing unit (GPU) programming from Advanced Micro Devices (AMD).

See also

Related Research Articles

<span class="mw-page-title-main">Graphics processing unit</span> Specialized electronic circuit; graphics accelerator

A graphics processing unit (GPU) is a specialized electronic circuit initially designed for digital image processing and to accelerate computer graphics, being present either as a discrete video card or embedded on motherboards, mobile phones, personal computers, workstations, and game consoles. After their initial design, GPUs were found to be useful for non-graphic calculations involving embarrassingly parallel problems due to their parallel structure. Other non-graphical uses include the training of neural networks and cryptocurrency mining.

General-purpose computing on graphics processing units is the use of a graphics processing unit (GPU), which typically handles computation only for computer graphics, to perform computation in applications traditionally handled by the central processing unit (CPU). The use of multiple video cards in one computer, or large numbers of graphics chips, further parallelizes the already parallel nature of graphics processing.

<span class="mw-page-title-main">Quadro</span> Brand of Nvidia graphics cards used in workstations

Quadro was Nvidia's brand for graphics cards intended for use in workstations running professional computer-aided design (CAD), computer-generated imagery (CGI), digital content creation (DCC) applications, scientific calculations and machine learning from 2000 to 2020.

nouveau (software) Open source software driver for Nvidia GPU

nouveau is a free and open-source graphics device driver for Nvidia video cards and the Tegra family of SoCs written by independent software engineers, with minor help from Nvidia employees.

In computing, Close To Metal is the name of a beta version of a low-level programming interface developed by ATI, now the AMD Graphics Product Group, aimed at enabling GPGPU computing. CTM was short-lived, and the first production version of AMD's GPGPU technology is now called AMD Stream SDK, or rather the current AMD APP SDK ) for Windows and Linux 32-bit and 64-bit, which also targets Heterogeneous System Architecture.

<span class="mw-page-title-main">Unified shader model</span> GPU whose shading hardware has equal capabilities for all stages of rendering

In the field of 3D computer graphics, the unified shader model refers to a form of shader hardware in a graphical processing unit (GPU) where all of the shader stages in the rendering pipeline have the same capabilities. They can all read textures and buffers, and they use instruction sets that are almost identical.

AMD FireStream was AMD's brand name for their Radeon-based product line targeting stream processing and/or GPGPU in supercomputers. Originally developed by ATI Technologies around the Radeon X1900 XTX in 2006, the product line was previously branded as both ATI FireSTREAM and AMD Stream Processor. The AMD FireStream can also be used as a floating-point co-processor for offloading CPU calculations, which is part of the Torrenza initiative. The FireStream line has been discontinued since 2012, when GPGPU workloads were entirely folded into the AMD FirePro line.

<span class="mw-page-title-main">OpenCL</span> Open standard for programming heterogenous computing systems, such as CPUs or GPUs

OpenCL is a framework for writing programs that execute across heterogeneous platforms consisting of central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs) and other processors or hardware accelerators. OpenCL specifies a programming language for programming these devices and application programming interfaces (APIs) to control the platform and execute programs on the compute devices. OpenCL provides a standard interface for parallel computing using task- and data-based parallelism.

Graphics Core Next (GCN) is the codename for a series of microarchitectures and an instruction set architecture that were developed by AMD for its GPUs as the successor to its TeraScale microarchitecture. The first product featuring GCN was launched on January 9, 2012.

GPULib is discontinued and unsupported software library developed by Tech-X Corporation for accelerating general-purpose scientific computations from within the Interactive Data Language (IDL) using Nvidia's CUDA platform for programming its graphics processing units (GPUs). GPULib provides basic arithmetic, array indexing, special functions, Fast Fourier Transforms (FFT), interpolation, BLAS matrix operations as well as LAPACK routines provided by MAGMA, and some image processing operations. All numeric data types provided by IDL are supported. GPULib is used in medical imaging, optics, astronomy, earth science, remote sensing, and other scientific areas.

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Pascal is the codename for a GPU microarchitecture developed by Nvidia, as the successor to the Maxwell architecture. The architecture was first introduced in April 2016 with the release of the Tesla P100 (GP100) on April 5, 2016, and is primarily used in the GeForce 10 series, starting with the GeForce GTX 1080 and GTX 1070, which were released on May 27, 2016, and June 10, 2016, respectively. Pascal was manufactured using TSMC's 16 nm FinFET process, and later Samsung's 14 nm FinFET process.

<span class="mw-page-title-main">Volta (microarchitecture)</span> GPU microarchitecture by Nvidia

Volta is the codename, but not the trademark, for a GPU microarchitecture developed by Nvidia, succeeding Pascal. It was first announced on a roadmap in March 2013, although the first product was not announced until May 2017. The architecture is named after 18th–19th century Italian chemist and physicist Alessandro Volta. It was Nvidia's first chip to feature Tensor Cores, specially designed cores that have superior deep learning performance over regular CUDA cores. The architecture is produced with TSMC's 12 nm FinFET process. The Ampere microarchitecture is the successor to Volta.

<span class="mw-page-title-main">Metal (API)</span> iOS, macOS, and tvOS graphics rendering API

Metal is a low-level, low-overhead hardware-accelerated 3D graphic and compute shader API created by Apple, debuting in iOS 8. Metal combines functions similar to OpenGL and OpenCL in one API. It is intended to improve performance by offering low-level access to the GPU hardware for apps on iOS, iPadOS, macOS, and tvOS. It can be compared to low-level APIs on other platforms such as Vulkan and DirectX 12.

<span class="mw-page-title-main">GPUOpen</span> Middleware software suite

GPUOpen is a middleware software suite originally developed by AMD's Radeon Technologies Group that offers advanced visual effects for computer games. It was released in 2016. GPUOpen serves as an alternative to, and a direct competitor of Nvidia GameWorks. GPUOpen is similar to GameWorks in that it encompasses several different graphics technologies as its main components that were previously independent and separate from one another. However, GPUOpen is partially open source software, unlike GameWorks which is proprietary and closed.

<span class="mw-page-title-main">SYCL</span> Higher-level programming standard for heterogeneous computing

SYCL is a higher-level programming model to improve programming productivity on various hardware accelerators. It is a single-source embedded domain-specific language (eDSL) based on pure C++17. It is a standard developed by Khronos Group, announced in March 2014.

<span class="mw-page-title-main">AMD Instinct</span> Brand of data center GPUs by AMD

AMD Instinct is AMD's brand of data center GPUs. It replaced AMD's FirePro S brand in 2016. Compared to the Radeon brand of mainstream consumer/gamer products, the Instinct product line is intended to accelerate deep learning, artificial neural network, and high-performance computing/GPGPU applications.

<span class="mw-page-title-main">ROCm</span> Parallel computing platform: GPGPU libraries and application programming interface

ROCm is an Advanced Micro Devices (AMD) software stack for graphics processing unit (GPU) programming. ROCm spans several domains: general-purpose computing on graphics processing units (GPGPU), high performance computing (HPC), heterogeneous computing. It offers several programming models: HIP, OpenMP, and OpenCL.

Ampere is the codename for a graphics processing unit (GPU) microarchitecture developed by Nvidia as the successor to both the Volta and Turing architectures. It was officially announced on May 14, 2020 and is named after French mathematician and physicist André-Marie Ampère.

oneAPI (compute acceleration) Open standard for parallel computing

oneAPI is an open standard, adopted by Intel, for a unified application programming interface (API) intended to be used across different computing accelerator (coprocessor) architectures, including GPUs, AI accelerators and field-programmable gate arrays. It is intended to eliminate the need for developers to maintain separate code bases, multiple programming languages, tools, and workflows for each architecture.

CuPy is an open source library for GPU-accelerated computing with Python programming language, providing support for multi-dimensional arrays, sparse matrices, and a variety of numerical algorithms implemented on top of them. CuPy shares the same API set as NumPy and SciPy, allowing it to be a drop-in replacement to run NumPy/SciPy code on GPU. CuPy supports Nvidia CUDA GPU platform, and AMD ROCm GPU platform starting in v9.0.

References

  1. 1 2 Shah, Agam. "Nvidia not totally against third parties making CUDA chips". www.theregister.com. Retrieved 2024-04-25.
  2. Nvidia. "What is CUDA?". Nvidia. Retrieved 21 March 2024.
  3. 1 2 Abi-Chahla, Fedy (June 18, 2008). "Nvidia's CUDA: The End of the CPU?". Tom's Hardware. Retrieved May 17, 2015.
  4. Zunitch, Peter (2018-01-24). "CUDA vs. OpenCL vs. OpenGL". Videomaker. Retrieved 2018-09-16.
  5. "OpenCL". NVIDIA Developer. 2013-04-24. Retrieved 2019-11-04.
  6. "Nvidia CUDA Home Page". 18 July 2017.
  7. Shimpi, Anand Lal; Wilson, Derek (November 8, 2006). "Nvidia's GeForce 8800 (G80): GPUs Re-architected for DirectX 10". AnandTech. Retrieved May 16, 2015.
  8. "Introduction — nsight-visual-studio-edition 12.6 documentation". docs.nvidia.com. Retrieved 2024-10-10.
  9. Witt, Stephen (2023-11-27). "How Jensen Huang's Nvidia Is Powering the A.I. Revolution". The New Yorker. ISSN   0028-792X . Retrieved 2023-12-10.
  10. "CUDA LLVM Compiler". 7 May 2012.
  11. First OpenCL demo on a GPU on YouTube
  12. DirectCompute Ocean Demo Running on Nvidia CUDA-enabled GPU on YouTube
  13. Vasiliadis, Giorgos; Antonatos, Spiros; Polychronakis, Michalis; Markatos, Evangelos P.; Ioannidis, Sotiris (September 2008). "Gnort: High Performance Network Intrusion Detection Using Graphics Processors" (PDF). Recent Advances in Intrusion Detection. Lecture Notes in Computer Science. Vol. 5230. pp. 116–134. doi:10.1007/978-3-540-87403-4_7. ISBN   978-3-540-87402-7.
  14. Schatz, Michael C.; Trapnell, Cole; Delcher, Arthur L.; Varshney, Amitabh (2007). "High-throughput sequence alignment using Graphics Processing Units". BMC Bioinformatics. 8: 474. doi: 10.1186/1471-2105-8-474 . PMC   2222658 . PMID   18070356.
  15. Manavski, Svetlin A.; Giorgio, Valle (2008). "CUDA compatible GPU cards as efficient hardware accelerators for Smith-Waterman sequence alignment". BMC Bioinformatics. 10 (Suppl 2): S10. doi: 10.1186/1471-2105-9-S2-S10 . PMC   2323659 . PMID   18387198.
  16. "Pyrit – Google Code".
  17. "Use your Nvidia GPU for scientific computing". BOINC. 2008-12-18. Archived from the original on 2008-12-28. Retrieved 2017-08-08.
  18. "Nvidia CUDA Software Development Kit (CUDA SDK) – Release Notes Version 2.0 for MAC OS X". Archived from the original on 2009-01-06.
  19. "CUDA 1.1 – Now on Mac OS X". February 14, 2008. Archived from the original on November 22, 2008.
  20. "CUDA 11 Features Revealed". 14 May 2020.
  21. "CUDA Toolkit 11.1 Introduces Support for GeForce RTX 30 Series and Quadro RTX Series GPUs". 23 September 2020.
  22. "Enhancing Memory Allocation with New NVIDIA CUDA 11.2 Features". 16 December 2020.
  23. "Exploring the New Features of CUDA 11.3". 16 April 2021.
  24. Silberstein, Mark; Schuster, Assaf; Geiger, Dan; Patney, Anjul; Owens, John D. (2008). "Efficient computation of sum-products on GPUs through software-managed cache" (PDF). Proceedings of the 22nd annual international conference on Supercomputing – ICS '08 (PDF). Proceedings of the 22nd annual international conference on Supercomputing – ICS '08. pp. 309–318. doi:10.1145/1375527.1375572. ISBN   978-1-60558-158-3.
  25. "CUDA C Programming Guide v8.0" (PDF). nVidia Developer Zone. January 2017. p. 19. Retrieved 22 March 2017.
  26. "NVCC forces c++ compilation of .cu files". 29 November 2011.
  27. Whitehead, Nathan; Fit-Florea, Alex. "Precision & Performance: Floating Point and IEEE 754 Compliance for Nvidia GPUs" (PDF). Nvidia . Retrieved November 18, 2014.
  28. "CUDA-Enabled Products". CUDA Zone. Nvidia Corporation. Retrieved 2008-11-03.
  29. "Coriander Project: Compile CUDA Codes To OpenCL, Run Everywhere". Phoronix.
  30. Perkins, Hugh (2017). "cuda-on-cl" (PDF). IWOCL. Retrieved August 8, 2017.
  31. "hughperkins/coriander: Build NVIDIA® CUDA™ code for OpenCL™ 1.2 devices". GitHub. May 6, 2019.
  32. "CU2CL Documentation". chrec.cs.vt.edu.
  33. "GitHub – vosen/ZLUDA". GitHub .
  34. Larabel, Michael (2024-02-12), "AMD Quietly Funded A Drop-In CUDA Implementation Built On ROCm: It's Now Open-Source", Phoronix , retrieved 2024-02-12
  35. "GitHub – chip-spv/chipStar". GitHub .
  36. "PyCUDA".
  37. "pycublas". Archived from the original on 2009-04-20. Retrieved 2017-08-08.
  38. "CuPy" . Retrieved 2020-01-08.
  39. "NVIDIA CUDA Programming Guide. Version 1.0" (PDF). June 23, 2007.
  40. "NVIDIA CUDA Programming Guide. Version 2.1" (PDF). December 8, 2008.
  41. "NVIDIA CUDA Programming Guide. Version 2.2" (PDF). April 2, 2009.
  42. "NVIDIA CUDA Programming Guide. Version 2.2.1" (PDF). May 26, 2009.
  43. "NVIDIA CUDA Programming Guide. Version 2.3.1" (PDF). August 26, 2009.
  44. "NVIDIA CUDA Programming Guide. Version 3.0" (PDF). February 20, 2010.
  45. "NVIDIA CUDA C Programming Guide. Version 3.1.1" (PDF). July 21, 2010.
  46. "NVIDIA CUDA C Programming Guide. Version 3.2" (PDF). November 9, 2010.
  47. "CUDA 11.0 Release Notes". NVIDIA Developer.
  48. "CUDA 11.1 Release Notes". NVIDIA Developer.
  49. "CUDA 11.5 Release Notes". NVIDIA Developer.
  50. "CUDA 11.8 Release Notes". NVIDIA Developer.
  51. "NVIDIA Quadro NVS 420 Specs". TechPowerUp GPU Database. 25 August 2023.
  52. Larabel, Michael (March 29, 2017). "NVIDIA Rolls Out Tegra X2 GPU Support In Nouveau". Phoronix . Retrieved August 8, 2017.
  53. Nvidia Xavier Specs on TechPowerUp (preliminary)
  54. "Welcome — Jetson LinuxDeveloper Guide 34.1 documentation".
  55. "NVIDIA Bringing up Open-Source Volta GPU Support for Their Xavier SoC".
  56. "NVIDIA Ada Lovelace Architecture".
  57. Dissecting the Turing GPU Architecture through Microbenchmarking
  58. "H.1. Features and Technical Specifications  Table 13. Feature Support per Compute Capability". docs.nvidia.com. Retrieved 2020-09-23.
  59. "CUDA C++ Programming Guide".
  60. Fused-Multiply-Add, actually executed, Dense Matrix
  61. as SASS since 7.5, as PTX since 8.0
  62. unofficial support in SASS
  63. unofficial support in SASS
  64. "Technical brief. NVIDIA Jetson AGX Orin Series" (PDF). nvidia.com. Retrieved 5 September 2023.
  65. "NVIDIA Ampere GA102 GPU Architecture" (PDF). nvidia.com. Retrieved 5 September 2023.
  66. Luo, Weile; Fan, Ruibo; Li, Zeyu; Du, Dayou; Wang, Qiang; Chu, Xiaowen (2024). "Benchmarking and Dissecting the Nvidia Hopper GPU Architecture". arXiv: 2402.13499v1 [cs.AR].
  67. "Datasheet NVIDIA A40" (PDF). nvidia.com. Retrieved 27 April 2024.
  68. "NVIDIA AMPERE GA102 GPU ARCHITECTURE" (PDF). 27 April 2024.
  69. "Datasheet NVIDIA L40" (PDF). 27 April 2024.
  70. In the Whitepapers the Tensor Core cube diagrams represent the Dot Product Unit Width into the height (4 FP16 for Volta and Turing, 8 FP16 for A100, 4 FP16 for GA102, 16 FP16 for GH100). The other two dimensions represent the number of Dot Product Units (4x4 = 16 for Volta and Turing, 8x4 = 32 for Ampere and Hopper). The resulting gray blocks are the FP16 FMA operations per cycle. Pascal without Tensor core is only shown for speed comparison as is Volta V100 with non-FP16 datatypes.
  71. "NVIDIA Turing Architecture Whitepaper" (PDF). nvidia.com. Retrieved 5 September 2023.
  72. "NVIDIA Tensor Core GPU" (PDF). nvidia.com. Retrieved 5 September 2023.
  73. "NVIDIA Hopper Architecture In-Depth". 22 March 2022.
  74. shape x converted operand size, e.g. 2 tensor cores x 4x4x4xFP16/cycle = 256 Bytes/cycle
  75. = product first 3 table rows
  76. = product of previous 2 table rows; shape: e.g. 8x8x4xFP16 = 512 Bytes
  77. Sun, Wei; Li, Ang; Geng, Tong; Stuijk, Sander; Corporaal, Henk (2023). "Dissecting Tensor Cores via Microbenchmarks: Latency, Throughput and Numeric Behaviors". IEEE Transactions on Parallel and Distributed Systems. 34 (1): 246–261. arXiv: 2206.02874 . doi:10.1109/tpds.2022.3217824. S2CID   249431357.
  78. "Parallel Thread Execution ISA Version 7.7".
  79. Raihan, Md Aamir; Goli, Negar; Aamodt, Tor (2018). "Modeling Deep Learning Accelerator Enabled GPUs". arXiv: 1811.08309 [cs.MS].
  80. "NVIDIA Ada Lovelace Architecture".
  81. shape x converted operand size, e.g. 2 tensor cores x 4x4x4xFP16/cycle = 256 Bytes/cycle
  82. = product first 3 table rows
  83. = product of previous 2 table rows; shape: e.g. 8x8x4xFP16 = 512 Bytes
  84. Jia, Zhe; Maggioni, Marco; Smith, Jeffrey; Daniele Paolo Scarpazza (2019). "Dissecting the NVidia Turing T4 GPU via Microbenchmarking". arXiv: 1903.07486 [cs.DC].
  85. Burgess, John (2019). "RTX ON – The NVIDIA TURING GPU". 2019 IEEE Hot Chips 31 Symposium (HCS). pp. 1–27. doi:10.1109/HOTCHIPS.2019.8875651. ISBN   978-1-7281-2089-8. S2CID   204822166.
  86. Jia, Zhe; Maggioni, Marco; Smith, Jeffrey; Daniele Paolo Scarpazza (2019). "Dissecting the NVidia Turing T4 GPU via Microbenchmarking". arXiv: 1903.07486 [cs.DC].
  87. Burgess, John (2019). "RTX ON – The NVIDIA TURING GPU". 2019 IEEE Hot Chips 31 Symposium (HCS). pp. 1–27. doi:10.1109/HOTCHIPS.2019.8875651. ISBN   978-1-7281-2089-8. S2CID   204822166.
  88. dependent on device
  89. "Tegra X1". 9 January 2015.
  90. NVIDIA H100 Tensor Core GPU Architecture
  91. H.1. Features and Technical Specifications – Table 14. Technical Specifications per Compute Capability
  92. NVIDIA Hopper Architecture In-Depth
  93. can only execute 160 integer instructions according to programming guide
  94. 128 according to . 64 from FP32 + 64 separate units?
  95. 64 by FP32 cores and 64 by flexible FP32/INT cores.
  96. "CUDA C++ Programming Guide".
  97. 32 FP32 lanes combine to 16 FP64 lanes. Maybe lower depending on model.
  98. only supported by 16 FP32 lanes, they combine to 4 FP64 lanes
  99. 1 2 3 4 5 6 depending on model
  100. Effective speed, probably over FP32 ports. No description of actual FP64 cores.
  101. Can also be used for integer additions and comparisons
  102. 2 clock cycles/instruction for each SM partition Burgess, John (2019). "RTX ON – The NVIDIA TURING GPU". 2019 IEEE Hot Chips 31 Symposium (HCS). pp. 1–27. doi:10.1109/HOTCHIPS.2019.8875651. ISBN   978-1-7281-2089-8. S2CID   204822166.
  103. Durant, Luke; Giroux, Olivier; Harris, Mark; Stam, Nick (May 10, 2017). "Inside Volta: The World's Most Advanced Data Center GPU". Nvidia developer blog.
  104. The schedulers and dispatchers have dedicated execution units unlike with Fermi and Kepler.
  105. Dispatching can overlap concurrently, if it takes more than one cycle (when there are less execution units than 32/SM Partition)
  106. Can dual issue MAD pipe and SFU pipe
  107. No more than one scheduler can issue 2 instructions at once. The first scheduler is in charge of warps with odd IDs. The second scheduler is in charge of warps with even IDs.
  108. 1 2 shared memory only, no data cache
  109. 1 2 3 4 5 6 shared memory separate, but L1 includes texture cache
  110. "H.6.1. Architecture". docs.nvidia.com. Retrieved 2019-05-13.
  111. "Demystifying GPU Microarchitecture through Microbenchmarking" (PDF).
  112. Jia, Zhe; Maggioni, Marco; Staiger, Benjamin; Scarpazza, Daniele P. (2018). "Dissecting the NVIDIA Volta GPU Architecture via Microbenchmarking". arXiv: 1804.06826 [cs.DC].
  113. "Tegra X1". 9 January 2015.
  114. Jia, Zhe; Maggioni, Marco; Smith, Jeffrey; Daniele Paolo Scarpazza (2019). "Dissecting the NVidia Turing T4 GPU via Microbenchmarking". arXiv: 1903.07486 [cs.DC].
  115. "Dissecting the Ampere GPU Architecture through Microbenchmarking".
  116. Note that Jia, Zhe; Maggioni, Marco; Smith, Jeffrey; Daniele Paolo Scarpazza (2019). "Dissecting the NVidia Turing T4 GPU via Microbenchmarking". arXiv: 1903.07486 [cs.DC]. disagrees and states 2 KiB L0 instruction cache per SM partition and 16 KiB L1 instruction cache per SM
  117. Jia, Zhe; Maggioni, Marco; Staiger, Benjamin; Scarpazza, Daniele P. (2018). "Dissecting the NVIDIA Volta GPU Architecture via Microbenchmarking". arXiv: 1804.06826 [cs.DC].
  118. "asfermi Opcode". GitHub .
  119. 1 2 for access with texture engine only
  120. 25% disabled on RTX 4090
  121. "I.7. Compute Capability 8.x". docs.nvidia.com. Retrieved 2022-10-12.
  122. "Appendix F. Features and Technical Specifications" (PDF). (3.2 MiB), page 148 of 175 (Version 5.0 October 2012).
  123. "nVidia CUDA Bioinformatics: BarraCUDA". BioCentric. 2019-07-19. Retrieved 2019-10-15.
  124. "Part V: Physics Simulation". NVIDIA Developer. Retrieved 2020-09-11.
  125. "oneAPI Programming Model". oneAPI.io. Retrieved 2024-07-27.
  126. "Specifications | oneAPI". oneAPI.io. Retrieved 2024-07-27.
  127. "oneAPI Specification — oneAPI Specification 1.3-rev-1 documentation". oneapi-spec.uxlfoundation.org. Retrieved 2024-07-27.
  128. "Exclusive: Behind the plot to break Nvidia's grip on AI by targeting software". Reuters . Retrieved 2024-04-05.
  129. "Question: What does ROCm stand for? · Issue #1628 · RadeonOpenCompute/ROCm". Github.com. Retrieved January 18, 2022.

Further reading