 | This article includes a list of general references, but it lacks sufficient corresponding inline citations .(May 2017) |
| Bits | 32-bit |
|---|---|
| Introduced | 1981 |
| Design | RISC |
| Successor | MIPS architecture (commercial), MIPS-X, DLX |
MIPS (also known as Stanford MIPS to disambiguate it from later architectures), an acronym for Microprocessor without Interlocked Pipeline Stages, was a research project conducted by John L. Hennessy at Stanford University between 1981 and 1984. MIPS investigated a type of instruction set architecture (ISA) now called reduced instruction set computer (RISC), its implementation as a microprocessor with very large scale integration (VLSI) semiconductor technology, and the effective exploitation of RISC architectures with optimizing compilers. MIPS, together with the IBM 801 and Berkeley RISC, were the three research projects that pioneered and popularized RISC technology in the mid-1980s. In recognition of the impact MIPS made on computing, Hennessy was awarded the IEEE John von Neumann Medal in 2000 by the Institute of Electrical and Electronics Engineers (IEEE) (shared with David A. Patterson), the Eckert–Mauchly Award in 2001 by the Association for Computing Machinery, the Seymour Cray Computer Engineering Award in 2001 by the IEEE Computer Society, and, again with David Patterson, the Turing Award in 2017 by the ACM.
The project was initiated in 1981 in response to reports of similar projects at IBM (the 801) and the University of California, Berkeley (the RISC). Hennessy and his graduate students carried out the MIPS project until its conclusion in 1984, with Hennessy founding MIPS Computer Systems in the same year to commercialize the technology that his group had developed. In 1985, MIPS Computer Systems announced a new ISA, also called MIPS, and its first implementation, the R2000 microprocessor. The commercial MIPS ISA and its implementations saw widespread use, appearing in embedded computers, personal computers, workstations, servers, and supercomputers. In 2021, the current owner of the MIPS architecture, MIPS Technologies, ceased developent of that architecture in favor of RISC-V. [1] In the late 1980s, Hennessy conducted a follow-up project called MIPS-X at Stanford.
As a 32-bit architecture, MIPS supported 32-bit addressing and data operations. It was a load/store architecture —all references to memory used load and store instructions that copied data between the main memory and 32 general-purpose registers (GPRs), which other instructions such as integer arithmetic could then use as their operands. It possessed a basic instruction set consisting of instructions for control flow, integer arithmetic, and logical operations. All instructions were 32 bits long. To minimize pipeline stalls, all instructions except for loads and stores had to be executed in one clock cycle. There were no instructions for integer multiplication or division, or operations for floating-point numbers. The architecture exposed all hazards caused by the five-stage pipeline using delay slots. The compiler scheduled instructions to avoid hazards that might result in incorrect computation, while simultaneously ensuring that the generated code minimized execution time. The decision to expose all hazards was motivated by the desire to maximize performance by minimizing critical paths, which interlock circuits lengthened. [2] The MIPS microprocessor was implemented in NMOS logic. [3]