This is a list of processors that implement the MIPS instruction set architecture, sorted by year, process size, frequency, die area, and so on. These processors are designed by Imagination Technologies, MIPS Technologies, and others. It displays an overview of the MIPS processors with performance and functionality versus capabilities for the more recent MIPS Aptiv families.
MIPS version | Processor | Year | Process (nm) | Frequency (MHz) | Transistors (millions) | Die area (mm2) | Pin count | Power (W) | Voltage (V) | D. cache (KB) | I. cache (KB) | MMU | L2 cache | L3 cache | Features |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MIPS I | R2000 | 1985 | 2000 | 8 to 16.67 | 0.11 | 80 | 64 external | 64 external | none | none | 5 stage pipelines, FPU: 2010 | ||||
R3000 | 1988 | 1200 | 16.67 to 40 | 0.11 | 40 | 145, 172 | 4 | 32-256 external | 32-256 external | 0-1 MB external | none | same as R2000; FPU: 3010 | |||
MIPS II | R6000 | 1990 | 60 to 66 | external | external | none | none | 32-bit register size, 36-bit physical address, FPU | |||||||
MIPS III | R4000 | 1991 | 800 | 100 | 1.35 | 213 | 179 | 15 | 5 | 8 | 8 | 128 KB to 4 MB external | none | ||
R4400 | 1992 | 600 | 100 to 250 | 2.3 | 186 | 179 | 15 | 5, 3.3 | 16 | 16 | 128 KB to 4 MB external | none | |||
R4200 | 1993 | 600 | 80 | 1.3 | 81 | 179 | 1.8-2.0 | 3.3 | 8 | 16 | 128 KB to 4 MB external | none | scalar design with a five-stage classic RISC pipeline | ||
R4300i | 1995 | 350 | 100 / 133 | 45 | 120 | 2.2 | 3.3 | none | |||||||
R4600 | 1994 | 640 | 100 / 133 | 2.2 | 77 | 179 | 4.6 | 5 | 16 | 16 | 512 KB external | none | |||
R4650 | 1994 | 640 | 133 / 180 | 2.2 | 77 | 179 | 4.6 | 5 | 16 | 16 | 512 KB external | none | |||
R4640 | 1995 | 640 | 179 | none | |||||||||||
R4700 | 1996 | 500 | 100 to 200 | 2.2 | 179 | 16 | 16 | External | none | ||||||
MIPS IV | R5000 | 1996 | 350 | 150 to 200 | 3.7 | 84 | 223 | 10 | 3.3 | 32 | 32 | 1 MB external | none | ||
RM7000 | 1998 | 250, 180, 130 | 250 to 600 | 18 | 91 | 304 | 10, 6, 3 | 3.3, 2.5, 1.5 | 16 | 16 | 256 KB internal | 1 MB external | |||
R8000 | 1994 | 700 | 75 to 90 | 2.6 | 299 | 591 | 30 | 3.3 | 16 | 16 | 4 MB external | none | superscalar, up to 4 instructions per cycle | ||
R10000 | 1996 | 350, 250 | 150 to 250 | 6.7 | 350 | 599 | 30 | 3.3 | 32 | 32 | 512 KB – 16 MB external | none | |||
R12000 | 1998 | 350, 250 | 270 to 360 | 7.15 | 229 | 600 | 20 | 4 | 32 | 32 | 512 KB – 16 MB external | none | single-chip 4-issue superscalar | ||
R12000A | 2000 | 180 | 400 | none | |||||||||||
R14000 | 2001 | 130 | 500 | 7.2 | 204 | 527 | 17 | 32 | 32 | 512 KB – 16 MB external | none | ||||
R14000A | 2002 | 130 | 600 | 17 | 32 | 32 | none | ||||||||
R16000 | 2003 | 110 | 700 to 1000 | 20 | 64 | 64 | 512 KB – 16 MB external | none | |||||||
R16000A | 2004 | 110 | 800 to 1000 | 64 | 64 | none | |||||||||
R18000 | 2001 | 130 | 1.2 | 1 MB | none | was planned, but not manufactured | |||||||||
MIPS V | H1 "Beast" | none | was planned, but not manufactured | ||||||||||||
H2 "Captain" | none | was planned, but not manufactured | |||||||||||||
MIPS32 | 4K | 1999 | 180 | 167 | 2.5 | none | |||||||||
4KE | 90 | 420 | 1.2 | none | |||||||||||
24K | 2003 | 130, 65, 40 | 400 (130 nm) 750 (65 nm) 1468 (40 nm) | 0.83 | 0 to 64 | 0 to 64 | 4–16 MB external | none | |||||||
24KE | 2003 | 130, 65, 40 | none | ||||||||||||
34K | 2006 | 90, 65, 40 | 500 (90 nm) 1454 (40 nm) | none | |||||||||||
74K | 2007 | 65 | 1110 | 2.5 | 0 to 64 | 0 to 64 | none | ||||||||
1004K | 2008 | 65 | 1100 | 4.7 | 8 to 64 | 8 to 64 | none | ||||||||
M14K | 2009 | 130 | 200 | none | MicroMIPS | ||||||||||
1074K | 2010 | 40 | 1500 | none | |||||||||||
1074Kf | 2010 | 40 | none | Floating point | |||||||||||
microAptiv | 2012 | 90, 65 | 8 to 64 | 8 to 64 | none | ||||||||||
interAptiv | 2012 | 4 to 64 | 4 to 64 | up to 8 MB internal | none | ||||||||||
proAptiv | 2012 | 32 or 64 | 32 or 64 | up to 8 MB internal | none | ||||||||||
MIPS64 | 5K | 1999 | |||||||||||||
20K | 2000 | ||||||||||||||
MIPS version | Processor | Year | Process (nm) | Frequency (MHz) | Transistors (millions) | Die area (mm2) | Pin count | Power (W) | Voltage (V) | D. cache (KB) | I. cache (KB) | MMU | L2 cache | L3 cache | Features |
MIPS Technologies was acquired 17 December 2012, by Imagination Technologies. Since then, the following processors have been introduced by Imagination Technologies.
Imagination Technologies sold MIPS processor rights to Tallwood MIPS Inc in 2017. [1] MIPS Technologies was acquired by Wave Computing in 2018, where "MIPS operates as an IP licensing business unit". [2] [3]
The Warrior P-Class CPU was announced on 14 October 2013. [4]
The CPU IP cores comprising the MIPS Series5 ‘Warrior’ family are based on MIPS32 release 5 and MIPS64 release 6, and will come in three classes of performance and features:
MIPS version | level | Processor | Year | Process (nm) | Frequency (GHz) | Transistors (billions) | Die area (mm2) | Pin count | Power (W) | Voltage (V) | D. cache (KB) | I. cache (KB) | MMU | L2 cache | L3 cache | Features |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MIPS32 Release 5 | Warrior-P | P5600 | 2013 | ? | 1.0 to 2.0 | ? | ? | ? | ? | ? | 32/64 | 32/64 | TLb | Up to 8 MB external | none | VZ, MSA |
Warrior-M | M5100 | 2014 | 65/28 | 0.1 to 0.497 | ? | 0.04 to 0.77 | ? | none | none | FMT | none | none | VZ | |||
Warrior-M | M5150 | 2014 | 65/28 | 0.372/0.576 | ? | 0.89/0.26 | ? | up to 64 | up to 64 | TLB | none | none | VZ | |||
MIPS64 Release 6 | Warrior-P | P6600 | 2015 | 28 | Up to 2.0 | ? | ? | ? | ? | ? | 32/64 | 32/64 | TLB | 0.5 - 8 MB external | none | SMT, VZ |
Warrior-I | I6400 | 2014 | 28 | 1.0 | ? | 1/core | ? | ? | ? | 32/64 | 32/64 | TLB | 0.5 - 8 MB external | none | SMT, VZ | |
Warrior-M | M6200 | 2015 | 65/40/28 | up to 0.750 | ? | 0.19 | ? | none | none | FMT | none | none | ||||
Warrior-M | M6250 | 2015 | 65/40/28 | up to 0.750 | ? | 0.23 | ? | up to 64 | up to 64 | TLB | none | none | XPA | |||
MIPS version | level | Processor | Year | Process (nm) | Frequency (GHz) | Transistors (billions) | Die area (mm2) | Pin count | Power (W) | Voltage (V) | D. cache (KB) | I. cache (KB) | MMU | L2 cache | L3 cache | Features |
A number of companies licensed the MIPS architecture and developed their own processors.
MIPS version | Licensee | Processor | Features | Year | Process (nm) | Frequency (MHz) | Transistors (millions) | Die size (mm2) | Pin count | Power (W) | Voltage (V) | D. cache (KB) | I. cache (KB) | MMU | L2 cache | L3 cache |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MIPS I | Lexra | LX4080, LX4180, LX4280, LX5280, LX8000 | ||||||||||||||
MIPS II | НИИСИ РАН | KOMDIV-32 | ||||||||||||||
MIPS III | Sony Computer Entertainment + Toshiba | Emotion Engine | ||||||||||||||
НИИСИ РАН | KOMDIV-64 | |||||||||||||||
MIPS32 | Alchemy Semiconductor | Au1 | ||||||||||||||
Broadcom | BMIPS3000 | |||||||||||||||
BMIPS4000 | ||||||||||||||||
BMIPS5000 | 1300 | |||||||||||||||
BCM53001 | 65 | 400 | 32 | 32 | ||||||||||||
BCM1255 | ||||||||||||||||
Ingenic Semiconductor | XBurst 1 | single issue, 8-stage pipeline | 2005 | 180, 130, 64, 40 | 240 | 0.15 | 1.8 | 16 | 16 | yes | none | none | ||||
XBurst 2 | dual-issue/dual-threaded | 2013 | 40 | 1200 | 0.15 | 1.8 | 32 | 32 | yes | 512 | none | |||||
MIPS64 | SiByte | SB1 | ||||||||||||||
Broadcom | BCM1125H | 400-800 | 4w @ 400 MHz | 32 | 32 | yes | 256 KB | |||||||||
BCM1255 | Dual-core, DDR2, 4× Gigabit LAN | 800-1200 | 13 W @ 1 GHz | 32 | 32 | yes | 512 KB | |||||||||
Cavium | Octeon: CN30xx, CN31xx, CN36xx, CN38xx | 2006 | ||||||||||||||
Octeon Plus: CN5xxx | 2007 | |||||||||||||||
Octeon II: CN6xxx | 2009 | |||||||||||||||
Octeon III: CN7xxx | 2012 | |||||||||||||||
NEC | VR4305 | |||||||||||||||
VR4310 | ||||||||||||||||
NXP Semiconductors | ?? | |||||||||||||||
?? | ||||||||||||||||
CAS: ICT | none yet | |||||||||||||||
?? | ||||||||||||||||
MIPS version | Licensee | Processor | Features | Year | Process (nm) | Frequency (MHz) | Transistors (millions) | Die size (mm2) | Pin count | Power (W) | Voltage (V) | D. cache (KB) | I. cache (KB) | MMU | L2 cache | L3 cache |
Advanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets.
MIPS is a family of reduced instruction set computer (RISC) instruction set architectures (ISA) developed by MIPS Computer Systems, now MIPS Technologies, based in the United States.
MIPS, formerly MIPS Computer Systems, Inc. and MIPS Technologies, Inc., is an American fabless semiconductor design company that is most widely known for developing the MIPS architecture and a series of RISC CPU chips based on it. MIPS provides processor architectures and cores for digital home, networking, embedded, Internet of things and mobile applications.
Instructions per second (IPS) is a measure of a computer's processor speed. For complex instruction set computers (CISCs), different instructions take different amounts of time, so the value measured depends on the instruction mix; even for comparing processors in the same family the IPS measurement can be problematic. Many reported IPS values have represented "peak" execution rates on artificial instruction sequences with few branches and no cache contention, whereas realistic workloads typically lead to significantly lower IPS values. Memory hierarchy also greatly affects processor performance, an issue barely considered in IPS calculations. Because of these problems, synthetic benchmarks such as Dhrystone are now generally used to estimate computer performance in commonly used applications, and raw IPS has fallen into disuse.
ARM is a family of RISC instruction set architectures (ISAs) for computer processors. Arm Ltd. develops the ISAs and licenses them to other companies, who build the physical devices that use the instruction set. It also designs and licenses cores that implement these ISAs.
SuperH is a 32-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Hitachi and currently produced by Renesas. It is implemented by microcontrollers and microprocessors for embedded systems.
The Intel i860 is a RISC microprocessor design introduced by Intel in 1989. It is one of Intel's first attempts at an entirely new, high-end instruction set architecture since the failed Intel iAPX 432 from the beginning of the 1980s. It was the world's first million-transistor chip. It was released with considerable fanfare, slightly obscuring the earlier Intel i960, which was successful in some niches of embedded systems. The i860 never achieved commercial success and the project was terminated in the mid-1990s.
In computer architecture, 64-bit integers, memory addresses, or other data units are those that are 64 bits wide. Also, 64-bit central processing units (CPU) and arithmetic logic units (ALU) are those that are based on processor registers, address buses, or data buses of that size. A computer that uses such a processor is a 64-bit computer.
Simultaneous multithreading (SMT) is a technique for improving the overall efficiency of superscalar CPUs with hardware multithreading. SMT permits multiple independent threads of execution to better use the resources provided by modern processor architectures.
Nucleus RTOS is a real-time operating system (RTOS) produced by the Embedded Software Division of Mentor Graphics, a Siemens Business, supporting 32- and 64-bit embedded system platforms. The operating system (OS) is designed for real-time embedded systems for medical, industrial, consumer, aerospace, and Internet of things (IoT) uses. Nucleus was released first in 1993. The latest version is 3.x, and includes features such as power management, process model, 64-bit support, safety certification, and support for heterogeneous computing multi-core system on a chip (SOCs) processors.
Loongson is the name of a family of general-purpose, MIPS architecture-compatible microprocessors, as well as the name of the Chinese fabless company that develops them. The processors are alternately called Godson processors, which is described as its academic name.
A multi-core processor is a microprocessor on a single integrated circuit with two or more separate processing units, called cores, each of which reads and executes program instructions. The instructions are ordinary CPU instructions but the single processor can run instructions on separate cores at the same time, increasing overall speed for programs that support multithreading or other parallel computing techniques. Manufacturers typically integrate the cores onto a single integrated circuit die or onto multiple dies in a single chip package. The microprocessors currently used in almost all personal computers are multi-core.
The history of general-purpose CPUs is a continuation of the earlier history of computing hardware.
Imagination Technologies Limited is a British semiconductor and software design company owned by Canyon Bridge Capital Partners, a private equity fund based in Beijing that is ultimately owned by the Chinese government. With its global headquarters in Hertfordshire in the United Kingdom, its primary business is in the design of PowerVR mobile graphics processors (GPUs), neural network accelerators for AI processing, and networking routers. The company was listed on the London Stock Exchange until it was acquired by Canyon Bridge in November 2017.
An instruction set architecture (ISA) is an abstract model of a computer, also referred to as computer architecture. A realization of an ISA is called an implementation. An ISA permits multiple implementations that may vary in performance, physical size, and monetary cost ; because the ISA serves as the interface between software and hardware. Software that has been written for an ISA can run on different implementations of the same ISA. This has enabled binary compatibility between different generations of computers to be easily achieved, and the development of computer families. Both of these developments have helped to lower the cost of computers and to increase their applicability. For these reasons, the ISA is one of the most important abstractions in computing today.
OVPsim is a multiprocessor platform emulator used to run unchanged production binaries of the target hardware. It has public APIs allowing users to create their own processor, peripheral and platform models. Various models are available as open source. OVPsim is a key component of the Open Virtual Platforms initiative (OVP), an organization created to promote the use of open virtual platforms for embedded software development. OVPsim requires OVP registration to download.
RISC-V is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. Unlike most other ISA designs, RISC-V is provided under royalty-free open-source licenses. Many companies are offering or have announced RISC-V hardware; open source operating systems with RISC-V support are available, and the instruction set is supported in several popular software toolchains.
Baikal CPU was a line of MIPS and ARM-based microprocessors developed by fabless design firm Baikal Electronics, a spin-off of the Russian supercomputer company T-Platforms.
Creator is a family of single-board computers developed by Imagination Technologies to promote educational research and software development based on the MIPS architecture. The first board in the platform, the Creator Ci20, was released in August 2014. A second development kit called Creator Ci40 was introduced through a Kickstarter campaign in November 2015.
Since 1985, many processors implementing some version of the MIPS architecture have been designed and used widely.