List of MIPS architecture processors

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This is a list of processors that implement the MIPS instruction set architecture, sorted by year, process size, frequency, die area, and so on. These processors are designed by Imagination Technologies, MIPS Technologies, and others. It displays an overview of the MIPS processors with performance and functionality versus capabilities for the more recent MIPS Aptiv families.

Contents

MIPS Computer Systems/MIPS Technologies

MIPS versionProcessorYearProcess (nm)Frequency (MHz)Transistors (millions)Die area (mm2)Pin countPower (W)Voltage (V)D. cache (KB)I. cache (KB) MMU L2 cacheL3 cacheFeatures
MIPS I R2000 198520008 to 16.670.118064 external64 externalnonenone5 stage pipelines, FPU: 2010
R3000 1988120016.67 to 400.1140145, 172432-256 external32-256 external0-1 MB externalnonesame as R2000; FPU: 3010
MIPS II R6000 199060 to 66externalexternalnonenone32-bit register size, 36-bit physical address, FPU
MIPS III R4000 19918001001.3521317915588128 KB to 4 MB externalnone
R4400 1992600100 to 2502.3186179155, 3.31616128 KB to 4 MB externalnone
R4200 1993600801.3811791.8-2.03.3816128 KB to 4 MB externalnone scalar design with a five-stage classic RISC pipeline
R4300i 1995350100 / 133451202.23.3none
R4600 1994640100 / 1332.2771794.651616512 KB externalnone
R4650 1994640133 / 1802.2771794.651616512 KB externalnone
R4640 1995640179none
R4700 1996500100 to 2002.21791616Externalnone
MIPS IV R5000 1996350150 to 2003.784223103.332321 MB externalnone
RM7000 1998250, 180, 130250 to 600189130410, 6, 33.3, 2.5, 1.51616256 KB internal1 MB external
R8000 199470075 to 902.6299591303.316164 MB externalnone superscalar, up to 4 instructions per cycle
R10000 1996350, 250150 to 2506.7350599303.33232512 KB – 16 MB externalnone
R12000 1998350, 250270 to 3607.152296002043232512 KB – 16 MB externalnonesingle-chip 4-issue superscalar
R12000A 2000180400none
R14000 20011305007.2204527173232512 KB – 16 MB externalnone
R14000A 2002130600173232none
R16000 2003110700 to 1000206464512 KB – 16 MB externalnone
R16000A 2004110800 to 10006464none
R18000 20011301.21 MBnonewas planned, but not manufactured
MIPS V H1 "Beast"nonewas planned, but not manufactured
H2 "Captain"nonewas planned, but not manufactured
MIPS32 4K19991801672.5none
4KE904201.2none
24K2003130, 65, 40400 (130 nm) 750 (65 nm) 1468 (40 nm)0.830 to 640 to 644–16 MB externalnone
24KE2003130, 65, 40none
34K200690, 65, 40500 (90 nm) 1454 (40 nm)none
74K20076511102.50 to 640 to 64none
1004K20086511004.78 to 648 to 64none
M14K2009130200noneMicroMIPS
1074K2010401500none
1074Kf201040noneFloating point
microAptiv201290, 658 to 648 to 64none
interAptiv20124 to 644 to 64up to 8 MB internalnone
proAptiv201232 or 6432 or 64up to 8 MB internalnone
MIPS64 5K1999
20K2000
MIPS versionProcessorYearProcess (nm)Frequency (MHz)Transistors (millions)Die area (mm2)Pin countPower (W)Voltage (V)D. cache (KB)I. cache (KB) MMU L2 cacheL3 cacheFeatures

Imagination Technologies

MIPS Technologies was acquired 17 December 2012, by Imagination Technologies. Since then, the following processors have been introduced by Imagination Technologies.

Imagination Technologies sold MIPS processor rights to Tallwood MIPS Inc in 2017. [1] MIPS Technologies was acquired by Wave Computing in 2018, where "MIPS operates as an IP licensing business unit". [2] [3]

The Warrior P-Class CPU was announced on 14 October 2013. [4]

The CPU IP cores comprising the MIPS Series5 ‘Warrior’ family are based on MIPS32 release 5 and MIPS64 release 6, and will come in three classes of performance and features:

MIPS versionlevelProcessorYearProcess (nm)Frequency (GHz)Transistors (billions)Die area (mm2)Pin countPower (W)Voltage (V)D. cache (KB)I. cache (KB) MMU L2 cacheL3 cacheFeatures
MIPS32 Release 5Warrior-PP56002013 ?1.0 to 2.0 ? ? ? ? ?32/6432/64TLbUp to 8 MB externalnoneVZ, MSA
Warrior-MM5100201465/280.1 to 0.497 ?0.04 to 0.77 ?nonenoneFMTnonenoneVZ
Warrior-MM5150201465/280.372/0.576 ?0.89/0.26 ?up to 64up to 64TLBnonenoneVZ
MIPS64 Release 6Warrior-PP6600201528Up to 2.0 ? ? ? ? ?32/6432/64TLB0.5 - 8 MB externalnoneSMT, VZ
Warrior-II64002014281.0 ?1/core ? ? ?32/6432/64TLB0.5 - 8 MB externalnoneSMT, VZ
Warrior-MM6200201565/40/28up to 0.750 ?0.19 ?nonenoneFMTnonenone
Warrior-MM6250201565/40/28up to 0.750 ?0.23 ?up to 64up to 64TLBnonenoneXPA
MIPS versionlevelProcessorYearProcess (nm)Frequency (GHz)Transistors (billions)Die area (mm2)Pin countPower (W)Voltage (V)D. cache (KB)I. cache (KB) MMU L2 cacheL3 cacheFeatures

Other designers

A number of companies licensed the MIPS architecture and developed their own processors.

MIPS versionLicenseeProcessorFeaturesYearProcess (nm)Frequency (MHz)Transistors (millions)Die size (mm2)Pin countPower (W)Voltage (V)D. cache (KB)I. cache (KB) MMU L2 cacheL3 cache
MIPS I Lexra LX4080, LX4180, LX4280, LX5280, LX8000
MIPS II НИИСИ РАН KOMDIV-32
MIPS III Sony Computer Entertainment + Toshiba Emotion Engine
НИИСИ РАН KOMDIV-64
MIPS32 Alchemy Semiconductor Au1
Broadcom BMIPS3000
BMIPS4000
BMIPS50001300
BCM53001654003232
BCM1255
Ingenic Semiconductor XBurst 1 single issue, 8-stage pipeline2005180, 130, 64, 402400.151.81616yesnonenone
XBurst 2 dual-issue/dual-threaded20134012000.151.83232yes512none
MIPS64 SiByte SB1
Broadcom BCM1125H400-8004w @ 400 MHz3232yes256 KB
BCM1255Dual-core, DDR2, 4× Gigabit LAN800-120013 W @ 1 GHz3232yes512 KB
Cavium Octeon: CN30xx, CN31xx, CN36xx, CN38xx2006
Octeon Plus: CN5xxx2007
Octeon II: CN6xxx2009
Octeon III: CN7xxx2012
NEC VR4305
VR4310
NXP Semiconductors  ??
 ??
CAS: ICT none yet
 ??
MIPS versionLicenseeProcessorFeaturesYearProcess (nm)Frequency (MHz)Transistors (millions)Die size (mm2)Pin countPower (W)Voltage (V)D. cache (KB)I. cache (KB) MMU L2 cacheL3 cache

Other

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References

  1. "Completion of sale of MIPS - Imagination". 25 October 2017.
  2. "Wave Computing and MIPS Technologies Reach Agreement to Exit Bankruptcy".
  3. "About  MIPS" . Retrieved 2019-11-06.
  4. "Imagination reveals first MIPS 'Warrior P-class' CPU core". 2013-10-14. Retrieved 2013-10-28.
  5. "MIPS reborn with 64-bit core launch".