R3000

R3000

Designer	MIPS Computer Systems
Bits	32-bit
Introduced	1988
Design	RISC

The R3000 is a 32-bit RISC microprocessor chipset developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture (ISA). Introduced in June 1988, it was the second MIPS implementation, succeeding the R2000 as the flagship MIPS microprocessor. It operated at 20, 25 and 33.33 MHz.

Description

The MIPS 1 instruction set is small compared to those of the contemporary 80x86 and 680x0 architectures, encoding only more commonly used operations and supporting few addressing modes. Combined with its fixed instruction length and only three different types of instruction formats, this simplified instruction decoding and processing. It employed a 5-stage instruction pipeline, enabling execution at a rate approaching one instruction per cycle, unusual for its time.

The architecture makes use of a branch delay slot. The compilers for the R3000 available from MIPS Computer Systems were typically able to fill the delay slot some 70 to 90 percent of the time. ^[1] In some military applications, the figure was 75 to 80 percent occupied. ^[2]

This MIPS generation supports up to four co-processors. In addition to the CPU core, the R3000 microprocessor includes a Control Processor (CP), which contains a Translation Lookaside Buffer and a Memory Management Unit. ^[3] The CP works as a coprocessor. Besides the CP, the R3000 can also support an external R3010 numeric coprocessor, ^[4] along with two other external coprocessors.

The R3000 CPU does not include level 1 cache. Instead, its on-chip cache controller operates external data and instruction caches of up to 256 KB each. It can access both caches during the same clock cycle.

The R3000 was a further development of the R2000 with minor improvements including larger TLB and a faster bus to the external caches. The R3000 die contained 115,000 transistors and measured about 75,000 square mils (48 mm²). ^[5] MIPS was a fabless semiconductor company, so the R3000 was fabricated by MIPS partners including Integrated Device Technology (IDT), LSI Logic, NEC Corporation, Performance Semiconductor, and others. It was fabricated in a 1.2 μm complementary metal–oxide–semiconductor (CMOS) process ^[3] with two levels of aluminium interconnect.

Use in workstations and servers

MIPS R3000A die shot

The RISC approach found much success and was quickly used by many companies in their workstations and servers. ^[6] Those using the R3000 included:

• Ardent Computer
• Atari COJAG (A modified Atari Jaguar for arcade systems).
• Digital Equipment Corporation (DEC) for their DECstation workstations and multiprocessor DECsystem servers.
• Evans & Sutherland for their Vision (ESV) series workstations.
• LSI Logic for their CW4003 RISC processor core and DCAM-101 system-on-a-chip. ^[7]
• MIPS Computer Systems for their MIPS RISC/os Unix workstations and servers.
• NEC for their RISC EWS4800 workstations and UP4800 servers.
• Prime Computer
• Pyramid Technology
• Seiko Epson
• Silicon Graphics for their Professional IRIS, Personal IRIS and Indigo workstations, and the multiprocessor Power Series visualization systems.
• Sony for their PlayStation and PlayStation 2 (SCPH-10000 to SCPH-700XX - clocked at 36.864 MHz for use as an I/O CPU and at 33.8688 MHz for compatibility with PlayStation games) video game consoles, and NEWS workstations, as well as the Bemani System 573 Analog arcade unit, which runs on the R3000A.
• Tandem Computers for their NonStop Cyclone/R and CLX/R fault-tolerant servers.
• Whitechapel Workstations for their Hitech-20 workstation.
• New Horizons Probe ^{[8] [9] [10]}

Derivatives of the R3000 for non-embedded applications include:

• R3000A - A further development by MIPS introduced in 1989. It operated at clock frequencies up to 40 MHz.
• PR3400 - Developed by Performance Semiconductor, introduced in May 1991, also at up to 40 MHz. It integrated the Performance Semiconductor PR3000A and PR3010A onto a single die.

Use in real-time systems

The MIPS R3000 could be used for real-time computing; indeed, an editor of Computer Design journal characterized the R3000 as "about the cleanest of the RISC processors to implement a real-time operating system". ^[2] It was possible for embedded implementations of the R3000 to customize the processor in certain ways, such as adding debugging facilities or adding traps on unimplemented features and opcodes. ^[11] The R3000 was used as an embedded systems microprocessor by a number of companies:

• Heurikon Corporation, with their HKMIPS/3500 board ^[12]
• Integrated Device Technology, with their IDT7RS301 and IDT7RS302 ^[12]
• LSI Logic, with their LR33000 for embedded control applications, with a 50Mz processor, 8K instruction cache and 1K data cache, ^[11] including an LR33000 Pocket Rocket Evaluation Board; ^[12] also with their larger LR3000, with memory management included ^[6]
• MIPS Computer Systems itself, with their R3200-6 CPU board ^[12]
• Lockheed Sanders, with their STAR MVP R3000/R3010 board that contains a 25 MHz processor, 128K instruction and data caches, and a 4-word write buffer ^[13]
• Texas Instruments, with their TI DP32 ^[12]

A number of these embedded systems were used in defense/avionics applications, and as such by the early 1990s there were a number of Ada programming language cross-compiler implementations available for the R3000. ^[12] The Joint Integrated Avionics Working Group (JIAWG), a United States government initiative of the late 1980s intended to establish common standards for the next generation of U.S. Air Force, Navy, and Army aircraft, selected the R3000 as one of two 32-bit instruction set architectures for real-time embedded systems applications (the other being the Intel i960). ^[2] In defense industry uses, the R3000 was often a successor to the 16-bit MIL-STD-1750A architecture. ^[14]

Use in other lower-cost designs

Even after advances in technology rendered the R3000 obsolete for high-performance systems, it found continued use in lower-cost designs. Derivatives of the R3000 for embedded applications include:

IDT R3051

IDT R3081

• CW4003, DCAM-101 - Aimed at digital camera applications, the CW4003 core featured a "multiplier-addition bolt-on" (MABO) unit for accelerated integer arithmetic and a pixel-processing accelerator (PPA) unit accessible via the coprocessor 2 interface. The DCAM-101 combined the CW4003 core with modules interfacing to a camera sensor, display, storage and other peripherals, also incorporating a JPEG compression/decompression unit. ^[7]
• PR31500, PR31700 - Microprocessors from Philips Semiconductors used in the Philips Velo handheld PC range. The 75 MHz PR31700 was fabricated in a 350 nm process, delivered in a 208-pin LQFP, it operated at 3.3 V and dissipated only 350 mW.^{[ citation needed ]}
• RISController - A family of embedded microprocessors from IDT. Models included the R3041, R3051, R3052, R3071 and R3081. All models included integrated L1 caches. Higher-end models included larger caches and optional MMUs and FPUs. They competed with the intel i960 and AMD 29000.
• TX3900 - A microcontroller from Toshiba.
• Mongoose-V - A radiation-hardened and expanded 10–15 MHz CPU for use on spacecraft, it is still in use today in applications such as NASA's New Horizons space probe.

References

1. Stallings, William (1996). Computer Organization and Architecture: Designing for Performance (Fourth ed.). Upper Saddle River, New Jersey: Prentice-Hall. p. 461. ISBN   0-13-359985-X.
2. Kurtz, J. Jay; Thibeault, John E.; Brauckmann, Walter J. (1990). An Applicability Evaluation of the MIPS R3000 and Intel 80960MC Processors for Real-Time Embedded Systems . IEEE Conference on Aerospace and Electronics, Dayton, OH, USA, 1990. pp. 140–147. doi:10.1109/NAECON.1990.112756.{{cite conference}}: Wikipedia Library link in |url= (help)
3. Jurij Šilc; Borut Robič; Theo Ungerer (1999). Processor Architecture: From Dataflow to Superscalar and Beyond. Springer-Verlag Berlin Heidelberg. p. 38. ISBN   978-3-540-64798-0.
4. Rowen, Chris; Johnson, Mark; Ries, Paul (June 1988). "The MIPS R3010 Floating-Point Coprocessor". IEEE Micro. 8 (3). The Institute of Electrical and Electronics Engineers: 53–62. doi:10.1109/40.540. ISSN   0272-1732. S2CID   12859181 . Retrieved 24 April 2022.
5. Michael Slater, ed. (1992). A Guide to RISC microprocessors. Academic Press, Inc. p. 129. ISBN   978-0-12-649140-1.
6. Caulk, Bob; et al. (1991). The Architecture of the LR33000: A MIPS Compatible RISC processor for Embedded Control Applications . IEEE International Conference on Computer Design: VLSI in Computers and Processors, Cambridge, MA, USA, 1991. pp. 333–336. doi:10.1109/ICCD.1991.139911.{{cite conference}}: Wikipedia Library link in |url= (help)
7. Archide, Reynaldo (March 1998). "A Flexible CPU for Digital Cameras". Byte. pp. 49–50. Retrieved 17 August 2023.
8. Sharma, Aashish (21 July 2015). "The Original PlayStation CPU is Powering New Horizons". Fossbytes.
9. Tomson, Iain (14 January 2015). "PlayStation-processor-powered plutonium probe prepares Pluto pics". The Register .
10. Dockrill, Peter (17 July 2015). "NASA's New Horizon Probe Made It to Pluto With a PlayStation CPU For a Brain". Science Alert.
11. Peck, Raymond; Patel, Jay (1991). Design Methodology for a MIPS Compatible Embedded Control Processor . IEEE International Conference on Computer Design: VLSI in Computers and Processors, Cambridge, MA, USA, 1991. pp. 324–328. doi:10.1109/ICCD.1991.139909.{{cite conference}}: Wikipedia Library link in |url= (help)
12. "Ada Implementations". Ada–JOVIAL Newsletter. High Order Language Control Facility, Wright-Patterson AFB, U.S. Air Force. September 1993. pp. 26–43, especially 32–34.
13. Schilling, Jonathan L.; Nielsen, Johan Olmütz (May–June 1994). "Automatic compiler recognition of monitor tasks". ACM SIGAda Ada Letters. 14 (3): 91–104. doi:10.1145/181468.181474.
14. See for instance Keller, John (April 1997). "R3000-based Apache Longbow computers set for production". Military & Aerospace Electronics.

External links

• "MIPS Technologies R3000"