V850 is a 32-bit RISCCPU architecture produced by Renesas Electronics for embeddedmicrocontrollers. It was designed by NEC as a replacement for their earlier NEC V60 family, and was introduced shortly before NEC sold their designs to Renesas in the early 1990s. It has continued to be developed by Renesas as of 2018[update].
The V850/RH850 microcontrollers are also used prominently on non-Japanese automobile marques such as Chevrolet, Chrysler, Dodge, Ford, Hyundai, Jeep, Kia, Opel, Range Rover, Renault and Volkswagen Group brands.
Its base-architecture has been succeeded by the V850 family variants, named V850E, V850E1, V850ES,[5] V850E1F, V850E2, V850E2M, V850E2S, and the RH850 family (V850E2M, V850E2S, and V850E3) CPU cores.
Many compilers and debuggers are available from various development tool vendors.
In-circuit emulators (ICE) are provided by many vendors. Legacy proven pod-based types—the JTAG-based N-Wire interface with the N-trace type, and the Nexus interface with the Aurora Trace type—are available.
In 1997, the V850/xxn product line started with the V850/SA1[10] and the V850/SV1[11] and expanded its application to ultra-lo-power products such as "handy camcorders." It has a main and sub internal oscillatoramplifier working from 1.8V to 3.6V with external crystal or ceramicresonator.[10] Software STOP mode, whose internal watch timer operates with a 32.768kHz sub-oscillator, typically consumes only 8μA of electrical current.[12][13] In 1998, NEC launched the V850/SB1,[14] with IEBus controller, for car audio, an ultra-low-power (3.6mW@5V/MIPS) and ultra-low-noise (EMI/EMS) 5V product.[15] The V850/SC1[16] was also for car audio.[17] These strategic product line expansions succeeded in increasing the number of devices sold.
This first generation of the V850 core is also used for some NEC mobile phones.[18] It is also used for the programmable-host CPUs of some small form factor GSM/GPRS mobile devices with GPS embedded modem modules.[19]
In the next phase, NEC targeted the automotive industry with a CAN bus controller based on the V850,[20] as the V850/SF1.[21] Later on, the automotive industry became the main target of the V850 and RH850.
The V850E core was targeted at system-on-a-chip (SoC) applications as well as standard products,[22][23] and was used for some Japanese domestic mobile phones, including Sony Mobile's and NEC's.[24][25][26][27][28] V850E and V850ES are also used in air conditioninginverter compressors.[29][30][31][32] At this stage, another mass market was its use in car audio.[33] The V850ES core succeeded in the low-power embedded-product line,[34] and is ISA-compatible with the V850E. NEC Electronics (currently, Renesas Electronics) adopted the V850 CPU core for its USB 3.0 controllers.[35]:11
Around 2005, several companies started a feasibility study for the FlexRay controller on the V850E platform. Yokogawa Digital Computer (currently DTS INSIGHT) developed an evaluation board named GT200 with a V850E/IA1 and a field-programmable gate array (FPGA), which employs the FlexRay controller developed by Bosch.[36]:78,PDF80
The V850E2 core primarily targeted automotive areas,[37] but was also used for NEC's mobile phones.[38]
The V850 family line up (based on V850E, V850ES, and V850E2 cores) and the Renesas RH850 family (based on the V850E3 core, as of 2018) are mainly employed in automotive applications as well as inter-equipment connectivity and motor-control specific microcontroller units (MCUs).[39][40]
Trademark strategy
The V850 is a unregistered trademark but not a registered one.[41] NEC once applied for a trademark to be registered with the Japan Patent Office, but it was rejected,[42][43] as it was a natural extension of the series number. However, this action has been enough to prevent other people or organizations from registering it as a trademark. In addition, Renesas has been using the V850X/xxn type trademark, such as V850E/MA1, for more than 20 years, because the combination of one alphabetical with two numerical characters cannot be granted as a registered trademark. It is thus free to use without registration.
One exception is V850E/PHO3 (PHOENIX 3, or PHOENIX-FS).[44]:3[45]:33 Another usage of PHOENIX 3 by Renesas Electronics is the COOL PHOENIX 3, which employs the ARM Cortex-M0 core.[46] PHOENIX 3 is a registered trademark of the 3DO Company as USPTO Reg. 2,009,119.[47]
According to current Renesas Electronics documentation, at least the following strings are regarded as its trademark: "V800 Series", "V850 family", "V850/SA1", "V850/SB1", "V850/SB2", "V850/SF1", "V850/SV1", "V850E/MA1", "V850E/MA2", "V850E/IA1", "V850E/IA2", "V850E/MS1", "V850E/MS2", "V851", "V852", "V853", "V854", "V850", "V850E", and "V850ES".[41][48]
Because the V850 trademark has been used for more than 20 years, most people do not know that the RH850 family is based on an extension of the V850 instruction set architecture, and has backward compatibility with V850, V850E, V850ES, and V850E2. The RH850 is consequently thought of as being without the legacy software compatibility of the V850.[49][50]
Because the V850family[48]:16 was developed as a branch of the V800series,[3]:97,PDF103 the basic CPU architecture is inherited from the V810.[52] The instruction set architecture of the first V850 is drastically modified from that of the V810, but the difference is within a patch level from the GNU Compiler Collection point of view.[53] The main purpose of this change is to implement saturation arithmetic at customers' request.
A v833 CPU, a pin-compatible revision of the v832 CPU. This microprocessor was used in car navigation systems during the 2000's, mostly made by Pioneer Corporation and Alpine Electronics.
The detailed design methodology of the V810 is described in this journal.[56] The V850 utilizes these design assets; but the datapath logic was changed from dynamic logic to static logic, to enable 32.768kHz real-time clock frequency operation mode.
Most of the register-transfer-level FDL netlist was translated to the gate-level schematic by hand, because the logic synthesis had not yet to be practical. The FDL was precisely divided into datapath and random logic. For the datapath part, the gate-level circuit diagram enabled manually repeated artwork. On the other hand, for the random logic part, logic synthesis was tried for generating gate-level schematic, but it was only about 10% of the total circuit.
In addition, formal verification was also not yet practical, which meant that full regression test by dynamic logic simulation was required for the gate-level netlist to compare with the RTL one. For gate-level logic simulation, NEC's in-house CAD tool V-SIM was usually used.[67] But sometimes a hardware emulator, such as Zycad LE simulation accelerator,[68] was used for this purpose. (Refer to:.[69]:13 In this material, the performance of Zycad LE is compared with NEC's HAL, but initial design decade differs.[70])
Architecture
Basic architecture
The basis of the V810 and V850 has a typical general-purpose registers-based load/store architecture.[71]:4 There are 32 32-bit general-purpose registers. Register 0 (R0) is fixed as the Zero Register which always contains zero. In the V850, R30 is implicitly used by the sld and sst instructions. 16-bit short-format load/store instructions use element pointer (ep), where the addressing mode comprises the base address register ep and immediate-operand offsets. In V850E or later microarchitectures, R3 is implicitly used by PREPARE/DISPOSE; call stack frame creation; and unwinding instructions, as a stack pointer. Compilers' calling conventions also use R3 as the stack pointer.
The original V850 has a simple 5-stage 1-clock pitch pipeline architecture.[48]:114–126 This is a significant feature of reduced instruction set computers (RISCs). But the object-code size is about half that of the MIPSR3000,[71]:5 because the V810 and V850 adopted 16-bit and 32-bit 2-way form-length instruction formats, respectively,[48]:38–40[71]:17[72]:29–30 and most of the frequently used instructions are mapped onto a 16-bit half-word. In other words, a 16-bit external bus width is enough to provide instructions continuously without pipeline stalling, which enables low power consumption on the application board, and is suitable for mobile equipment. This concept is similar to Renesas (formerly, Hitachi) SH, ARM Thumb, and MIPS16 instruction set architectures.[73]:4
In addition, the instruction set is carefully implemented. For example, to execute a function call with a Jump and (Register) Link instruction,[48]:61[71]:20[72]:64 which saves the next program counter (PC) on a register (fixed to R31 in V810), is also one of the RISC techniques to reduce the number of instructions. Return from the function can be accoomplished by jmp [Rn] (jmp [R31] in V810) instruction.[48]:61[71]:23[72]:65 Typical CISC processors use call and return instructions and push the next PC on their stack memory area.
Though the V800 series adopts a RISC instruction set architecture, their assembly language is hand-coding friendly. They adopt a straightforward load/store architecture.[71]:4 In addition, the "interlock" mechanism, both for the data hazards and for the branch hazards, are implemented:[71]:33–35 in other words, an assembly language programmer does not need to consider any delay slots. 32 general-purpose registers provide flexibility for assembly language users. A mixture of hand-assembled codes and C language compiled codes is facilitated by using compiler options, such as "-mno-app-regs" in the Gnu Compiler Collection.[74]
The IN instruction of the V810, which enables unsigned-load from memory-mapped I/O, was removed from the first V850s.[71]:22[72]:63
Detailed discussions are available in some old journals.[75][76]
Instruction set extensions
The V850 series added many instruction set extensions, but all the extensions have backward compatibility.[77] Therefore, old binary software assets work on the new cores.
The first generation of the V850 does not have unsigned load instructions, which had been removed from the V810 (where it was implemented with IN.H and IN.B). Then, in the second generation V850E (V850E1) Series, such unsigned functionality was again added (with LD.HU and LD.BU). In addition, the V850E has some other user-friendly "CISCy" extensions, such as call table, switch, and prepare/dispose.[78]:217
In 1996, the V853 was announced as the first 32-bit RISC microcontroller with integrated flash memory.[79] But its maximum number of "erase and write" cycles was 16.[80]:37
In 2001, NEC launched V850ES core, which is an ultra-low-power series, but is ISA-compatible with the V850E.[82]
Around 2001, Java Acceleration IP core for the V850 seemed to be provided to some customers as SoC,[83] but detailed information is only found in some patents.[84][85]
In 2009, NEC Electronics introduced V850E2M as dual-core with 2.56MIPS/MHz and 1.5mW/MIPS.[87]
In 2011, Renesas disclosed the SIMD extension for the V850 as V850E2H.[77][88] As for the SIMD extension, some academic studies were done.[89] But architectural documentation for this latest product line is disclosed to automotive customers only; it cannot be found on Renesas' website.[90] Its name seems to have been changed to V850E3 or G3H. The only way to know about its instruction set is to reverse engineer it with the GNU Compiler Collection.
Power consumption
The original V810 and V850 CPU architecture is designed for ultra-low power applications.
The V810 is described in detail in some journals.[91][92]
According to Renesas's documentation, the power consumption of the V850ES/Jx3-L implementation is about 70% of ARM Cortex-M3.[5]:14,15
The V810 was one of the most low-power 32-bit microcontroller products of the early 1990s. It operates at from 2.2V to 5.5V with a 5V 0.8μm (CZ4) fabrication process.[93] Measured with Dhrystone MIPS, power dissipation is 500mW at 15MIPS and 40mW at 6MIPS, at 5V and 2.2V, respectively. This specification can be achieved both by well considered instruction-set architecture and by precisely tuned 5-stage 1-clock pitch pipeline microarchitecture, both of which are the benefit of a simplified RISC architecture.
This ultra-low-power architecture was succeeded by V850/Sxn product line, which are still being mass-produced after 20 years. Most of the improved chips are produced using a 3.3V, 0.35μm (UC1) fabrication process, where the CPU core is precisely tuned to operate from 1.8V to 3.6V, working at 32.768kHz (sub-oscillator) to 16.78MHz (main-oscillator) with internal oscillator amplifier plus external resonator (crystal or ceramic).[10] Its power dissipation is 2.7mW/MIPS at 3.3V when made with a 0.35μm (UC1) fabrication process, and 3.6mW/MIPS at 5V with a 0.35μm (CZ6) fabrication process. "Software STOP" stand-by mode for the mask ROM version of V850/SA1, whose internal watch timer operates at 3.3V with 32.768kHz sub-oscillator (IDD6), consumes typically only 8 μA electrical current. Subclock normal operation mode at 3.3V with 32.768kHz consumes 40 μA typically, 140 μA at the maximum. (IDD5)[94]:440,IDD5[13] Its 1.8V typical CPU operating current at 32.768kHz might be 22 μA (40μA ÷ 3.3V × 1.8V), where power dissipation should be 40μW. It corresponds to 1.0mW/MIPS (40μW ÷ 0.032768MHz ÷ 1.15DMIPS/MHz ÷ 1000). The V850/Sxn product line is also tuned for low noise, with both EMI and with EMS. The V850/SB1 and SB2 are especially tuned for low EMI noise with a 5V internal voltage regulator, which facilitates high sensitivity in receiving RF for car radios.[95]:41–44
In 2011, NEC launched the 3rd generation microarchitecture V850ES ultra-low-power series, which achieves 1.43mW/MIPS at an operating voltage range of from 2.2V to 2.7V,[82] but this first implementation of V850ES microarchitecture seems to be incomplete compared with later generations of the same architecture. Its "Sub-IDLE" stand-by mode for the mask ROM version of V850ES/SA2 and V850ES/SA3, whose internal RTC operate at 2.5V with 32.768kHz sub-oscillator (IDD6), consume typically only 5 μA electrical current. But, Subclock normal operation mode at 2.5V with 32.768kHz consumes typically 40 μA, 100 μA at the maximum.[96]:509 Its 2.2V typical CPU operation current at 32.768kHz might be 31 μA (40μA ÷ 2.5V × 2.2V), where power dissipation should be 68 μW. This is about 1.7 times that of V850/SA1. It corresponds to 1.6mW/MIPS (68μW ÷ 0.032768MHz ÷ 1.3 DMIPS/MHz ÷ 1000).
The V850ES/JG3-L product line has ultra-low-power variants, the μPD70F3792, 793, and the μPD70F3841, 842. They can operate from 2.0V to 3.6V with typical electrical current of 18 μA at 32.768kHz,[97]:1002,1041 which should be 22 μW at 2.0V (18μA × 2.0V ÷ 3.3V × 2.0 V). This corresponds to 0.52mW/MIPS (22μW ÷ 0.032768MHz ÷ 1.3 DMIPS/MHz ÷ 1000). In addition, their sub-clock idle mode power consumption, with watch timer, should be typically 3.4 μW at 1.8V (3.5μA ÷ 3.3 V × 1.8V × 1.8V).[97]:1002,1041
The power consumption of the NA85E2 (V850E2) core is much larger compared with the NU85E (V850E1) core using the same CB-12L (UX4L)[93][98] fabrication process. The reason is that the V850E2x core has a 128-bit instruction prefetch bus and more than one instruction prefetch queue,[99]:16 while the average instruction length of the V800 series is 16 bits.[71]:17 It means 16 instructions can be fetched from the memory at once, and the memory and prefetch circuits sleep fors 3 to 7 cycles for dual-pipeline superscalar architecture. This gap enlarges electrical current amplitude differences. In addition, the peak electric current exceeds allowances for the voltage stabilizers of mobile gadgets. As for V850E2M CPU core, it is publicly introduced as 1.5mW/MIPS, 3 times that of former generations, although it should be able to take advantage of new fabrication process technologies.[87] Some mobile equipment avoids using dual-instruction execution (dual-pipeline superscalar), adopting the single-instruction (single-pipeline) execution setting to reduce electrical current amplitude differences.
All opcodes (operation codes) of the hardwired control operation are contained within the first 16-bit half-word of an instruction, from the most significant bit (MSB). A 64-word depth ROM structure with branch condition code table is enough for decoding hardware. If a 16-bit literal operand is required, it is located in the second half-word. Microprogram control operations, bit strings, and floating-point arithmetic instructions are also located in the second 16-bit half-word. As a result, all the instructions have 16-bit and 32-bit 2-way form length. Unsigned load form memory mapped I/O is implemented as the In instruction. Arithmetic and logical instructions are not fully, but relatively, orthogonal.
The V810 does not have saturation arithmetic instructions, but 1 additional instruction in format II, such as SAT which checks flags (Overflow, Sign, Zero, and Half-word) and rewrites the specified register, might be enough both for signed and unsigned, and for word and half-word, arithmetic operations.
Not for new developments. Signed load. 1.15 Dhrystone MIPS/MHz Ultra-low power products. 3.6mW/MIPS (5V product) 2.7mW/MIPS(3.3Vproduct) 1.0mW/MIPS(1.8VSub-ope.)
NA85E2 SoC core[112][114] (NEC's long-running cellular. Sets life = 2004–2012.)
-mv850e2
Not for new developments. Many errata but still alive. Single insn. executing. (Dual-executing errata.) 7-stage pipeline. S/W float. Standard Products. SoC Products.
In 1998, NEC started to provide the V850 family as an ASIC core, to expand its ASIC business.[117] In addition, both the V850E1 CPU core named Nx85E[118][119] and the V850E2 CPU core named Nx85E2,[120] are also used for expanding its ASIC products business. Various SoCs utilize this core. In 2003, for example, Dotcast, Inc. used the NU85E core for a set top box receiver of digital datacasting based on the dNTSC (data in NTSC video method[121]). This core is fabricated with CB-10 0.25μm 5-layered-metal process technology.[122]:9–10
The NA85E2C core, which is developed using a 1.5V 150nm CB-12L (UX4L) fabrication process,[93][98] has many errata (4 pages appendix in preliminary architecture manual,[123]:230–233 plus a further, 7-page restrictions document[124]), but which doesn't seem to matter, because this is a product with a long lifespan.
NEC also expanded production of a core using a 130nm CB-130 (UX5) fabrication process,[93] cell-base IC.[125][126]
Synopsys DesignWare IP core for V850E was once announced,[127] but support has been discontinued.[128]
FPGA prototyping systems for V850E1, V850E2, and V850E2M core-based SoCs were intensively developed to expand the SoC business. They comprised a V850 CPU core LSI (TEG, or Test Element Group) board and FPGA add-ons. Most SoC products were for mobile equipments, because the power dissipation of original V800-Series RISC architecture was much lower compared with CISC.[1][5][103] It is similar to the ARM architecture that is widely used for mobile gadgets.
Around 2011–2014, Renesas Electronics extensively expanded the V850E2 product line,[148][149] but this high-paced expansion brought much confusion. For example, as of 2018, some have requested that V850E2/xxn products be replaced with RH850/xnx ones.[150]
In addition, in 2012 Renesas started to intensively promote the migration from ten-year-old V850ES/Jx3 product lines to the newly produced V850E2/Jx4, such as for Ethernet and USB applications,[151][152] but the newer products are not listed on their website, as of 2018.[39]
Currently,[as of?] Renesas Electronics is designing a "dual" "lockstep" system, but its predecessor NEC V60-V80 had "multiple modular" lockstep mechanism called FRM,[153] either with roll-back by "retry" or with roll-forward by "exception" for each fault detected instruction.
In addition, the NEC V60-V80 has several implementations of UNIX System V port product releases, one of which is "real-time UNIX RX/UX-832"[154] (here, 832 stands for the μPD70832 (V80), not V832). Its multiprocessor implementation is called MUSTARD (Multiprocessor Unix for Embedded Real-Time Systems), which can operate a maximum of 8 processors simultaneously, and its lockstep mechanism was dynamically configurable.[155]
In 2001, both NEC Corporation and Synopsys, Inc., announced they had agreed to promote the V850E as DesignWare IP core.[127][128] But as of 2018, the V850E is not listed on DesignWare libraries.[156]
In 2006,Metrowerks developed the CodeWarrior compiler for the V850, which was one of the main compilers for the V850,[161] but around 2010, they discontinued support.
Also in 2006, NEC did not give any roadmap for the V850 family as SoC cores.[115] The V850E2 core, developed in 2004, was described as the last, best core for SoC applications. However, NEC introduced ARM9 (arm v5) and ARM11 (arm v6), especially for mobile equipment. This decision suddenly decreased the net profit of LSI devices, because of the royalty for using ARM, and thus price competition with other ARM SoC providers. The sales revenue of "V850 total solutions", such as development tools, real-time OS, middle-ware packages, and in-circuit emulators, also decreased. The number of V850 devices sold also suddenly decreased, because mobile equipment manufacturer were the major customers of V850E1 and V850E2 cores at that moment.[162]
In 2008, KMC (Kyoto Mictocomputer), which is one of the major and of the first providers of in-circuit emulators for the V850 family, announced "exeGCC" being updated from Rel. 3 to Rel. 4,[163] but it excluded the V850 from this updating list, which added PowerPC and ARM v7. KMC chose SH-4A and ARM v7, instead of V850 and RH850,[164] though it had been working closely with NEC and Renesas Electronics.[161]
The V850 CPU cores run uClinux,[165] but on October 9, 2008, Linux kernel support for the V850 was removed in revision 2.6.27.,[166] because NEC stopped its maintenance.[167][168][169] The person in charge of V850 Linux kernel maintenance was moved from NEC to Renesas by its merger, but his new job was compiler design and never returned to Linux kernel maintenance.[170] This corporate decision prevented the possibility of porting to Android.[171] As of 2018, Renesas Electronics mainly focuses Linux kernel support on SH3/SH4 and M32R processors. [172][173][174][175][176]
ITRON is an open standard specification of real-time OS (RTOS), which is major in Japan. Its specification is defined under the leadership of Ken Sakamura, as a part of TRON project, the initialr I standing for "Industrial". Because the ITRON specification defines interface and skeleton only, each vendor has its own implementation.
In Japan, this research was started in 2006, as a joint project by JAIST and DENSO. Renesas Electronics joined this project in 2009.[193] Because the current RH850 and V850 processors are principally targeted at the automotive industry, it is a strategical product of Renesas Electronics. However, its documentation is only available in Japanese, as its main customer is Toyota Motor Corporation.
Renesas: RV850 (documents are in Japanese only)[194]
Most of the compilers, for both for the V850 family and the RH850 family, are exactly the same product, and extended ISA targets are controlled by command line options.[215][216]
Compilers for the V850 family and the RH850 family include:
N-Wire and N-Trace[260][255][261][262] is a JTAG-based debugging interface specification, which circuit implementation is called TAP Controller (Test Access Port controller),[263] primarily compiled by Philips N.V. (currently NXP Semiconductors). But it is perhaps not disclosed publicly in its earlier stage. As the result, each semiconductor and in-circuit emulator vendor implemented similar interfaces independently. Nowadays, it is standardized by IEEE 1149.1 Working Group.[264]
Renesas
E1 Emulator:[265]USB 2.0 based affordable compact housing equipment.
A gang writer, or a gang programmer, is an old terminology for programmable ROMwriters, or programmers. Its name comes from that it steals the binary code from one device, and write it to several others simultaneously. This read device is sometimes called a master device. For mass production use, a dedicated attachment board with "a set of sockets", i.e. "a gang", is needed. As usual, instead of a programmed master device, an object code file can be copied from a PC via download cable, or from a USB stick. Most gang writers accept ASCII-format files such as Intel HEX and Motorola SREC, or binary format files such as ELF.
Minato Holdings, Inc. (in Japanese)[281] is a Japanese company that started as an automated test equipment vendor for memory LSIs. Nowadays, it provides flash ROM programming services for various devices, including V850 and RH850, with its own gang writers and full automatic device handler machines.
On board programming with ICE
Most JTAG-based in-circuit emulators have an on board flash ROM programming function via a debug port, which may be according to IEEE standard 1532-2002, a standard for in-system configuration of programmable components.[282]
Direct connection via RS-232C
If the target board has a RS-232C connector and a transceiver (driver/receiver) IC, such as ICL32xx,[283] for the UARTx peripheral function of V850 device, flash ROM programming with a directly connected PC might be available (depends on devices[284]:16–24 ). The Renesas Flash Programmer software V2[285] or V3[286] is required.
Dedicated on board programmer
On-board programming is also available via UARTx or CSIx+HS peripherals on V850 devices by using dedicated programmer hardware (depends on devices[284]:16–24).
To program V851[288]:11,14–20 and V852,[289]:11,14–20 an ancient PROM programmer with dedicated adapter is required.
Renesas PG-1500 (obsoleted)
Renesas PG-1500[290] is a programmable ROM writer compatible with 27C1001A[291] devices, UV EPROM, or one-time PROM (OTP). This writer reads a silicon signature[292][293] from each device before programming, by asserting 12.5V to the A9 (address #9) terminal. It must NOT be used for modern flash ROM burning.
Gray zone tools
Some gray zone hacking tools exist for V850 on car dashboards.
1 2 3 4 Harigai, Hisao; Kusuda, Masaori; Kojima, Shingo; Moriyama, Masatoshi; Ienaga, Takashi; Yano, Yoichi (1992-10-22). "低消費電力・低電圧動作の32ビットマイクロプロセッサV810"[A low power consumption and low voltage operation 32-bit RISC Microprocessor](PDF). SIG Technical Reports, Information Processing Society of Japan. 1992 (82 (1992-ARC-096)): 41–48. Abstract: An advanced 32-bit RISC microprocessor for embedded control; V810 is introduced in this paper. The V810 has high performance and application specified functions. V810 dissipates less power than any other RISC chips. The V810 is the first 32-bit RISC microprocessor that operates at 2.2 V. The V810 chip is fabricated by using 0.8 μm CMOS double metal layer process technology to integrate 240,000 transistors on a 7.7×7.7 mm2 die.
↑ Naito, Yukihiro; Hikishima, Naoki; Ohta, Yoshiaki; Hatabu, Atsushi; Kuroda, Ichiro (20 April 2001). "W-CDMA端末用ビデオフォン"[Video-Phone for W-CDMA Terminal](PDF). The Journal of the Institute of Image Information and Television Engineers (in Japanese). 55 (4): 497–498. doi:10.3169/itej.55.497. ISSN1881-6908.
↑ Yun Chan Cho; Jae Wook Jeon (2007). "Current software platforms on mobile phone". 2007 International Conference on Control, Automation and Systems. pp.1862–1867. doi:10.1109/ICCAS.2007.4406649. S2CID16120691.
↑ Kaneko, Yasunori; Fumio, Suto; Umeda, Koji; Shiraishi, Mitsutaka; Shirota, HIrobumi; Suka, Takeya (2002-04-25). "デジタル・ムーバN503iS HYPERの開発"[Development of Digital Mova N503iS HYPER.]. NEC Technical Journal (in Japanese). 55 (4): 156–159. ISSN0285-4139.
↑ Kayama, Naoyuki; Mizoguchi, Tamiyuki; Ehara, Tatsuji; Osawa, Takeshi; Umezawa, Atsushi; Yamada, Yasuyoshi (2003-03-10). "ムーバN504iSの開発"[Development of Mova N504iS.]. NEC Technical Journal (in Japanese). 56 (2): 52–55. ISSN0285-4139.
↑ Yamashita, Masayoshi; Takenaka, Hidetoshi; Inoue, Jiro; Terada, Shigehiro; Yamada, Hironori; Akiyama, Makoto (2003-09-25). "ムーバN505iの開発"[Development of mova N505i]. NEC Technical Journal (in Japanese). 56 (8). NEC: 33–37. ISSN0285-4139. 200902227791143957.
↑ Nonaka, Yoshiya; Denda, Akihiro; Uesaka, Gakuji; Sakamoto, Yuji; Nii, Noritaka; Satou, Masahiro; Endo, Kazuaki; Katou, Hiroki; Sugino, Ryouji; Sada, Takeshi; Endo, Koji; Nishigata, Junko; Ishiyama, Kunihiro; Morita, Kenji (2002). "HDD-DEH のソフトウェア開発"[Software Development of CD/MP3/Memory Stick Player with HDD](PDF). Pioneer R&D (in Japanese). 12 (3). Pioneer Corporation: 26–38. Summary: We developed this product which carries new functions, CD( includes MP3CD playback), MagicGate Memory Stick (recording & playback & updating) and HDD (recording & playback), for the first time as a car audio product. This product for the worldwide market is packed into 1DIN size, with standard features (AM/FM Tuner, MOS-FET50Wx4ch amplifier, OrganicEL display, and sound field control DSP) and the new functions. We considered the operation carefully to handle many music files in the HDD easily. We concentrated on making a new field of audio entertainment, and we were the first to introduce this system on the car audio market.
↑ Suzuki, Hiroaki; Suzuki, Chika; Kimura, Akiko; Sato, Syoichiro; Ide, Syuichi; Sakanaka, Yasuhide (1993-01-22). "A 32 - Bit RISC Microprocessor V810 and its design techniques"(PDF). SIG SLDM Technical Reports. 1992-SLDM-065 (in Japanese). 1993 (6). Information Processing Society of Japan: 155–162. AA11451459. Abstract: An advanced 32-bit RISC microprocessor for embedded controls; V810 and its design technique are described in this paper. The V810 is fabricated by using 0.8μm CMOS double metal layer process technology to integrate 240,000 transistors on a 7.7×7.7mm2 die. In design of the V810, we used design automation techniques. The V810 was analyzed for logical correctness and timing constraint before fabrication. Finally, V810 executed realtime-OS and SPEC benchmarks correctly at first silicons.
↑ Akaboshi, Hiroki; Yasuura, Hiroto (8 March 1995). "Design Comparison of Hardware Description Languages in RT Level"(PDF). IPSJ SIG Notes (in Japanese). 1995 (24 (1994-SLDM-074)). Information Processing Society of Japan: 57–64. Retrieved 23 September 2022. Abstract: Progress of logic/layout synthesis makes it possible to design circuits by Hardware Description Languages (HDLs). When a designed circuit is small, it is synthesized automatically from HDL description. In this paper, to make it clear what kinds of problems are there in designing a large circuit looks like a processor, we design a processor and some components of it by HDLs in RT level and evaluate circuits synthesized by a logic/layout synthesis tool.
↑ Yano, Yoichi (April 2012). "32ビット・マイコン「V60」開発物語"[Development story of the V60; a 32-bit microprocessor](PDF). Encor (in Japanese) (75). Society of Semiconductor Industry Specialists: 17–20.
↑ Inasaka, Jun; Ikeda, Rikikazu; Umezawa, Kazuhiko; Yoshikawa, Ko; Yamada, Shitaka; Kitawaki, Shigemune (January 2003). "Hardware Technology of the Earth Simulator"(PDF). NEC Research and Development. Architecture and Hardware for HPC. 44 (1): 27–36.
↑ Jansen, Dirk (2010-02-23). The Electronic Design Automation Handbook. Springer Science & Business Media. p.54. ISBN9780387735436. Design Architect by Mentor Graphics Corporation with programs NETED and SYMED. This system is the most universal one of the three [3.3]. Version C1 on HP Unix V10.20 is used (short form MENTOR)
↑ Engblom, Jakob (2003). "Embedded Systems Computer Architecture"(PDF). Extended Abstract from ESSES 2003. S2CID15760973. Archived from the original(PDF) on 2018-02-25. Code size is an important factor in most embedded designs, and instruction sets are designed and extended with code size in mind. Fairly typically, the NEC V850 architecture uses 16-, 32-, 48-bit, and 64-bit instructions to encode a RISC-style instruction set. The 32-bit ARM and MIPS architecture have been extended with reduced 16-bit instruction sets in order to reduce the code size. Instructions that perform a lot of work, like loading multiple values from the stack, are popular to reduce code size.
↑ Kaneko, Hiroaki; Sakurai, Yoshikazu; Nasu, Masaki; Katsuta, Hiroshi; Nagasaki, Kazunori; Hiiragizawa, Yasunori; Sonobe, Satoru; Onishi, Tatsuro; Tokunaga, Kei (March 1995). "高性能・低消費電力動作の32ビットRISCシングルチップマイクロコンピュータV851"[High Performance and Low-Power-Consumption 32-bit RISC Single Chip Microcomputer V851.]. NEC Technical Journal. Special Issue on Semiconductor Devices. (in Japanese). 48 (3). NEC Corporation: 42–48. ISSN0285-4139.
↑ Yamagata, Yasushi; Ishibashi, Takashi; Sano, Yuichi; Koga, Yoshikazu; Yoshida, Miho; Sugo, Akihisa (April 1996). "32ビットRISCマイクロコントローラV853"[32-bit RISC Microcontroller V853.]. NEC Technical Journal. Special Issue: Semiconductor Devices. (in Japanese). 49 (3). NEC Corporation: 55–60. ISSN0285-4139.
1 2 Krämer, Michael (2011-01-21). "Latest 32-bit RISC architecture for automotive expands functionality". EE Times. All V850 products are upwards compatible. As a result, today's sophisticated components can still execute the same instructions as their forebears. The architecture has undergone continual improvements with extensions to the instruction set, and today it offers computing power of up to 2.6 Dhrystone MIPS/MHz. Further performance increases can be achieved by integrating several of these processor cores on a single chip, delivering twice or even four times more computing power.
↑ Aoki, Yayoi (2001-11-30). "US 6,948,034 B2; Method for use of stack"(PDF). pdfpiw.uspto.gov. The present invention relates to a method for use of a stack in a Java accelerator device.
↑ Mine, Kazumasa (2000-11-21). "US 7,200,741 B1: Microprocessor having main processor and co-processor"(PDF). pdfpiw.uspto.gov. United States Patent and Trademark Office. With such arrangement, the microprocessor can flexibly deal with various kinds of instruction sets with different architectures such as an instruction set for an interpreter language for realizing a virtual machine for Java and an instruction set for emulating another microprocessor.
↑ Harigai, Hisao; Kusuda, Masahiro; Kojima, Shingo; Moriyama, Masatoshi; Ienaga, Takashi; Yano, Yoichi (1992-10-22). "A low power consumption and low voltage operation 32-bit RISC Microprocessor"(PDF). SIG ARC Technical Reports (in Japanese). 1992 (82 (1992-ARC-096)). Information Processing Society of Japan: 41–48. AN10096105. Abstract: An advanced 32-bit RISC microprocessor for embedded control; V810 is introduced in this paper. The V810 has high performance and application specified functions. V810 dissipates less power than any other RISC chips. The V810 is the first 32-bit RISC microprocessor that operates at 2.2 V. The V810 chip is fabricated by using 0.8 μm CMOS double metal layer process technology to integrate 240,000 transistors on a 7.7×7.7 mm2 die.
↑ Kusuda, Masahiro; Hirai, Miho; Suzuki, Hiroaki; Daito, Masayuki; Suzuki, Chika; Kimura, Akiko; Demura, Shigeki; Ishibashi, Takashi; Sato, Syoichiro (September 1992). "低消費電力・低電圧動作のオリジナル32ビットRISCマイクロプロセッサV810"[V810-Low Power Consumption and Low Voltage Operation 32-bit RISC Microprocessor.](image/jp2). NEC Technical Journal (in Japanese). 45 (8). NEC Corporation: 66–73. ISSN0285-4139. 000000018731.
1 2 3 Suzuki, Hiroaki; Sakai, Toshichika; Harigai, Hisao; Yano, Yoichi (1995-04-25). "A 0.9-V, 2.5MHz CMOS 32-bit Microprocessor". IEICE Transactions on Electronics. E78-C (4): 389–393. ISSN0916-8516. Retrieved 2018-01-09. Summary: A 32-bit RISC microprocessor "V810" that has 5-stage pipeline structure and a 1 Kbyte, direct-mapped instruction cache realizes 2.5MHz operation at 0.9 V with 2.0 mW power consumption. The supply voltage can be reduced to 0.75 V. To overcome narrow noise margin, all the signals are set to have rail-to-rail swing by pseudo-static circuit technique. The chip is fabricated by a 0.8 μm double metal-layer CMOS process technology to integrate 240,000 transistors on a 7.4 × 7.1 mm die.
↑ "NEC narrows gate length below 0.10 micron | EE Times". EETimes. 2000-10-31. NEC also will provide internally-developed V850E and VRx CPUs, though Mabuchi said he believes NEC will need to license the ARM9 core to address the market for mobile terminals.
↑ Nishiguchi, Nobuyuki (2001-02-02). "システムLSIの未来は、NECが拓く –設計環境の現状と今後–"[System LSI Design Envilonments, Today and the Future](PDF) (in Japanese). NEC Corporation.
↑ Mizuhashi, Yukiko; Teramoto, Msanoro (August 1989). "Real-time UNIX operating system: RX-UX 832". Microprocessing and Microprogramming. 27 (1–5): 533–538. doi:10.1016/0165-6074(89)90105-1. Abstract: This paper describes requirements for real-time UNIX operating systems, design concept and the implementation of RX-UX 832 real-time UNIX operating system for v60/v70 microprocessor which are NEC's 32-bit microprocessors. RX-UX 832 is implemented adopting the building block structure, composed of three modules, real-time kernel, file-server and Unix supervisor. To guarantee a real-time responsibility, several enhancements were introduced such as, fixed priority task scheduling scheme, contiguous block file system and fault tolerant functions. Thus, RX-UX 832 allows system designers to use standard Unix as its man-machine interface to build fault tolerant systems with sophisticated operability and provides high-quality software applications on the high performance microchips.
↑ Bunk, Adrian; Torvalds, Linus (2008-07-24). "remove the v850 port". git.kernel.org. Trying to compile the v850 port brings many compile errors, one of them exists since at least kernel 2.6.19. There also seems to be no one willing to bring this port back into a usable state. This patch therefore removes the v850 port. If anyone ever decides to revive the v850 port the code will still be available from older kernels, and it wouldn't be impossible for the port to reenter the kernel if it would become actively maintained again.
↑ "Industry Solution Automotive"(PDF). www.sysgo.com. SYSGO AG. "We have developed a virtualization technology for our V850 architecture to control multiple systems on a single CPU core with no mutual interference, allowing high speed and composite control for industrial machinery and automotive, where real-time is essential. SYSGO enables us to achieve a scalable CPU architecture with virtualization technology that supports our customers in building flexible development systems." Michiya Nakamura, General Manager, 1st MCU Business Division, Renesas Electronic Corporation
↑ "Wind River Diab Compiler Achieves Automotive SPICE Level 2 and New Enhancements Speed Development for Safe Vehicle Systems". www.windriver.com. Windriver Systems. 2013-11-04. NEWS HIGHLIGHTS •Development process for Wind River Diab Compiler achieves Automotive SPICE Process Capability Level 2 certification. •New Wind River Diab Compiler ISO 26262 Qualification Kit guides customers in qualifying Diab Compiler for safety-related projects. •Diab Compiler adds support for Renesas RH850 family microcontrollers.
1 2 PARTNER Users Manual "V800 Series Common Edition"(PDF) (2.20ed.). Midas lab. Inc. May 2000. PARTNER Overview PARTNER is a Window based source level debugger, which is developed as PARTNERWin by Kyoto Micro Computer Co., Ltd., and ported for the products of Midas lab Inc. In addition to the basic functions as a source level debugger tool, such as program load, program execution, break point control, data display/change, code display/change, there are other functions customized for Midas lab products.
↑ "IDT JTAG/EJTAG Devices"(PDF). Integrated Device Technology, Inc. 2000. The vast majority of the competition's offerings have included a JTAG Test Access Port (TAP). Recently, products have been arriving with more enhanced capabilities, such as N-Wire/N-Trace from NEC, RISCWatch from IBM, and COP from Motorola. These versions of Enhanced JTAG perform relatively the same functions and use the traditional JTAG TAP with a couple additional pins for greater control.
A microprocessor is a computer processor for which the data processing logic and control is included on a single integrated circuit (IC), or a small number of ICs. The microprocessor contains the arithmetic, logic, and control circuitry required to perform the functions of a computer's central processing unit (CPU). The IC is capable of interpreting and executing program instructions and performing arithmetic operations. The microprocessor is a multipurpose, clock-driven, register-based, digital integrated circuit that accepts binary data as input, processes it according to instructions stored in its memory, and provides results as output. Microprocessors contain both combinational logic and sequential digital logic, and operate on numbers and symbols represented in the binary number system.
A microcontroller or microcontroller unit (MCU) is a small computer on a single integrated circuit. A microcontroller contains one or more CPUs along with memory and programmable input/output peripherals. Program memory in the form of NOR flash, OTP ROM, or ferroelectric RAM is also often included on the chip, as well as a small amount of RAM. Microcontrollers are designed for embedded applications, in contrast to the microprocessors used in personal computers or other general-purpose applications consisting of various discrete chips.
SuperH is a 32-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Hitachi and currently produced by Renesas. It is implemented by microcontrollers and microprocessors for embedded systems.
Renesas Electronics Corporation is a Japanese semiconductor manufacturer headquartered in Tokyo, Japan, initially incorporated in 2002 as Renesas Technology, the consolidated entity of the semiconductor units of Hitachi and Mitsubishi excluding their dynamic random-access memory (DRAM) businesses, to which NEC Electronics merged in 2010, resulting in a minor change in the corporate name and logo to as it is now.
μClinux is a variation of the Linux kernel, previously maintained as a fork, that targets microcontrollers without a memory management unit (MMU). It was integrated into the mainline kernel as of 2.5.46; the project continues to develop patches and tools for microcontrollers. The homepage lists Linux kernel releases for 2.0, 2.4 and 2.6.
4-bit computing is the use of computer architectures in which integers and other data units are 4 bits wide. 4-bit central processing unit (CPU) and arithmetic logic unit (ALU) architectures are those that are based on registers or data buses of that size. A group of four bits is also called a nibble and has 24 = 16 possible values, with a range of 0 to 15.
Blackfin is a family of 16-/32-bit microprocessors developed, manufactured and marketed by Analog Devices. The processors have built-in, fixed-point digital signal processor (DSP) functionality performed by 16-bit multiply–accumulates (MACs), accompanied on-chip by a microcontroller. It was designed for a unified low-power processor architecture that can run operating systems while simultaneously handling complex numeric tasks such as real-time H.264 video encoding.
The M32R is a 32-bit RISC instruction set architecture (ISA) developed by Mitsubishi Electric for embedded microprocessors and microcontrollers. The ISA is now owned by Renesas Electronics Corporation, and the company designs and fabricates M32R implementations. M32R processors are used in embedded systems such as Engine Control Units, digital cameras and PDAs. The ISA was supported by Linux and the GNU Compiler Collection but was dropped in Linux kernel version 4.16. GCC removed support for this architecture in the GCC 12.1 release.
The R3000 is a 32-bit RISC microprocessor chipset developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture (ISA). Introduced in June 1988, it was the second MIPS implementation, succeeding the R2000 as the flagship MIPS microprocessor. It operated at 20, 25 and 33.33 MHz.
AVR32 is a 32-bit RISC microcontroller architecture produced by Atmel. The microcontroller architecture was designed by a handful of people educated at the Norwegian University of Science and Technology, including lead designer Øyvind Strøm and CPU architect Erik Renno in Atmel's Norwegian design center.
IEBus is a communication bus specification "between equipments within a vehicle or a chassis" of Renesas Electronics. It defines OSI model layer 1 and layer 2 specification. IEBus is mainly used for car audio and car navigations, which established de facto standard in Japan, though SAE J1850 is major in United States. IEBus is also used in some vending machines, which major customer is Fuji Electric. Each button on the vending machine has an IEBus ID, i.e. has a controller. Detailed specification is disclosed to licensees only, but protocol analyzers are provided from some test equipment vendors. Its modulation method is PWM with 6.00 MHz base clock originally, but most of automotive customers use 6.291 MHz, and physical layer is a pair of differential signalling harness. Its physical layer adopts half-duplex, asynchronous, and multi-master communication with carrier-sense multiple access with collision detection (CSMA/CD) for medium access control. It allows for up to fifty units on one bus over a maximum length of 150 meters. Two differential signalling lines are used with Bus+ / Bus− naming, sometimes labeled as Data(+) / Data(−).
The NEC V60 is a CISC microprocessor manufactured by NEC starting in 1986. Several improved versions were introduced with the same instruction set architecture (ISA), the V70 in 1987, and the V80 and AFPP in 1989. They were succeeded by the V800 product families, which is currently produced by Renesas Electronics.
The history of general-purpose CPUs is a continuation of the earlier history of computing hardware.
RL78 Family is a 16-bit CPU core for embedded microcontrollers of Renesas Electronics introduced in 2010.
Since 1985, many processors implementing some version of the MIPS architecture have been designed and used widely.
78K is the trademark name of 16- and 8-bit microcontroller family manufactured by Renesas Electronics, originally developed by NEC started in 1986. The basis of 78K Family is an accumulator-based register-bank CISC architecture. 78K is a single-chip microcontroller, which usually integrates; program ROM, data RAM, serial interfaces, timers, I/O ports, an A/D converter, an interrupt controller, and a CPU core, on one die.
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