COP8

Last updated
National Semiconductor COP8
General information
Launched1988;36 years ago (1988)
Common manufacturer
Performance
Max. CPU clock rate to 15 MHz
Data width8 (RAM), 8 (ROM)
Address width8 (RAM), 15 (ROM)
Architecture and classification
ApplicationEmbedded
Instruction set COP8
Number of instructions69
Physical specifications
Package
  • 20, 28, and 40-pin DIP; 16, 20, and 28 pin SOIC; 44-pin PLCC
History
Predecessor COP400
Successornone

The National Semiconductor COP8 is an 8-bit CISC core microcontroller. COP8 is an enhancement to the earlier COP400 4-bit microcontroller family. COP8 main features are:

Contents

It has a machine cycle of up to 2M cycles per second, but most versions seem to be overclockable to up to 2.8M cycles per second (28 MHz clock).[ citation needed ]

Registers and memory map

COP8 registers
141312111009080706050403020100(bit position)
Main registers
AAccumulator
PCProgram Counter
Note: All other programmer-visible registers and status bits are allocated in RAM.

The COP8 uses separate instruction and data spaces (Harvard architecture). [1] : 2-1  [2] : 2-4  Instruction address space is 15-bit (32 KiB maximum), while data addresses are 8-bit (256 bytes maximum, extended via bank-switching).

To allow software bugs to be caught, all invalid instruction addresses read as zero, which is a trap instruction. Invalid RAM above the stack reads as all-ones, which is an invalid address.

The CPU has an 8-bit accumulator and 15-bit program counter. 16 additional 8-bit registers (R0–R15) and an 8-bit program status word are memory mapped. There are special instructions to access them, but general RAM access instructions may also be used.

The memory map is divided into half RAM and half control registers as follows:

COP8 data address space
AddressesUse
0x00–6FGeneral purpose RAM, used for stack
0x70–7FUnused, reads as all-ones (0xFF) to trap stack underflows
0x80–8FUnused, reads undefined
0x90–BFAdditional peripheral control registers
0xC0–CFPeripheral control registers.
0xD0–DFGeneral purpose I/O ports L, G, I, C and D
0xE0–E8Reserved
0xE9 Microwire shift register
0xEA–EDTimer 1 registers
0xEECNTRL register, control bits for Microwire & Timer 1
0xEFPSW, CPU program status word
0xF0–FBR0–R11, general purpose registers (additional RAM)
0xFCR12, a.k.a. X, secondary indirect pointer register
0xFDR13, a.k.a. SP, stack pointer register
0xFER14, a.k.a. B, primary indirect pointer register
0xFFR15, a.k.a. S, data segment extension register

If RAM is not banked, then R15 (S) is just another general-purpose register. If RAM is banked, then the low half of the data address space (addresses 0x00–7F) is directed to a RAM bank selected by S. The special purpose registers in the high half of the data address space are always visible. The data registers at 0xFx can be used to copy data between banks.

RAM banks other than bank 0 have all 128 bytes available. The stack (addressed via the stack pointer) is always on bank 0, no matter how the S register is set.

Control transfers

In addition to 3-byte JMPL and JSRL instructions which can address the entire address space, 2-byte versions of these instructions, JMP and JSR, can jump within a 4K page. The instruction specifies the low 12 bits, and the high 3 bits of the PC are preserved. (These are intended primarily for models with up to 4K of ROM.) For short-distance branches, there are 63 1-byte instructions, JP, which perform PC-relative branches from PC−32 to PC+31. This is a 15-bit addition, and no page boundary requirements apply.

There are also jump indirect and load accumulator indirect instructions which use the accumulator contents as the low 8 bits of an address; the high 7 bits of the current PC are preserved.

Conditional branches per se do not exist, nor does the processor provide the traditional ZCVN status flags, although the program status word contains carry and half-carry flags for multi-byte arithmetic. Rather, there are a number of compare-and-skip instructions. For example, IFEQ compares its two operands, and skips the following instruction if they are unequal. Any instruction may be skipped; it is not limited to branches.

A feature unique to the COP8 architecture is the IFBNE instruction. This compares the low 4 bits of the B (memory pointer) register with a 4-bit immediate constant, and can be used to loop until B has reaches the end of a small (up to 16 byte) buffer.

An interesting extension of this mechanism is the RETSK return-and-skip instruction, which lets any subroutine call conditionally skip the following instruction. This provides a very compact way to return a boolean value from a subroutine.

Instruction set

COP8 operands are listed in destination, source order. Most instructions have the accumulator A as one of the operands. The other operand is generally chosen from an 8-bit immediate value, an 8-bit RAM address, or [B], the RAM address selected by the B register. Some instructions also support RAM addressing by the X register ([X]), and post-inc/decrement variants ([B+], [B−], [X+], [X−]).

Indirect addressing via B is particularly fast, and can be done in the same cycle that the instruction is executed.

On the other hand, absolute RAM addressing is not directly encoded in most cases. Rather, a special "direct addressing" prefix opcode, followed by a 1-byte address, may precede any instruction with a [B] operand, and changes it to a memory direct operand. This adds two bytes and three cycles to the instruction. (Conditional-skip instructions skip the prefix and following instruction as a pair.)

All "move" instructions are called LD (load) even if the destination is a memory address. Unusually, there are no LD instructions with the accumulator as a source; stores are done with the X instruction which exchanges the accumulator with the memory operand, storing A and loading the previous memory contents. (This takes no additional time; X A,[B] is a one-cycle instruction.)

There are instructions to fetch from tables in ROM. These combine the high 7 bits of the program counter (PCU) with the accumulator, fetch a byte from that address, and place it in the accumulator (LAID instruction) or the low 8 bits of the program counter PCL (JID instruction). Because the next instruction executed must be in the same 256-byte page of ROM as the table itself, a 256-entry table is not possible.

COP8 family instruction set [1] [3] [2] [4]
OpcodeOperandsMnemonicCyclesDescription
76543210b2b3
00000000——INTR7Software interrupt (push PC, PC ← 0x00ff)
000offset——JP +disp53PC ← PC + offset; jump 1–31 bytes forward (offset=0 reserved)
0010addrhiaddrlo—JMP addr123PC[11:0] ← address. Top 3 bits of PC preserved.
0011addrhiaddrlo—JSR addr125Jump to subroutine: push PC, proceed as JMP.
0100k——IFBNE #imm41Execute next instruction if (B & 15) ≠ k; skip if (B & 15) = k.
0101k——LD B,#imm41B ← 15 − k (zero-extended)
01100000k—ANDSZ A,#imm8*2Skip if A & k = 0 (=IFBIT #bit,A)
01100001addrlo—JSRB addr8†5Push PC, jump to boot ROM subroutine at address [5]
0110001–——(reserved for boot ROM†) [5]
01100100——CLR A1A ← 0
01100101——SWAP A1A ← A<<4 | A>>4; swap nibbles
01100110——DCOR A1Decimal correct after BCD addition
01100111——PUSH A*3[SP] ← A, SP ← SP−1
01101bit——RBIT #bit,[B]1Reset (clear to 0) given bit of RAM
01110bit——IFBIT #bit,[B]1Test given bit of RAM, skip if zero
01111bit——SBIT #bit,[B]1Set (to 1) given bit of RAM
100m0opcodeoperand—ALU operations, A ← A op operand
10000opcode——OP A,[B]1ALU operation with A and [B] (with [address] using DIR prefix)
10010opcodek—OP A,#imm82ALU operation with A and immediate k
100m0000operand—ADC A,operandC,A ← A + operand + C; add with carry
100m0001operand—SUBC A,operandC,A ← A + ~operand + C (A − operand − ~C)
100m0010operand—IFEQ A,operandSkip if A ≠ operand
100m0011operand—IFGT A,operandSkip if A ≤ operand
100m0100operand—ADD A,operandA ← A + operand (carry unchanged!)
100m0101operand—AND A,operandA ← A & operand
100m0110operand—XOR A,operandA ← A ^ operand
100m0111operand—OR A,operandA ← A |operand
10001000——IFC1Skip if carry clear
10001001——IFNC1Skip if carry set
10001010——INC A1A ← A + 1 (carry unchanged)
10001011——DEC A1A ← A − 1 (carry unchanged)
10001100——POP A*3SP ← SP+1, A ← [SP]
10001101——RETSK5Pop PC, skip one instruction
10001110——RET5Pop PC high, pop PC low
10001111——RETI5Return and enable interrupts
10011000k—LD A,#imm82A ← k
10011001k—IFNE A,#imm8*2Skip if A = k
10011010k—LD [B+],#imm83[B] ← k, B ← B + 1
10011011k—LD [B−],#imm83[B] ← k, B ← B − 1
10011100address—X A,addr83A ↔ [address], exchange
10011101address—LD A,addr83A ← [address]
10011110k—LD [B],#imm82[B] ← k
10011111k—LD B,#imm8*2B ← k (one cycle faster than LD R14,#k)
10100000——RC1C ← 0; reset carry to 0
10100001——SC1C ← 1; set carry to 1
10100010——X A,[B+]2A ↔ [B], B ← B+1
10100011——X A,[B−]2A ↔ [B], B ← B−1
10100100——LAID3A ← ROM[PCU:A]; load from ROM
10100101——JID3PCL ← ROM[PCU:A]; jump via ROM table
10100110——X A,[B]1A ↔ [B]
10100111——(reserved)
10101000——RLC A*1C,A ← A,C; rotate left through carry (=ADC A,A)
10101001addresskIFEQ addr8,#imm8*3Skip if [address] ≠ k
10101010——LD A,[B+]2A ← [B], B ← B+1
10101011——LD A,[B−]2A ← [B], B ← B−1
10101100addrhiaddrloJMPL addr154PC ← address
10101101addrhiaddrloJSRL addr155Push PC, PC ← address
10101110——LD A,[B]1A ← [B]
10101111——(reserved)
10110000——RRC A1A,C ← C,A; rotate right through carry
10110001——(reserved)
10110010——X A,[X+]3A ↔ [X], X ← X+1
10110011——X A,[X−]3A ↔ [X], X ← X−1
10110100——VIS*5PC ← ROM[vector table]; Vector Interrupt Select
10110101——RPND*1Reset pending interrupt flag
10110110——X A,[X]3A ↔ [X]
10110111——(reserved)
10111000——NOP1No operation
10111001——IFNE A,[B]*1Skip if A = [B]
10111010——LD A,[X+]3A ← [X], X ← X+1
10111011——LD A,[X−]3A ← [X], X ← X−1
10111100addresskLD addr8,#imm83[address] ← k
10111101address—DIR addr83Change next instruction's operand from [B] to [address]
10111110——LD A,[X]3A ← [X]
10111111——(reserved)
1100register——DRSZ register3register ← register − 1, skip if result is zero
1101registerk—LD register,#imm83register ← k (=LD 0xf0+register,#k, one byte shorter)
111offset——JP −disp53PC ← PC − 32 + offset; jump 1–32 bytes backward
76543210b2b3MnemonicCyclesDescription

*: Only on "feature family" (COP888/COP8SA) cores; not present on "basic family" (COP800) cores.
†: Only on "flash family" (COP8TA/COP8C) models with boot ROM for in-system programming

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References

  1. 1 2 COP8 Basic Family User's Manual (PDF). Revision 002. National Semiconductor. June 1996. Literature Number 620895-002. Retrieved 2021-01-02.
  2. 1 2 Aleaf, Abdul (July 1996). "Comparison of COP878x to the Enhanced COP8SAx7 Family - Hardware/Software Considerations" (PDF). National Semiconductor. Application Note 1043.
  3. ↑ COP8 Feature Family User's Manual. Revision 005. National Semiconductor. March 1999. Literature Number 620897-005. Extracted from zipped ISO image 530094-003_COP8_Tools_Docs_Aug1999.zip, retrieved 2020-01-07.
  4. ↑ "COP8SAx Designer's Guide" (PDF). National Semiconductor. January 1997. Literature Number 620894-001.
  5. 1 2 "COP8SBR9/COP8SCR9/COP8SDR98-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout" (PDF) (data sheet). National Semiconductor. April 2002. Retrieved 2021-01-06.
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