Program status word

Last updated

The program status word [lower-alpha 1] (PSW) is a register that performs the function of a status register and program counter, and sometimes more. The term is also applied to a copy of the PSW in storage. This article only discusses the PSW in the IBM System/360 [1] and its successors, [2] [3] [4] [5] [6] and follows the IBM convention of numbering bits starting with 0 as the leftmost (most significant) bit.

Contents

Although certain fields within the PSW may be tested or set by using non-privileged instructions, testing or setting the remaining fields may only be accomplished by using privileged instructions.

Contained within the PSW are the two bit condition code, representing zero, positive, negative, overflow, and similar flags of other architectures' status registers. Conditional branch instructions test this encoded as a four bit value, with each bit representing a test of one of the four condition code values, 23 + 22 + 21 + 20. (Since IBM uses big-endian bit numbering, mask value 8 selects code 0, mask value 4 selects code 1, mask value 2 selects code 2, and mask value 1 selects code 3.)

The 64-bit PSW describes (among other things)

In the early instances of the architecture (System/360 and early System/370), the instruction address was 24 [lower-alpha 2] bits; in later instances (XA/370), the instruction address was 31 bits plus a mode bit (24 bit addressing mode if zero; 31 bit addressing mode if one) for a total of 32 bits.

In the present instances of the architecture (z/Architecture), the instruction address is 64 bits and the PSW itself is 128 bits.

The PSW may be loaded by the LOAD PSW instruction (LPSW or LPSWE). Its contents may be examined with the Extract PSW instruction (EPSW).

Format

S/360

On all but 360/20, [lower-alpha 3] the PSW has the following formats. S/360 Extended PSW format only applies to the 360/67 with bit 8 of control register 6 set.

IBM S/360 PSW formats
S/360 Standard PSW [11]

System MaskKeyAMWPInterruption Code [12]
07811121314151631

ILCCCProgram
Mask		Instruction Address
3233343536394063
S/360 Standard PSW abbreviations
BitsFieldMeaning
0-7SM
System Mask
BitMeaning
0Channel 0 mask
1Channel 1 mask
2Channel 2 mask
3Channel 3 mask
4Channel 4 mask
5Channel 5 mask
6Channel 6 mask
7External Mask
8-11KeyPSW key
12AASCII
13MMachine-check mask
14WWait state
15PProblem state
16-31ICInterruption Code [13]
32-33ILCInstruction-Length Code [14]
34-35CCCondition Code
36-39PM
Program Mask
BitMeaning
36Fixed-point overflow
37Decimal overflow
38Exponent underflow
39Significance
40-63IAInstruction Address
S/360 Extended PSW [15]

spare24/32
Bit
Mode		Tran
Ctrl		I/O
Mask		Ext.
Mask		KeyAMWPILCCCProgram
Mask		spare
034567811121314151617181920232431

Instruction Address
3263
S/360 Extended PSW abbreviations
BitsFieldMeaning
0-3Spare (must be 0)
424/32-bit Address mode
5Translation Control
6IOI/O Mask (Summary)
7EXExternal Mask (Summary)
8-11KeyProtection Key
12AASCII
13MMachine-check mask
14WWait state
15PProblem state
16-17ILCInstruction-Length Code [16]
18-19CCCondition Code
20-23PM
Program Mask
BitMeaning
20Fixed-point overflow
21Decimal overflow
22Exponent underflow
23Significance
24-31Spare
32-63IAInstruction Address

S/370

IBM S/370 PSW formats
S/370 Basic Control mode PSW [17]

Chan.
Mask		I
O		E
X		Key0MWPInterruption Code
0124567811121314151631

ILCCCProgram
Mask		Instruction Address
3233343536394063
S/370 BC mode PSW abbreviations
BitsFieldMeaning
0-5Channel Masks for channels 0-5
6IOI/O Mask for channels > 5
7EXExternal Mask
8-11KeyPSW key
12E=0Basic Control mode
13MMachine-check mask
14WWait state
15PProblem state
16-31ICInterruption Code [18]
32-33ILCInstruction-Length Code [19]
34-35CCCondition Code
36-39PM
Program Mask
BitMeaning
36Fixed-point overflow
37Decimal overflow
38Exponent underflow
39Significance
40-63IAInstruction Address
S/370 Extended Control mode PSW [20]

0R000TI
O		E
X		Key1MWPS0CCProgram
Mask		00000000
0124567811121314151617181920232431

00000000Instruction Address
32394063
S/370 EC mode PSW abbreviations
BitsFieldMeaning
1RPER Mask
5TDAT mode
6IOI/O Mask; subject to channel mask in CR2
7EXExternal Mask; subject to external subclass mask in CR0
8-11KeyPSW key
12E=1Extended Control mode
13MMachine-check mask
14WWait state
15PProblem state
16SAddress-Space Control
0=primary-space mode
1=Secondary-space mode
18-19CCCondition Code
20-23PM
Program Mask
BitMeaning
20Fixed-point overflow
21Decimal overflow
22Exponent underflow
23Significance
40-63IAInstruction Address

S/370 Extended Architecture (S/370-XA)

IBM Extended Architecture (XA) PSW format
Extended Architecture Extended Control mode PSW [21]

0R000TI
O		E
X		Key1MWPS0CCProgram
Mask		00000000
0124567811121314151617181920232431

AInstruction Address
323363
S/370-XA EC mode PSW abbreviations
BitsFieldMeaning
1RPER Mask
5TDAT mode
6IOI/O Mask; subject to channel mask in CR2
7EXExternal Mask; subject to external subclass mask in CR0
8-11KeyPSW key
12E=1Extended Control mode
13MMachine-check mask
14WWait state
15PProblem state
16SAddress-Space Control
0=primary-space mode
1=Secondary-space mode
18-19CCCondition Code
20-23PM
Program Mask
BitMeaning
20Fixed-point overflow
21Decimal overflow
22Exponent underflow
23Significance
32AAddressing mode
0=24 bit; 1=31 bit
33-63IAInstruction Address

Enterprise Systems Architecture (ESA)

IBM Enterprise Systems Architecture (ESA) PSW format
Enterprise Systems Architecture Extended Control mode PSW [22] [23]

0R000TI
O		E
X		Key1MWPASCCProgram
Mask		00000000
0124567811121314151617181920232431

AInstruction Address
323363
ESA EC mode PSW abbreviations
BitsFieldMeaning
1RPER Mask
5TDAT mode
6IOI/O Mask; subject to channel mask in CR2
7EXExternal Mask; subject to external subclass mask in CR0
8-11KeyPSW key
12E=1Extended Control mode
13MMachine-check mask
14WWait state
15PProblem state
16-17ASAddress-Space Control
00=primary-space mode
01=Access-register mode
10=Secondary-space mode
11=Home-space mode
18-19CCCondition Code
20-23PM
Program Mask
BitMeaning
20Fixed-point overflow
21Decimal overflow
22Exponent underflow [lower-alpha 4]
23Significance [lower-alpha 5]
32AAddressing mode
0=24 bit; 1=31 bit
33-63IAInstruction Address

z/Architecture

IBM z/Architecture PSW formats
z/Architecture long PSW [24]

0R000TI
O		E
X		Key0MWPASCCProgram
Mask		R
I		000000E
A
012456781112131415161718192023243031

B
A		0
323363

Instruction Address
6495

Instruction Address (Continued)
96127
Long PSW abbreviations
BitsFieldMeaning
1RPER Mask
5TDAT mode
6IOI/O mask
7EXExternal Mask
8-11KeyPSW key
12E=0Must be zero for LPSWE
13MMachine-check mask
14WWait state
15PProblem state
16-17ASAddress-Space Control
00=primary-space mode
01=Access-register mode
10=Secondary-space mode
11=Home-space mode
18-19CCCondition Code
20-23PM
Program Mask
BitMeaning
20Fixed-point overflow
21Decimal overflow
22HFP Exponent underflow
23HFP Significance
24RIReserved for IBM
31EAExtended Addressing mode
0=defined by BA below; 1=64-bit, BA must be zero
32BABasic Addressing mode
0=24 or 64; 1=31
64-127IAInstruction Address
z/Architecture short PSW [25]

0R000TI
O		E
X		Key1MWPASCCProgram
Mask		R
I		000000E
A
01245678111213141516171819202324253031

B
A		Instruction Address
323363
Short PSW abbreviations
BitsFieldMeaning
1RPER Mask
5TDAT mode
6IOI/O mask
7EXExternal Mask
8-11KeyPSW key
12E=1Must be one for LPSW
13MMachine-check mask
14WWait state
15PProblem state
16-17ASAddress-Space Control
00=primary-space mode
01=Access-register mode
10=Secondary-space mode
11=Home-space mode
18-19CCCondition Code
20-23PM
Program Mask
BitMeaning
20Fixed-point overflow
21Decimal overflow
22HFP Exponent underflow
23HFP Significance
24RIReserved for IBM
31EAExtended Addressing mode
0=defined by BA below; 1=64-bit, BA must be zero
32BABasic Addressing mode
0=24 or 64; 1=31
33-63IAInstruction Address

Notes

  1. ↑ The nomenclature varies among architectures.
  2. ↑ However, a 360/67 [7] equipped with the Extended Dynamic Address Translation [8] feature has a 32-bit mode selected by bit 4 of the PSW [9] in Extended PSW mode [8] (Control Register 6, bit 8 [10] ).
  3. ↑ Despite the name, the 350/20 does not adhere to the S/360 architecture.
  4. ↑ Bit 22 is renamed as HFP exponent underflow in ESA/390
  5. ↑ Bit 23 is renamed as HFP significance in ESA/390

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References

  1. ↑ S360.
  2. ↑ S370.
  3. ↑ S370-XA.
  4. ↑ S370-ESA.
  5. ↑ S390-ESA.
  6. ↑ z.
  7. ↑ func67.
  8. 1 2 func67, p. 57, Glossary.
  9. ↑ func67, p. 15, Instruction Fetching and Execution.
  10. ↑ func67, p. 16, Table 4. Control Registers.
  11. ↑ S360, p. 15, Program Status Word.
  12. ↑ S360, pp. 15–16, Interruption.
  13. ↑ S370, pp. 15–16, Interruption.
  14. ↑ S370, p. 156, Instruction-Length Code.
  15. ↑ func67, pp. 15–16, Instruction Fetching and Execution.
  16. ↑ S360, p. 156, Instruction-Length Code.
  17. ↑ S370, pp. 4-8 –&#32, 4–9, Program-Status Word Format in BC Mode.
  18. ↑ S370, pp. 6-3 –&#32, 6–5, Interruption Action.
  19. ↑ S370, pp. 6-7 –&#32, 6–9, Instruction-Length Code.
  20. ↑ S370, pp. 4-6 –&#32, 4–7, Program-Status Word Format in EC Mode.
  21. ↑ S370-XA, p. 4-5, Program-Status-Word Format.
  22. ↑ S370-ESA, p. 4-5, Program-Status-Word Format.
  23. ↑ S390-ESA, p. 4-5, Program-Status-Word Format.
  24. ↑ z, pp. 4-5 –&#32, 4–8, Program-Status-Word Format.
  25. ↑ z, p. 4-8, Short PSW Format.
S360
IBM System/360 Principles of Operation (PDF) (Eighth ed.). IBM. September 1968. A22-6821-7.
func67
IBM System/360 Model 67 Functional Characteristics (PDF) (Third ed.). IBM. February 1972. GA27-2719-2.
S370
IBM System/370 Principles of Operation (PDF) (Eleventh ed.). IBM. September 1987. A22-7000-10.
S370-XA
IBM System/370 Extended Architecture Principles of Operation (PDF) (Second ed.). IBM. January 1987. SA22-7085-1.
S370-ESA
IBM Enterprise Systems Architecture/370 Principles of Operation (PDF) (First ed.). IBM. August 1988. SA22-7200-0.
z
z/Architecture Principles of Operation (PDF) (Thirteenth ed.). IBM. September 2019. SA22-7832-12.
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