Zilog Z80

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Zilog Z80
Zilog Z80.jpg
A Z80 manufactured in June 1976 according to the date stamp
General Info
LaunchedMarch 1976
Common manufacturer(s)
Max. CPU clock rate 2.5, 4, 6, 8 MHz to 10 MHz with CMOS variant up to 20 MHz and binary compatible derivatives (from Zilog) up to 33 and 50 MHz.
The Z80's original DIP40 chip package pinout Z80 pinout.svg
The Z80's original DIP40 chip package pinout

The Z80 is an 8-bit microprocessor introduced by Zilog as the startup company's first product. The Z80 was conceived by Federico Faggin in late 1974 and developed by him and his 11 employees starting in early 1975. The first working samples were delivered in March 1976, and it was officially introduced on the market in July 1976. With the revenue from the Z80, the company built its own chip factories and grew to over a thousand employees over the following two years. [2]


The Zilog Z80 is a software-compatible extension and enhancement of the Intel 8080 and, like it, was mainly aimed at embedded systems. Although used in that role, the Z80 also became one of the most widely used CPUs in desktop computers and home computers from the 1970s to the mid-1980s. [3] [4] It was also common in military applications, musical equipment such as synthesizers, and coin operated arcade games of the late 1970s and early 1980s including Pac-Man .

Zilog licensed the Z80 to the US-based Synertek and Mostek, which had helped them with initial production, as well as to a European second source manufacturer, SGS. The design was also copied by several Japanese, East European and Soviet manufacturers. [lower-roman 1] This won the Z80 acceptance in the world market since large companies like NEC, Toshiba, Sharp, and Hitachi started to manufacture the device (or their own Z80-compatible clones or designs).

In recent decades Zilog has refocused on the ever-growing market for embedded systems and the most recent Z80-compatible microcontroller family, the fully pipelined 24-bit eZ80 with a linear 16  MB address range, has been successfully introduced alongside the simpler Z80 and Z180 products.


A May 1976 advertisement for the Zilog Z-80 8-bit microprocessor Zilog Z-80 Microprocessor ad May 1976.jpg
A May 1976 advertisement for the Zilog Z-80 8-bit microprocessor
Photo of the original Zilog Z80 microprocessor design in depletion-load nMOS. Total die size is 3545x3350 um. (This actual chip manufactured in 1990.) Z80-Z0840004PSC-HD.jpg
Photo of the original Zilog Z80 microprocessor design in depletion-load nMOS. Total die size is 3545×3350 µm. (This actual chip manufactured in 1990.)
A CMOS Z80 in a Quad Flat Package Z84C0010FEC LQFP.png
A CMOS Z80 in a Quad Flat Package

The Z80 came about when physicist Federico Faggin left Intel at the end of 1974 to found Zilog with Ralph Ungermann  [ it ]. At Fairchild Semiconductor, and later at Intel, Faggin had been working on fundamental transistor and semiconductor manufacturing technology. He also developed the basic design methodology used for memories and microprocessors at Intel and led the work on the Intel 4004, the 8080 and several other ICs. Masatoshi Shima, the principal logic and transistor level-designer of the 4004 and the 8080 under Faggin's supervision, joined the Zilog team.

According to the designers, the primary targets for the Z80 CPU (and its optional support and peripheral ICs [lower-roman 2] ) were products like intelligent terminals, high end printers and advanced cash registers as well as telecom equipment, industrial robots and other kinds of automation equipment.

By March 1976, Zilog had developed the Z80 as well as an accompanying assembler based development system for its customers, and by July 1976, this was formally launched onto the market. [5] Some of the Z80 support and peripheral ICs were under development at this point, and many of them were launched during the following year.

Early Z80s were manufactured by Synertek and Mostek, before Zilog had its own manufacturing factory ready, in late 1976. These companies were chosen because they could do the ion implantation needed to create the depletion-mode MOSFETs that the Z80 design used as load transistors in order to cope with a single 5 Volt power supply. [lower-roman 3]

Faggin designed the instruction set to be binary compatible with the Intel 8080 [6] [7] so that most 8080 code, notably the CP/M operating system and Intel's PL/M compiler for 8080 (as well as its generated code), would run unmodified on the new Z80 CPU. Masatoshi Shima designed most of the microarchitecture as well as the gate and transistor levels of the Z80 CPU, assisted by a small number of engineers and layout people. [8] [9] CEO Federico Faggin was actually heavily involved in the chip layout work, together with two dedicated layout people. According to Faggin, he worked 80 hours a week in order to meet the tight schedule given by the financial investors. [10]

The Z80 offered many improvements over the 8080: [7]

The Z80 took over from the 8080 and its offspring, the 8085, in the processor market, [15] and became one of the most popular 8-bit CPUs. [3] [4] Zilog was later by a few years than Intel (with its 80C85) to produce a low-power CMOS CPU, and this resulted in the Intel chip first appearing in use with battery-powered portable computers, such as Tandy/Radio Shack's TRS-80 Model 100 laptop from April 1983. In following years, however, the CMOS Z80 would dominate this market.

Some organisations, such as BT, remained loyal to the 8085 for embedded applications owing to their familiarity with it, and to its on-chip support for a serial interface and multi-level interrupt architecture. Perhaps a key to the initial success of the Z80 was the built-in DRAM refresh, and other features which allowed systems to be built with fewer support chips (Z80 embedded systems typically use static RAM and hence do not need this refresh).

For the original NMOS design, the specified upper clock frequency limit increased successively from the introductory 2.5  MHz, via the well known 4 MHz (Z80A), up to 6 (Z80B) and 8 MHz (Z80H). [16] [17] The NMOS version has been produced as a 10 MHz part since the late 1980s. CMOS versions were developed with specified upper frequency limits ranging from 4 MHz up to 20 MHz for the version sold today. The CMOS versions allowed low-power sleep with internal state retained, having no lower frequency limit. [lower-roman 7] The fully compatible derivatives HD64180/Z180 [18] [19] and eZ80 are currently specified for up to 33 and 50 MHz respectively.


Programming model and register set

An approximate block diagram of the Z80. There is no dedicated adder for offsets or separate incrementer for R, and no need for more than a single 16-bit temporary register WZ (although the incrementer latches are also used as a 16-bit temporary register, in other contexts). It is the PC and IR registers that are placed in a separate group, with a detachable bus segment, to allow updates of these registers in parallel with the main register bank. Z80 arch.svg
An approximate block diagram of the Z80. There is no dedicated adder for offsets or separate incrementer for R, and no need for more than a single 16-bit temporary register WZ (although the incrementer latches are also used as a 16-bit temporary register, in other contexts). It is the PC and IR registers that are placed in a separate group, with a detachable bus segment, to allow updates of these registers in parallel with the main register bank.

The programming model and register set of the Z80 are fairly conventional, ultimately based on the register structure of the Datapoint 2200. The Z80 was designed as an extension of the 8080, created by the same engineers, which in turn was an extension of the 8008. The 8008 was basically a PMOS implementation of the TTL-based CPU of the Datapoint 2200. [lower-roman 8]

The 2200 design allowed 8-bit registers H and L (High and Low) to be paired into a 16-bit address register HL. [lower-roman 9] In the 8080, this pairing was added to the BC and DE pairs as well, while HL was generalized to allow use as a 16-bit accumulator, not just an address register. The 8080 also introduced the important 8-bit immediate data mode for accumulator operations, and immediate 16-bit data for HL, BC and DE loads. Furthermore, direct 16-bit copying between HL and memory was now possible, using a direct address.

The Z80 orthogonalized this further by making all 16-bit register pairs, including IX and IY, more general purpose, as well as allowing 16-bit copying directly to and from memory for all of these pairs. The 16-bit IX and IY registers in the Z80 are primarily intended as base address-registers, where a particular instruction supplies a constant offset that is added to the previous values, but they are also usable as 16-bit accumulators, among other things. The Z80 also introduced a new signed overflow flag and complemented the fairly simple 16-bit arithmetics of the 8080 with dedicated instructions for signed 16-bit arithmetics.

The 8080-compatible registers AF, BC, DE, HL are duplicated as two separate banks in the Z80, [21] where the processor can quickly switch from one bank to the other; [22] a feature useful for speeding up responses to single-level, high-priority interrupts. A similar feature was present in the 2200, but was never implemented at Intel. The dual register-set is very useful in the embedded role, as it improves interrupt handling performance, but found widespread use in the personal computer role as an additional set of general registers for complex code like floating point arithmetics or home computer games.


The Z80 registers
15141312111009080706050403020100(bit position)
Main registers
AFlagsAF (accumulator and flags)
HLHL (indirect address)
Alternate registers
A'Flags'AF' (accumulator and flags)
H'L'HL' (indirect address)
Index registers
IXIndex X
IYIndex Y
SPStack Pointer
Other registers
 IInterrupt vector
 RRefresh counter
Program counter
PCProgram Counter
Status register
  S Z - H - P/V N C Flags

As on the 8080, 8-bit registers are typically paired to provide 16-bit versions. The 8080 compatible registers [23] are:

  • AF: 8-bit accumulator (A) and flag bits (F) carry, zero, minus, parity/overflow, half-carry (used for BCD), and an Add/Subtract flag (usually called N) also for BCD
  • BC: 16-bit data/address register or two 8-bit registers
  • DE: 16-bit data/address register or two 8-bit registers
  • HL: 16-bit accumulator/address register or two 8-bit registers
  • SP: stack pointer, 16 bits
  • PC: program counter, 16 bits

The new registers introduced with the Z80 are:

  • IX: 16-bit index or base register for 8-bit immediate offsets
  • IY: 16-bit index or base register for 8-bit immediate offsets
  • I: interrupt vector base register, 8 bits
  • R: DRAM refresh counter, 8 bits (msb does not count)
  • AF': alternate (or shadow) accumulator and flags (toggled in and out with EX AF,AF' )
  • BC', DE' and HL': alternate (or shadow) registers (toggled in and out with EXX)
  • Four bits of interrupt status and interrupt mode status

There is no direct access to the alternate registers; instead, two special instructions, EX AF,AF' and EXX, [23] each toggles one of two multiplexer flip-flops. This enables fast context switches for interrupt service routines: EX AF, AF' may be used alone, for really simple and fast interrupt routines, or together with EXX to swap the whole BC, DE, HL set. This is still several times as fast as pushing the same registers on the stack. Slower, lower priority, or multi level interrupts normally use the stack to store registers, however.

The refresh register, R, increments each time the CPU fetches an opcode (or opcode prefix) and has no simple relationship with program execution. This has sometimes been used to generate pseudorandom numbers in games, and also in software protection schemes.[ citation needed ] It has also been employed as a "hardware" counter in some designs; an example of this is the ZX81, which lets it keep track of character positions on the TV screen by triggering an interrupt at wrap around (by connecting INT to A6).

The interrupt vector register, I, is used for the Z80 specific mode 2 interrupts (selected by the IM 2 instruction). It supplies the high byte of the base address for a 128-entry table of service routine addresses which are selected via an index sent to the CPU during an interrupt acknowledge cycle; this index is simply the low byte part of the pointer to the tabulated indirect address pointing to the service routine. [13] The pointer identifies a particular peripheral chip or peripheral function or event, where the chips are normally connected in a so-called daisy chain for priority resolution. Like the refresh register, this register has also sometimes been used creatively; in interrupt modes 0 and 1 (or in a system not using interrupts) it can be used as simply another 8-bit data register.

The instructions LD A,R and LD A,I affect the Z80 flags register, unlike all the other LD (load) instructions. The Sign (bit 7) and Zero (bit 6) flags are set according to the data loaded from the Refresh or Interrupt source registers. For both instructions, the Parity/Overflow flag (bit 2) is set according to the current state of the IFF2 flip-flop. [24]

Z80 assembly language

Datapoint 2200 and Intel 8008

The first Intel 8008 assembly language was based on a very simple (but systematic) syntax inherited from the Datapoint 2200 design. This original syntax was later transformed into a new, somewhat more traditional, assembly language form for this same original 8008 chip. At about the same time, the new assembly language was also extended to accommodate the added addressing possibilities in the more advanced Intel 8080 chip (the 8008 and 8080 shared a language subset without being binary compatible; however, the 8008 was binary compatible with the Datapoint 2200).

In this process, the mnemonic L, for LOAD, was replaced by various abbreviations of the words LOAD, STORE and MOVE, intermixed with other symbolic letters. The mnemonic letter M, for memory (referenced by HL), was lifted out from within the instruction mnemonic to become a syntactically freestanding operand, while registers and combinations of registers became very inconsistently denoted; either by abbreviated operands (MVI D, LXI H and so on), within the instruction mnemonic itself (LDA, LHLD and so on), or both at the same time (LDAX B, STAX D and so on).

Datapoint 2200 & i8008i8080Z80i8086/i8088
before ca. 1973ca. 197419761978
--STAXDLD(DE),AMOV[DX],AL [lower-roman 10]

Illustration of four syntaxes, using samples of equivalent, or (for 8086) very similar, load and store instructions. [25] The Z80 syntax uses parentheses around an expression to indicate that the value should be used as a memory address (as mentioned below), while the 8086 syntax uses brackets instead of ordinary parentheses for this purpose. Both Z80 and 8086 use the + sign to indicate that a constant is added to a base register to form an address

New syntax

Because Intel claimed a copyright on their assembly mnemonics, [26] a new assembly syntax had to be developed for the Z80. This time a more systematic approach was used:

  • All registers and register pairs are explicitly denoted by their full names
  • Parentheses are consistently used to indicate "memory contents at" (constant address or variable pointer dereferencing) with the exception of some jump instructions. [27]
  • All load and store instructions use the same mnemonic name, LD, for LOAD (a return to the simplistic Datapoint 2200 vocabulary); other common instructions, such as ADD and INC, use the same mnemonic regardless of addressing mode or operand size. This is possible because the operands themselves carry enough information.

These principles made it straightforward to find names and forms for all new Z80 instructions, as well as orthogonalizations of old ones, such as LD BC,(1234).

Apart from naming differences, and despite a certain discrepancy in basic register structure, the Z80 and 8086 syntax are virtually isomorphic for a large portion of instructions. Only quite superficial similarities (such as the word MOV, or the letter X, for extended register) exist between the 8080 and 8086 assembly languages, although 8080 programs can be translated to 8086 assembly language by translator programs. [28] [29]

Instruction set and encoding

The Z80 uses 252 out of the available 256 codes as single byte opcodes ("root instruction"); the four remaining codes are used extensively as opcode prefixes: [30] CB and ED enable extra instructions and DD or FD selects IX+d or IY+d respectively (in some cases without displacement d) in place of HL. This scheme gives the Z80 a large number of permutations of instructions and registers; Zilog categorizes these into 158 different "instruction types", 78 of which are the same as those of the Intel 8080 [30] (allowing operation of most 8080 programs on a Z80). The Zilog documentation further groups instructions into the following categories:

No multiply instructions are available in the original Z80. [31] Different sizes and variants of additions, shifts, and rotates have somewhat differing effects on flags because most of the flag-changing properties of the 8080 were copied. However, the parity flag bit P of the 8080 (bit 2) is called P/V (parity/overflow) in the Z80 as it serves the additional purpose of a twos complement overflow indicator, a lacking feature in the 8080. Arithmetic instructions on the Z80 set it to indicate overflow rather than parity, while bitwise instructions still use it as a parity flag. This new overflow flag is used for all new Z80-specific 16-bit operations (ADC, SBC) as well as for 8-bit arithmetic operations, although the 16-bit operations inherited from the 8080 (ADD, INC, DEC) do not affect it. Also, bit 1 of the flags register (a spare bit on the 8080) is used as a flag, N, that indicates whether the last arithmetic instruction executed was a subtraction or addition. The Z80 version of the DAA instruction (Decimal Adjust Accumulator for BCD arithmetic) checks the N flag and behaves accordingly, so a (hypothetical) subtraction followed later by DAA will yield a different result on an old 8080 than on the Z80. However, this would likely be erroneous code on the 8080, as DAA was defined for addition only on that processor.

The Z80 has six new LD instructions that can load the DE, BC, and SP register pairs from memory, and load memory from these three register pairs—unlike the 8080. [32] As on the 8080, load instructions do not affect the flags (except for the special purpose I and R register loads). A result of a regular encoding (common with the 8080) is that each of the 8-bit registers can be loaded from themselves (e.g. LD A,A). This is effectively a NOP.

New block transfer instructions can move up to 64 kilobytes from memory to memory or between memory and I/O peripheral ports. Block instructions LDIR and LDDR (LoaD,Increment/Decrement,Repeat) use HL to point to the source address, DE to the destination address, and BC as a byte counter. Bytes are copied from source to destination, the pointers are incremented or decremented, and the byte counter is decremented until BC reaches zero. Non-repeating versions LDI and LDD move a single byte and bump the pointers and byte counter, which if becomes zero resets the P/V flag. Corresponding memory-to-I/O instructions INIR, INDR, OTIR, OTDR, INI, IND, OUTI and OUTD operate similarly. The Z80 can input and output any register to an I/O port using register C to designate the port (the 8080 only performs I/O through the accumulator A).

The last group of block instructions perform a CP compare operation between the byte at (HL) and the accumulator A. Register pair DE is not used. The repeating versions CPIR and CPDR only terminate if BC goes to zero or a match is found. HL is left pointing to the byte after (CPIR) or before (CPDR) the matching byte. If no match is found the Z flag is reset. There are non-repeating versions CPI and CPD.

Unlike the 8080, the Z80 can jump to a relative address (JR instead of JP) using a signed 8-bit displacement. Only the Zero and Carry flags can be tested for these new two-byte JR instructions. A two-byte instruction specialized for program looping is also new to the Z80. DJNZ (Decrement Jump if Non-Zero) takes a signed 8-bit displacement as an immediate operand. The B register is decremented. If the result is nonzero then program execution jumps relative to the address of the PC plus the displacement. The flags remain unaltered. To perform an equivalent loop on an 8080 would require separate decrement and jump (to a two-byte absolute address) instructions, and the flag register would be altered.

The index register (IX/IY, often abbreviated XY) instructions can be useful for accessing data organised in fixed heterogenous structures (such as records) or at fixed offsets relative a variable base address (as in recursive stack frames) and can also reduce code size by removing the need for multiple short instructions using non-indexed registers. However, although they may save speed in some contexts when compared to long/complex "equivalent" sequences of simpler operations, they incur a lot of additional CPU time (e.g. 19 T-states to access one indexed memory location vs. as little as 11 to access the same memory using HL and INC to point to the next). Thus, for simple or linear accesses of data, use of IX and IY tend to be slower and occupy more memory. Still, they may be useful in cases where the 'main' registers are all occupied, by removing the need to save/restore registers. Their officially undocumented 8-bit halves (see below) can be especially useful in this context, for they incur less slowdown than their 16-bit parents. Similarly, instructions for 16-bit additions are not particularly fast (11 clocks) in the original Z80; nonetheless, they are about twice as fast as performing the same calculations using 8-bit operations, and equally important, they reduce register usage. It was not uncommon for programmers to "poke" different (typically calculated dynamically) offset displacement bytes into indexed instructions; this is an example of self-modifying code which was regular practice on nearly all early 8-bit processors with non-pipelined execution units.

The index registers have a parallel instruction to JP (HL), which is JP (XY). This is often seen in stack-oriented languages like Forth which at the end of every Forth word (atomic subroutines comprising the language) must jump unconditionally back to their thread interpreter routines. Typically this jump instruction appears many hundreds of times in an application, and using JP (XY) rather than JP THREAD saves a byte and two t-states each occurrence. This naturally makes the index register unavailable for any other use, or else the need to constantly reload it would negate its efficiency.

The 10-year-newer microcoded Z180 design could initially afford more "chip area", permitting a slightly more efficient implementation (using a wider ALU, among other things); similar things can be said for the Z800, Z280, and Z380. However, it was not until the fully pipelined eZ80 was launched in 2001 that those instructions finally became approximately as cycle-efficient as it is technically possible to make them, i.e. given the Z80 encodings combined with the capability to do an 8-bit read or write every clock cycle.[ citation needed ]

Undocumented instructions

The index registers, IX and IY, were intended as flexible 16 bit pointers, enhancing the ability to manipulate memory, stack frames and data structures. Officially, they were treated as 16-bit only. In reality they were implemented as a pair of 8-bit registers, [33] in the same fashion as the HL register, which is accessible either as 16 bits or separately as the High and Low registers. The binary opcodes (machine language) were identical, but preceded by a new opcode prefix. [34] Zilog published the opcodes and related mnemonics for the intended functions, but did not document the fact that every opcode that allowed manipulation of the H and L registers was equally valid for the 8 bit portions of the IX and IY registers. For example, the opcode 26h followed by an immediate byte value (LD H,n) will load that value into the H register. Preceding this two-byte instruction with the IX register's opcode prefix, DD, would instead result in the most significant 8 bits of the IX register being loaded with that same value. A notable exception to this would be instructions similar to LD H,(IX+d) which make use of both the HL and IX or IY registers in the same instruction; [34] in this case the DD prefix is only applied to the (IX+d) portion of the instruction. The halves of the XY registers could also hold operands for 8-bit arithmetic, logical and compare instructions, sparing the regular 8-bit registers for other use. The undocumented ability to increment and decrement the upper half of an index register made it easy to expand the range of the normal indexed instructions, without having to resort to the legal ADD/SBC XY,DE or ADD/SBC XY,BC.

There are several other undocumented instructions as well. [35] Undocumented or illegal opcodes are not detected by the Z80 and have various effects, some of which are useful. However, as they are not part of the formal definition of the instruction set, different implementations of the Z80 are not guaranteed to work the same way for every undocumented opcode.


The OTDR instruction does not conform to the Z80 documentation. Both the OTDR and OTIR instructions are supposed to leave the carry (C) flag unmodified. The OTIR instruction operates correctly; however, during the execution of the OTDR instruction, the carry flag takes the results of a spurious compare between the accumulator (A) and the last output of the OTDR instruction.

Example code

The following Z80 assembly source code is for a subroutine named memcpy that copies a block of data bytes of a given size from one location to another. Important: the example code does not handle a certain case where the destination block overlaps the source; a fatal bug. The sample code is extremely inefficient, intended to illustrate various instruction types, rather than best practices for speed. In particular, the Z80 has a single instruction that will execute the entire loop (LDIR). The data block is copied one byte at a time, and the data movement and looping logic utilizes 16-bit operations. Note that the assembled code is binary-compatible with the Intel 8080 and 8085 CPUs.

 1000              1000              1000 78           1001 B1           1002 C8           1003 1A           1004 77           1005 13           1006 23           1007 0B           1008 C3 00 10     100B 
; memcpy --; Copy a block of memory from one location to another.;; Entry registers;      BC - Number of bytes to copy;      DE - Address of source data block;      HL - Address of target data block;; Return registers;      BC - Zeroorg1000h;Origin at 1000hmemcpypubliclooplda,b;Test BC,orc;If BC = 0,retz;Returnlda,(de);Load A from (DE)ld(hl),a;Store A into (HL)incde;Increment DEinchl;Increment HLdecbc;Decrement BCjploop;Repeat the loopend

Instruction execution

Each instruction is executed in steps that are usually termed machine cycles (M-cycles), each of which can take between three and six clock periods (T-cycles). [36] Each M-cycle corresponds roughly to one memory access or internal operation. Many instructions actually end during the M1 of the next instruction which is known as a fetch/execute overlap.

Examples of typical instructions (R=read, W=write)


1 [37] INCBCopcode
2 [38] ADDA,nopcoden
3 [39] ADDHL,DEopcodeinternalinternal
4 [40] SETb,(HL)prefixopcodeR(HL), setW(HL)
5 [41] LD(IX+d),nprefixopcodedn,addW(IX+d)
6 [42] INC(IY+d)prefixopcodedaddR(IY+d),incW(IY+d)

The Z80 machine cycles are sequenced by an internal state machine which builds each M-cycle out of 3, 4, 5 or 6 T-cycles depending on context. This avoids cumbersome asynchronous logic and makes the control signals behave consistently at a wide range of clock frequencies. It also means that a higher frequency crystal must be used than without this subdivision of machine cycles (approximately 2–3 times higher). It does not imply tighter requirements on memory access times, since a high resolution clock allows more precise control of memory timings and so memory can be active in parallel with the CPU to a greater extent, allowing more efficient use of available memory bandwidth.[ citation needed ]

One central example of this is that, for opcode fetch, the Z80 combines two full clock cycles into a memory access period (the M1-signal). In the Z80 this signal lasts for a relatively larger part of the typical instruction execution time than in a design such as the 6800, 6502, or similar, where this period would typically last typically 30-40% of a clock cycle.[ citation needed ] With memory chip affordability (i.e. access times around 450-250 ns in the 1980s[ citation needed ]) typically determining the fastest possible access time, this meant that such designs were locked to a significantly longer clock cycle (i.e. lower internal clock speed) than the Z80.

Memory was generally slow compared to the state machine sub-cycles (clock cycles) used in contemporary microprocessors. The shortest machine cycle that could safely be used in embedded designs has therefore often been limited by memory access times, not by the maximum CPU frequency (especially so during the home computer era). However, this relation has slowly changed during the last decades, particularly regarding SRAM; cacheless, single-cycle designs such as the eZ80 have therefore become much more meaningful recently.

The content of the refresh register R is sent out on the lower half of the address bus along with a refresh control signal while the CPU is decoding and executing the fetched instruction. During refresh the contents of the Interrupt register I are sent out on the upper half of the address bus. [43]

Compatible peripherals

Zilog introduced a number of peripheral parts for the Z80, which all support the Z80's interrupt handling system and I/O address space. These include the Counter/Timer Channel (CTC), [44] the SIO (Serial Input Output), the DMA (Direct Memory Access), the PIO (Parallel Input-Output) and the DART (Dual Asynchronous Receiver Transmitter). As the product line developed, low-power, high-speed and CMOS versions of these chips were introduced.

Like the 8080, 8085 and 8086 processors, but unlike processors such as the Motorola 6800 and MOS Technology 6502, the Z80 and 8080 has a separate control line and address space for I/O instructions. While some Z80-based computers such as the Osborne 1 used "Motorola-style" memory mapped input/output devices, usually the I/O space was used to address one of the many Zilog peripheral chips compatible with the Z80. Zilog I/O chips supported the Z80's new mode 2 interrupts which simplified interrupt handling for large numbers of peripherals.

The Z80 was officially described as supporting 16-bit (64 KB) memory addressing, and 8-bit (256 ports) I/O-addressing. All I/O instructions actually assert the entire 16-bit address bus. OUT (C),reg and IN reg,(C) places the contents of the entire 16 bit BC register on the address bus; [45] OUT (n),A and IN A,(n) places the contents of the A register on b8-b15 of the address bus and n on b0-b7 of the address bus. A designer could choose to decode the entire 16 bit address bus on I/O operations in order to take advantage of this feature, or use the high half of the address bus to select subfeatures of the I/O device. This feature has also been used to minimise decoding hardware requirements, such as in the Amstrad CPC/PCW and ZX81.

Second sources and derivatives

Second sources

Mostek, who produced the first Z80 for Zilog, offered it as second-source as MK3880. SGS-Thomson (now STMicroelectronics) was a second-source, too, with their Z8400. Sharp and NEC developed second sources for the NMOS Z80, the LH0080, µPD780-1 and µPD780C respectively. The µPD780C was used in Sinclair's ZX80, ZX81 and early versions of the ZX Spectrum, in several MSX computers, and in musical synthesizers such as Oberheim OB-8 and others, while the µPD780-1 (a Z80A part which ran at 4 MHz) was used in Sega's SG-1000 game console. The LH0080 was used in various home computers and personal computers made by Sharp and other Japanese manufacturers, including Sony MSX computers, and a number of computers in the Sharp MZ series. [46]

Toshiba made a CMOS-version, the TMPZ84C00, which is believed[ by whom? ] (but not verified) to be the same design also used by Zilog for its own CMOS Z84C00. There were also Z80-chips made by GoldStar (now LG) and the BU18400 series of Z80-clones (including DMA, PIO, CTC, DART and SIO) in NMOS and CMOS made by ROHM Electronics.

In East Germany, an unlicensed clone of the Z80, known as the U880, was manufactured. It was very popular and was used in Robotron's and VEB Mikroelektronik Mühlhausen's computer systems (such as the KC85-series) and also in many self-made computer systems. In Romania another unlicensed clone could be found, named MMN80CPU and produced by Microelectronica, used in home computers like TIM-S, HC, COBRA.

Also, several clones of Z80 were created in the Soviet Union, notable ones being the T34BM1, also called КР1858ВМ1 (parallelling the Soviet 8080-clone KR580VM80A). The first marking was used in pre-production series, while the second had to be used for a larger production. Though, due to the collapse of Soviet microelectronics in the late 1980s, there are many more T34BM1s than КР1858ВМ1s.[ citation needed ]


Compatible with the original Z80
Partly compatible
No longer produced

Notable uses

Desktop computers

The Z80A was used as the CPU in a number of gaming consoles, such as this ColecoVision. ColecoVision-Open-FL.jpg
The Z80A was used as the CPU in a number of gaming consoles, such as this ColecoVision.

During the late 1970s and early 1980s, the Z80 was used in a great number of fairly anonymous business-oriented machines with the CP/M operating system, a combination that dominated the market at the time. [57] [58] Four well-known examples of Z80 business computers running CP/M are the Heathkit H89, the portable Osborne 1, the Kaypro series, and the Epson QX-10. Less well-known was the expensive high-end Otrona Attache. [59] Some systems used multi-tasking operating system software (like MP/M or Morrow's Micronix) to share the one processor between several concurrent users.

A Sinclair ZX Spectrum which used a Z80 Clocked at 3.5 MHz ZX Spectrum.jpg
A Sinclair ZX Spectrum which used a Z80 Clocked at 3.5 MHz

Multiple home computers were introduced that used the Z80 as the main processor or as a plug-in option to allow access to software written for the Z80.

In 1981, Multitech (later to become Acer) introduced the Microprofessor I, a simple and inexpensive training system for the Z80 microprocessor. Currently, it is still manufactured and sold by Flite Electronics International Limited in Southampton, England.

Portable and handheld computers

Use of the Z80 in lighter, battery-operated devices became more widespread with the availability of CMOS versions of the processor. The Sharp PC-1500, a BASIC-programmable pocket computer was released in 1981, followed by the improved Sharp PC-1600 in 1986 and the Sharp PC-E220 in 1991. Laptops which could run the CP/M operating system just like the desktop machines followed with Epson PX-8 Geneva in 1984, and in 1985 the Epson PX-4 and Bondwell-2. While the laptop market in subsequent years moved to more powerful Intel 8086 processors and the MS-DOS operating system, light-weight Z80-based systems with a longer battery life were still being introduced, such as the Cambridge Z88 in 1988 and the Amstrad NC100 in 1992. The Z80-derived Z8S180 also found its way into an early pen-operated personal digital assistant, the Amstrad PenPad PDA600 in 1993. Hong Kong-based VTech produced a line of small laptop computers called 'Lasers' based on a Z80. [60] [61] The last two were the Laser PC5 [62] and PC6. [63]

Starting with the TI-81 in 1990, Texas Instruments has manufactured a long line of graphing calculators based on the Z80. The TI-84 Plus series, introduced in 2004, is still in production as of 2019. The TI-84 Plus CE series, introduced in 2015, uses the Z80-derived Zilog eZ80 processor and is also still in production as of 2019. TI also produced a line of pocket organizers (ended in 2000) using Toshiba processors built around a Z80 core; the first of these was the TI PS-6200 [64] and after a lengthy production run of some dozen models culminated in their PocketMate series. [65] Later models of the Sharp Wizard series of personal organizers were Z80 based.

Embedded systems and consumer electronics

Z80-based PABX. The Z80 is third chip in from the left, to the right of the chip with the hand-written white label on it. PABX.jpg
Z80-based PABX. The Z80 is third chip in from the left, to the right of the chip with the hand-written white label on it.

The Zilog Z80 has long been a popular microprocessor in embedded systems and microcontroller cores, [23] where it remains in widespread use today. [3] [66] Applications of the Z80 include uses in consumer electronics, industrial products, and electronic musical instruments. For example, Z80 was used in the groundbreaking music synthesizer Prophet-5, [67] as well as in the first MIDI synthesizer Prophet 600. [68] Casio used the Z80A in its PV-1000 video game console. The Z80 was also used in the Sega Master System and Game Gear consoles. The Sega Genesis also contained a Zilog Z80 which controlled the system’s sound chips but also provided backwards compatibility with Sega Master System games.

In the late 1980s, a series of Soviet landline phones called "AON" featured the Z80; these phones expanded the featureset of the landline with caller ID, different ringtones based on the caller, speed dial and so forth. [69]

See also


  1. Zilog included several "traps" in the layout of the chip to try to delay this copying. According to Faggin, an NEC engineer later told him it had cost them several months of work, before they were able to get their μPD780 to function.
  2. These were named the Z80 CTC (counter/timer), Z80 DMA (direct memory access), Z80 DART (dual asynchronous receiver-transmitter), Z80 SIO (synchronous communication controller), and Z80 PIO (parallel input/output)
  3. Zilog manufactured the Z80 as well as most of their other products for many years until they sold their manufacturing plants and become the "fabless" company they are today.
  4. Although the 8080 had 16-bit addition and 16-bit increment and decrement instructions, it had no explicit 16-bit subtraction, and no overflow flag. The Z80 complemented this with the ADC HL,rr and SBC HL,rr instructions which sets the new overflow flag accordingly. (The 8080 compatible ADD HL,rr does not.)
  5. Notably to simultaneously handle the 32-bit mantissas of two operands in the 40-bit floating point format used in the Sinclair home computers. They were also used in a similar fashion in some earlier but lesser known Z80 based computers, such as the Swedish ABC 80 and ABC 800.
  6. As this refresh does not need to transfer any data, just output sequential row-addresses, it occupies less than 1.5 T-states. The dedicated M1-signal (machine cycle one) in the Z80 can be used to allow memory chips the same amount of access time for instruction fetches as for data access, i.e almost two full T-states out of the 4T fetch cycle (as well as out of the 3T data read cycle). The Z80 could use memory with the same range of access times as the 8080 (or the 8086) at the same clock frequency. This long M1-signal (relative to the clock) also meant that the Z80 could employ about 4-5 times the internal frequency of a 6800, 6502 or similar using the same type of memory.
  7. Unlike the original nMOS version, which used dynamic latches and could not be stopped for more than a few thousand clock cycles.
  8. The related 8086 family also inherited this register design.
  9. This variable HL pointer was actually the only way to access memory (for data) in the Datapoint 2200, and hence also in the Intel 8008. No direct addresses could be used to access data.
  10. It is not actually possible to encode this instruction on the Intel 8086 or later processors. See Intel reference manuals.

Related Research Articles

Intel 8080 8-bit microprocessor

The Intel 8080 ("eighty-eighty") was the second 8-bit microprocessor designed and manufactured by Intel and was released in April 1974. It is an extended and enhanced variant of the earlier 8008 design, although without binary compatibility. The initial specified clock rate or frequency limit was 2 MHz, and with common instructions using 4, 5, 7, 10, or 11 cycles this meant that it operated at a typical speed of a few hundred thousand instructions per second. A faster variant 8080A-1 became available later with clock frequency limit up to 3.125 MHz.

Intel 8086 16-bit central processing unit

The 8086 is a 16-bit microprocessor chip designed by Intel between early 1976 and June 8, 1978, when it was released. The Intel 8088, released July 1, 1979, is a slightly modified chip with an external 8-bit data bus, and is notable as the processor used in the original IBM PC design.

Intel 8088 microprocessor model

The Intel 8088 microprocessor is a variant of the Intel 8086. Introduced on June 1, 1979, the 8088 had an eight-bit external data bus instead of the 16-bit bus of the 8086. The 16-bit registers and the one megabyte address range were unchanged, however. In fact, according to the Intel documentation, the 8086 and 8088 have the same execution unit (EU)—only the bus interface unit (BIU) is different. The original IBM PC was based on the 8088, as were its clones.

Microprocessor Computer processor contained on an integrated-circuit chip

A microprocessor is a computer processor that incorporates the functions of a central processing unit on a single integrated circuit (IC), or sometimes up to 8 integrated circuits. The microprocessor is a multipurpose, clock driven, register based, digital integrated circuit that accepts binary data as input, processes it according to instructions stored in its memory and provides results as output. Microprocessors contain both combinational logic and sequential digital logic. Microprocessors operate on numbers and symbols represented in the binary number system.

MOS Technology 6502 8-bit microprocessor

The MOS Technology 6502 is an 8-bit microprocessor that was designed by a small team led by Chuck Peddle for MOS Technology.

Intel 8008 byte-oriented microprocessor

The Intel 8008 is an early byte-oriented microprocessor designed and manufactured by Intel and introduced in April 1972. It is an 8-bit CPU with an external 14-bit address bus that could address 16 KB of memory. Originally known as the 1201, the chip was commissioned by Computer Terminal Corporation (CTC) to implement an instruction set of their design for their Datapoint 2200 programmable terminal. As the chip was delayed and did not meet CTC's performance goals, the 2200 ended up using CTC's own TTL-based CPU instead. An agreement permitted Intel to market the chip to other customers after Seiko expressed an interest in using it for a calculator.

Intel 8085 8-bit microprocessor invented in 1976

The Intel 8085 ("eighty-eighty-five") is an 8-bit microprocessor produced by Intel and introduced in March 1976. It is a software-binary compatible with the more-famous Intel 8080 with only two minor instructions added to support its added interrupt and serial input/output features. However, it requires less support circuitry, allowing simpler and less expensive microcomputer systems to be built.

Intel 4004 4-bit central processing unit

The Intel 4004 is a 4-bit central processing unit (CPU) released by Intel Corporation in 1971. It was the first commercially available microprocessor, and the first in a long line of Intel CPUs. The chip design, implemented with the MOS silicon gate technology, started in April 1970, and was created by Federico Faggin who led the project from beginning to completion in 1971. Marcian Hoff formulated and led the architectural proposal in 1969, and Masatoshi Shima contributed to the architecture and later to the logic design. The first commercial sale of the fully operational 4004 occurred in March 1971 to Busicom Corp. of Japan for its 141-PF electronic calculator, for which it was originally designed and built as a custom chip.

The Zilog Z800 was a 16-bit microprocessor designed by Zilog and meant to be released in 1985. It was instruction compatible with their existing Z80, and differed primarily in having on-chip cache and a memory management unit (MMU) to provide a 16 MB address range. It also added a huge number of new more orthogonal instructions and addressing modes.

Zilog Z8000 16-bit microprocessor

The Z8000 is a 16-bit microprocessor introduced by Zilog in early 1979. The architecture was designed by Bernard Peuto while the logic and physical implementation was done by Masatoshi Shima, assisted by a small group of people.

Federico Faggin Italian physicist and electrical engineer

Federico Faggin is an Italian-American physicist, engineer, inventor and entrepreneur. He is best known for designing the first commercial microprocessor, the Intel 4004. He led the 4004 (MCS-4) project and the design group during the first five years of Intel's microprocessor effort. Faggin also created, while working at Fairchild Semiconductor in 1968, the self-aligned MOS (metal–oxide–semiconductor) silicon-gate technology (SGT), which made possible MOS semiconductor memory chips, CCD image sensors, and the microprocessor. After the 4004, he led development of the Intel 8008 and 8080, using his SGT methodology for random logic chip design, which was essential to the creation of early Intel microprocessors. He was co-founder and CEO of Zilog, the first company solely dedicated to microprocessors, and led the development of the Zilog Z80 and Z8 processors. He was later the co-founder and CEO of Cygnet Technologies, and then Synaptics.

Masatoshi Shima Japanese computer pioneer

Masatoshi Shima is a Japanese electronics engineer. He was one of the architects of the world's first microprocessor, the Intel 4004. Working for Busicom in Japan, in 1968 he did the logic design for a specialized CPU to be translated into three-chip custom chips. In 1969 he worked with Intel's Ted Hoff and Stanley Mazor to reduce the 3- chip Busicom proposal into a single-chip architecture. In 1970 that architecture was transformed into a silicon chip, the Intel 4004, by Federico Faggin, with Shima's assistance in logic design.

NEC V20 microprocessor model

The NEC V20 (μPD70108) was a processor made by NEC that was a reverse-engineered, pin-compatible version of the Intel 8088 with an instruction set compatible with the Intel 80186. The V20 was introduced in 1982, and the V30 debuted in 1983.

Zilog Z280

The Zilog Z280 is a 16-bit microprocessor, an enhancement of the Zilog Z80 architecture, introduced in July 1987. It is basically the Z800, renamed, with slight improvements such as being fabricated in CMOS. It was a commercial failure. Zilog added a memory management unit (MMU) to expand the addressing range to 16 MB, features for multitasking and multiprocessor and coprocessor configurations, and 256 bytes of on-chip static RAM, configurable as either a cache for instructions and/or data, or as part of the ordinary address space. It has a huge number of new instructions and addressing modes giving a total of over 2000 combinations. It is capable of efficiently handling 32-bit data operations including hardware multiply, divide, and sign extension. It offers Supervisor and User operating modes, and optionally separate address spaces for instructions and data in both modes. Its internal clock signal can be configured to run at 1, 2 or 4 times the external clock's speed. Unlike the Z80 the Z280 uses a multiplexed arrangement for its address and data busses. More successful extensions of the Z80-architecture include the Hitachi HD64180 in 1986 and Zilog eZ80 in 2001, among others. See further Zilog Z800.

Zilog Z380 Z80-compatible 16/32-bit processor

The Z380 is a Zilog 16-bit/32-bit processor from 1994. It is Z80 compatible, but it was released much later than its competitors and as a result was never able to gain any significant market leverage. On the other hand, the newer and faster eZ80 family has been more successful recently.

R800 (CPU)

The R800 is the central processing unit used in the MSX Turbo-R home computer. The R800 was designed by ASCII Corporation of Japan and built by Mitsui & Co., Ltd.. The goal was a modern and pipelined CPU binary compatible with the Z80, and therefore with MSX software, while also maintaining compatibility with older MSX Z80-based hardware.

Zilog eZ80 8-bit microprocessor

The Zilog eZ80 is an 8-bit microprocessor from Zilog which is essentially an updated version of the company's earlier Z80 8-bit microprocessor.

Signetics 2650 8-bit microprocessor

The Signetics 2650 was an 8-bit microprocessor introduced in mid-1975. According to Adam Osborne's book An Introduction to Microprocessors Vol 2: Some Real Products, it was "the most minicomputer-like" of the microprocessors available at the time. A combination of missing features and odd memory access limited its appeal, and the system saw little use in the market. Signetics became better known as a second-source supplier for the MOS 6502.

KR580VM80A 8-bit microprocessor

The KR580VM80A is a Soviet microprocessor, a clone of the Intel 8080 CPU. Different versions of this CPU were manufactured beginning in the late 1970s, the earliest known use being in the SM1800 computer in 1979. Initially called the K580IK80 (К580ИК80), it was produced in a 48-pin planar metal-ceramic package. Later, a version in a PDIP-40 package was produced and was named the KR580IK80A (КР580ИК80А). The pin layout of the latter completely matched that of Intel's 8080A CPU. In 1986 this CPU received a new part number to conform with the 1980 Soviet integrated circuit designation and became known as the KR580VM80A (КР580ВМ80А), the number it is most widely known by today. Normal clock frequency for the K580IK80A is 2 MHz, with speeds up to 2.5 MHz for the KR580VM80A. The KR580IK80A was manufactured in a 6 µm process. In the later KR580VM80A the feature size was reduced to 5 µm and the die became 20% smaller.

In computer architecture, 16-bit integers, memory addresses, or other data units are those that are 16 bits wide. Also, 16-bit CPU and ALU architectures are those that are based on registers, address buses, or data buses of that size. 16-bit microcomputers are computers in which 16-bit microprocessors were the norm.


  1. Only in CMOS, National made no NMOS version, according to Oral History with Federico Faggin
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  4. 1 2 The Seybold report on professional computing. Seybold Publications. 1983. In the 8-bit world, the two most popular microcomputers are the Z80 and 6502 computer chips.
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  10. See Federico Faggin, oral history.
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  13. 1 2 Wai-Kai Chen (2002). The circuits and filters handbook. CRC Press. p. 1943. ISBN   978-0-8493-0912-0. interrupt processing commences according to the interrupt method stipulated by the IM i, i=0, 1, or 2, instruction. If i=1, for direct method, the PC is loaded with 0038H. If i=0, for vectored method, the interrupting device has the opportunity to place the op-code for one byte . If i=2, for indirect vector method, the interrupting device must then place a byte. The Z80 then uses this byte where one of 128 interrupt vectors can be selected by the byte.
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Further reading

Datasheets and manuals
Hardware books
Software books
Reference cards
Simulators / Emulators