Integrated circuit layout

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Layout view of a simple CMOS operational amplifier Vlsiopamp2.gif
Layout view of a simple CMOS operational amplifier

In integrated circuit design, integrated circuit (IC) layout, also known IC mask layout or mask design, is the representation of an integrated circuit in terms of planar geometric shapes which correspond to the patterns of metal, oxide, or semiconductor layers that make up the components of the integrated circuit. Originally the overall process was called tapeout, as historically early ICs used graphical black crepe tape on mylar media for photo imaging (erroneously believed[ who? ] to reference magnetic data—the photo process greatly predated magnetic media[ citation needed ]).

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When using a standard process—where the interaction of the many chemical, thermal, and photographic variables is known and carefully controlled—the behaviour of the final integrated circuit depends largely on the positions and interconnections of the geometric shapes. Using a computer-aided layout tool, the layout engineer—or layout technician—places and connects all of the components that make up the chip such that they meet certain criteria—typically: performance, size, density, and manufacturability. This practice is often subdivided between two primary layout disciplines: analog and digital.

The generated layout must pass a series of checks in a process known as physical verification. The most common checks in this verification process are [1] [2]

When all verification is complete, layout post processing [3] is applied where the data is also translated into an industry-standard format, typically GDSII, and sent to a semiconductor foundry. The milestone completion of the layout process of sending this data to the foundry is now colloquially called "tapeout". The foundry converts the data into mask data [3] and uses it to generate the photomasks used in a photolithographic process of semiconductor device fabrication.

In the earlier, simpler, days of IC design, layout was done by hand using opaque tapes and films, an evolution derived from early days of printed circuit board (PCB) design -- tape-out.

Modern IC layout is done with the aid of IC layout editor software, mostly automatically using EDA tools, including place and route tools or schematic-driven layout tools. Typically this involves a library of standard cells.

The manual operation of choosing and positioning the geometric shapes is informally known as "polygon pushing". [4] [5] [6] [7] [8]

See also

Related Research Articles

<span class="mw-page-title-main">Integrated circuit</span> Electronic circuit formed on a small, flat piece of semiconductor material

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<span class="mw-page-title-main">Semiconductor device fabrication</span> Manufacturing process used to create integrated circuits

Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically integrated circuits (ICs) such as computer processors, microcontrollers, and memory chips that are present in everyday electronic devices. It is a multiple-step photolithographic and physio-chemical process during which electronic circuits are gradually created on a wafer, typically made of pure single-crystal semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.

In electronics and photonics design, tape-out or tapeout is the final result of the design process for integrated circuits or printed circuit boards before they are sent for manufacturing. The tapeout is specifically the point at which the graphic for the photomask of the circuit is sent to the fabrication facility.

<span class="mw-page-title-main">Very Large Scale Integration</span> Creating an integrated circuit by combining many transistors into a single chip

Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining millions or billions of MOS transistors onto a single chip. VLSI began in the 1970s when MOS integrated circuit chips were developed and then widely adopted, enabling complex semiconductor and telecommunication technologies. The microprocessor and memory chips are VLSI devices.

<span class="mw-page-title-main">Application-specific integrated circuit</span> Integrated circuit customized for a specific task

An application-specific integrated circuit is an integrated circuit (IC) chip customized for a particular use, rather than intended for general-purpose use, such as a chip designed to run in a digital voice recorder or a high-efficiency video codec. Application-specific standard product chips are intermediate between ASICs and industry standard integrated circuits like the 7400 series or the 4000 series. ASIC chips are typically fabricated using metal–oxide–semiconductor (MOS) technology, as MOS integrated circuit chips.

Electronic design automation (EDA), also referred to as electronic computer-aided design (ECAD), is a category of software tools for designing electronic systems such as integrated circuits and printed circuit boards. The tools work together in a design flow that chip designers use to design and analyze entire semiconductor chips. Since a modern semiconductor chip can have billions of components, EDA tools are essential for their design; this article in particular describes EDA specifically with respect to integrated circuits (ICs).

<span class="mw-page-title-main">GDSII</span> Database file format for data exchange of integrated circuit layout artwork

GDSII stream format (GDSII), is a binary database file format which is the de facto industry standard for Electronic Design Automation data exchange of integrated circuit or IC layout artwork. It is a binary file format representing planar geometric shapes, text labels, and other information about the layout in hierarchical form. The data can be used to reconstruct all or part of the artwork to be used in sharing layouts, transferring artwork between different tools, or creating photomasks.

Place and route is a stage in the design of printed circuit boards, integrated circuits, and field-programmable gate arrays. As implied by the name, it is composed of two steps, placement and routing. The first step, placement, involves deciding where to place all electronic components, circuitry, and logic elements in a generally limited amount of space. This is followed by routing, which decides the exact design of all the wires needed to connect the placed components. This step must implement all the desired connections while following the rules and limitations of the manufacturing process.

<span class="mw-page-title-main">Mixed-signal integrated circuit</span> Integrated circuit

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In electronic design automation, a design rule is a geometric constraint imposed on circuit board, semiconductor device, and integrated circuit (IC) designers to ensure their designs function properly, reliably, and can be produced with acceptable yield. Design rules for production are developed by process engineers based on the capability of their processes to realize design intent. Electronic design automation is used extensively to ensure that designers do not violate design rules; a process called design rule checking (DRC). DRC is a major step during physical verification signoff on the design, which also involves LVS checks, XOR checks, ERC, and antenna checks. The importance of design rules and DRC is greatest for ICs, which have micro- or nano-scale geometries; for advanced processes, some fabs also insist upon the use of more restricted rules to improve yield.

<span class="mw-page-title-main">Standard cell</span>

In semiconductor design, standard-cell methodology is a method of designing application-specific integrated circuits (ASICs) with mostly digital-logic features. Standard-cell methodology is an example of design abstraction, whereby a low-level very-large-scale integration (VLSI) layout is encapsulated into an abstract logic representation.

<span class="mw-page-title-main">Front end of line</span> Part of manufacturing process used to create integrated circuits

The front end of line (FEOL) is the first portion of IC fabrication where the individual components are patterned in the semiconductor. FEOL generally covers everything up to the deposition of metal interconnect layers.

<span class="mw-page-title-main">Back end of line</span> Part of manufacturing process used to create integrated circuits

While the term front end of line (FEOL) refers to the first portion of any IC fabrication where the individual devices are patterned in the semiconductor, back end of line (BEOL) comprises the subsequent deposition of metal interconnect layers. Thus, BEOL is the second portion of IC fabrication process where the individual devices get interconnected with wiring by deposited metalization layers.

<span class="mw-page-title-main">Integrated circuit design</span> Engineering process for electronic hardware

Integrated circuit design, semiconductor design, chip design or IC design, is a sub-field of electronics engineering, encompassing the particular logic and circuit design techniques required to design integrated circuits, or ICs. ICs consist of miniaturized electronic components built into an electrical network on a monolithic semiconductor substrate by photolithography.

Mask data preparation (MDP), also known as layout post processing, is the procedure of translating a file containing the intended set of polygons from an integrated circuit layout into set of instructions that a photomask writer can use to generate a physical mask. Typically, amendments and additions to the chip layout are performed in order to convert the physical layout into data for mask production.

Physical verification is a process whereby an integrated circuit layout design is verified via EDA software tools to ensure correct electrical and logical functionality and manufacturability. Verification involves design rule check (DRC), layout versus schematic (LVS), XOR, antenna checks and electrical rule check (ERC).

<span class="mw-page-title-main">Multi-project wafer service</span>

Multi-project chip (MPC), and multi-project wafer (MPW) semiconductor manufacturing arrangements allow customers to share tooling and microelectronics wafer fabrication cost between several designs or projects.

<span class="mw-page-title-main">Physical design (electronics)</span>

In integrated circuit design, physical design is a step in the standard design cycle which follows after the circuit design. At this step, circuit representations of the components of the design are converted into geometric representations of shapes which, when manufactured in the corresponding layers of materials, will ensure the required functioning of the components. This geometric representation is called integrated circuit layout. This step is usually split into several sub-steps, which include both design and verification and validation of the layout.

<span class="mw-page-title-main">Floorplan (microelectronics)</span> Layout of major electronic circuit blocks

In electronic design automation, a floorplan of an integrated circuit is a schematic representation of tentative placement of its major functional blocks.

In the automated design of integrated circuits, signoff checks is the collective name given to a series of verification steps that the design must pass before it can be taped out. This implies an iterative process involving incremental fixes across the board using one or more check types, and then retesting the design. There are two types of sign-off's: front-end sign-off and back-end sign-off. After back-end sign-off, the chip goes to fabrication. After listing out all the features in the specification, the verification engineer will write coverage for those features to identify bugs, and send back the RTL design to the designer. Bugs, or defects, can include issues like missing features, errors in design, etc. When the coverage reaches a maximum percentage then the verification team will sign it off. By using a methodology like UVM, OVM, or VMM, the verification team develops a reusable environment. Nowadays, UVM is more popular than others.

References

  1. A. Kahng, J. Lienig, I. Markov, J. Hu: VLSI Physical Design: From Graph Partitioning to Timing Closure, doi : 10.1007/978-3-030-96415-3, ISBN   978-3-030-96414-6, p. 9.
  2. Basu, Joydeep (2019-10-09). "From Design to Tape-out in SCL 180 nm CMOS Integrated Circuit Fabrication Technology". IETE Journal of Education. 60 (2): 51–64. arXiv: 1908.10674 . doi:10.1080/09747338.2019.1657787. S2CID   201657819.
  3. 1 2 J. Lienig, J. Scheible (2020). "Chap. 3.3: Mask Data: Layout Post Processing". Fundamentals of Layout Design for Electronic Circuits. Springer. p. 102-110. doi:10.1007/978-3-030-39284-0. ISBN   978-3-030-39284-0. S2CID   215840278.
  4. Dirk Jansen, editor. "The Electronic Design Automation Handbook". 2010. p. 39.
  5. Dan Clein. "CMOS IC Layout: Concepts, Methodologies, and Tools". 1999 p. 60.
  6. "Conference Record". 1987. p. 118.
  7. Charles A. Harper; Harold C. Jones. "Active Electronic Component Handbook". 1996. p. 2
  8. Riko Radojcic. "Managing More-than-Moore Integration Technology Development". 2018. p. 99

Further reading