IC layout editor

Last updated October 31, 2019

An Integrated circuit layout editor or IC layout editor is an electronic design automation software tool that allows a user to digitize the shapes and patterns that form an integrated circuit. Typically the view will include the components (usually as pcells), metal routing tracks, vias and electrical pins. Software of this type is similar to computer aided drafting software, but is specialized for the task of integrated circuit layout. The typical flow for the layout of analog circuits might be :

Electronic design automation (EDA), also referred to as electronic computer-aided design (ECAD), is a category of software tools for designing electronic systems such as integrated circuits and printed circuit boards. The tools work together in a design flow that chip designers use to design and analyze entire semiconductor chips. Since a modern semiconductor chip can have billions of components, EDA tools are essential for their design.

Integrated circuit electronic circuit manufactured by lithography; set of electronic circuits on one small flat piece (or "chip") of semiconductor material, normally silicon

An integrated circuit or monolithic integrated circuit is a set of electronic circuits on one small flat piece of semiconductor material that is normally silicon. The integration of large numbers of tiny MOS transistors into a small chip results in circuits that are orders of magnitude smaller, faster, and less expensive than those constructed of discrete electronic components. The IC's mass production capability, reliability, and building-block approach to circuit design has ensured the rapid adoption of standardized IC's in place of designs using discrete transistors. ICs are now used in virtually all electronic equipment and have revolutionized the world of electronics. Computers, mobile phones, and other digital home appliances are now inextricable parts of the structure of modern societies, made possible by the small size and low cost of ICs.

A via or VIA is an electrical connection between layers in a physical electronic circuit that goes through the plane of one or more adjacent layers. To ensure via robustness, IPC sponsored a round-robin exercise that developed a time to failure calculator.

1. The layout engineer receives the schematic from the designer in electrical form

2. Either the tool or the layout engineer creates a physical view of the circuit including all of the required components, wires, layers and pads.

3. The layout engineer positions the components to minimize both the area required and the negative effects of layout parasitics upon the circuit performance and also to allow efficient routing to components.

4. The layout engineer uses metal routing and other layers at times to connect all of the components, again taking care to avoid unwanted layout parasitics.

5. The layout engineer uses DRC and LVS checks to ensure that the circuit is both manufacturable and functional. Other tools in include field solver verification to check for important specs such as device resistance and sources of problems such as electromigration or too thin wires resulting in burn up of wires causing shorts or open circuits.

6. Other checks include ESD, XOR, EOS and verification with the foundry called Mebes check to ensure the boolean algorithms that generate the mask layers are done as intended. Boolean generation is quite often done in the layout editor.

Layout used to be done on sticks and yards of strings for very basic components. The advent of computers particularly mainframes and mini computers helped bring layout to the digital world of computers. In the 80's and 90's quite a bit of layout editing was done on personal pc's using such tools as IC Editors, L-Edit and others. Other layout editors use large track ball like device with clickers. Layout editors have moved mostly to the server world through the likes of Cadence Virtuoso and Mentor though some is still done through PC tools through tools such as L-Edit but sadly there is little choose from in the PC market though there are a few exceptions such as Magic and Klayout but these are mostly utilized for utility such as to view GDS files not fully powered layout editors as there once was in the 90's.

Layout Editors have grown in complexity and function to deal with the ever growing device count and issues that weren't issues before when device counts were smaller and geometries were much larger.

Layout Editors have started to incorporate other tools to see parasitics since RF and smaller geometries have been introduced. Layout engineers are sometimes called physical designers since a lot of layout is generated by the machine in digital blocks. This is done by tools such as Cadence Encounter or Synopsys tools. Yet since a drawn wire in the layout editor is a perfectly ideal that doesn't show the reality of the physical chip geometries. Wires are actually more like imperfect strands with some areas thinner and thicker than other areas. Ends are more rounded instead of perfectly square on the layout editor. Sometimes these imperfections need to be reflected or extracted by the layout editor and fed back to the circuit designer so that they can run what is called RCX simulation to take account of these physical parasitics.

In some cases the layout engineer will request minor changes to the schematic to simplify the layout.

Very rarely, socialism works

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