Physical verification

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Physical verification is a process whereby an integrated circuit layout (IC layout) design is verified via EDA software tools to ensure correct electrical and logical functionality and manufacturability. Verification involves design rule check (DRC), layout versus schematic (LVS), XOR (exclusive OR), antenna checks and electrical rule check (ERC). [1]

Contents

Design Rule Check (DRC)

DRC verifies that the layout meets all technology-imposed constraints. DRC also verifies layer density for chemical-mechanical polishing (CMP). [1]

Layout Versus Schematic (LVS)

LVS verifies the functionality of the design. From the layout, a netlist is derived and compared with the original netlist produced from logic synthesis or circuit design. [1]

XOR check

This check is typically run after a metal spin, where the original and modified database are compared. This is done to confirm that the desired modifications have been made and no undesired modifications have been made by accident. This step involves comparing the two layout databases/GDS by XOR operation of the layout geometries. This check results a database which has all the mismatching geometries in both the layouts.

Antenna check

The antenna basically is a metal interconnect, i.e., a conductor like polysilicon or metal, that is not electrically connected to silicon or grounded, during the processing steps of the wafer. [1] During the manufacturing process charge accumulation can occur on the antenna during certain fabrication steps like Plasma etching, which uses highly ionized matter to etch. If the connection to silicon does not exist, charges may build up on the interconnect to the point at which rapid discharge does take place and permanent physical damage results to thin transistor gate oxide. This rapid and destructive phenomenon is known as the antenna effect. Antenna errors can be cured by adding a small antenna diode to safely discharge the node or splitting the antenna by routing up to another metal layer and then down again. [1]

The antenna ratio is defined as the ratio between the physical area of the conductors making up the antenna to the total gate oxide area to which the antenna is electrically connected.

Electrical Rule Check (ERC)

ERC verifies the correctness of power and ground connections, and that signal transition times (slew), capacitive loads and fanouts are appropriately bounded. [1] This might include checking for

Gates should not connect directly to supplies; connection should be through TIE high/low cells only. ERC checks are based upon assumptions about the normal operating conditions of the ASIC, so they may give many false warning on ASICs with multiple or negative supplies. They can also check for structures susceptible to electrostatic discharge (ESD) damage.

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<span class="mw-page-title-main">Very Large Scale Integration</span> Creating an integrated circuit by combining many transistors into a single chip

Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining millions or billions of MOS transistors onto a single chip. VLSI began in the 1970s when MOS integrated circuit chips were developed and then widely adopted, enabling complex semiconductor and telecommunication technologies. The microprocessor and memory chips are VLSI devices.

<span class="mw-page-title-main">Application-specific integrated circuit</span> Integrated circuit customized for a specific task

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<span class="mw-page-title-main">Integrated circuit layout</span> Representation of an integrated circuits components as planar shapes

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<span class="mw-page-title-main">Standard cell</span>

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<span class="mw-page-title-main">Integrated circuit design</span> Engineering process for electronic hardware

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Design Closure is a part of the digital electronic design automation workflow by which an integrated circuit design is modified from its initial description to meet a growing list of design constraints and objectives.

<span class="mw-page-title-main">Layout Versus Schematic</span> Type of electronic circuit design software

The Layout Versus Schematic (LVS) is the class of electronic design automation (EDA) verification software that determines whether a particular integrated circuit layout corresponds to the original schematic or circuit diagram of the design.

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<span class="mw-page-title-main">Physical design (electronics)</span>

In integrated circuit design, physical design is a step in the standard design cycle which follows after the circuit design. At this step, circuit representations of the components of the design are converted into geometric representations of shapes which, when manufactured in the corresponding layers of materials, will ensure the required functioning of the components. This geometric representation is called integrated circuit layout. This step is usually split into several sub-steps, which include both design and verification and validation of the layout.

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In electronic design automation, a floorplan of an integrated circuit is a schematic representation of tentative placement of its major functional blocks.

In the automated design of integrated circuits, signoff checks is the collective name given to a series of verification steps that the design must pass before it can be taped out. This implies an iterative process involving incremental fixes across the board using one or more check types, and then retesting the design. There are two types of sign-off's: front-end sign-off and back-end sign-off. After back-end sign-off, the chip goes to fabrication. After listing out all the features in the specification, the verification engineer will write coverage for those features to identify bugs, and send back the RTL design to the designer. Bugs, or defects, can include issues like missing features, errors in design, etc. When the coverage reaches a maximum percentage then the verification team will sign it off. By using a methodology like UVM, OVM, or VMM, the verification team develops a reusable environment. Nowadays, UVM is more popular than others.

In integrated circuits (ICs), interconnects are structures that connect two or more circuit elements together electrically. The design and layout of interconnects on an IC is vital to its proper function, performance, power efficiency, reliability, and fabrication yield. The material interconnects are made from depends on many factors. Chemical and mechanical compatibility with the semiconductor substrate and the dielectric between the levels of interconnect is necessary, otherwise barrier layers are needed. Suitability for fabrication is also required; some chemistries and processes prevent the integration of materials and unit processes into a larger technology (recipe) for IC fabrication. In fabrication, interconnects are formed during the back-end-of-line after the fabrication of the transistors on the substrate.

References

  1. 1 2 3 4 5 6 A. Kahng, et al.: VLSI Physical Design: From Graph Partitioning to Timing Closure, ISBN   978-3-030-96414-6, doi : 10.1007/978-3-030-96415-3, p. 9.

Further reading