Fan-out

Last updated September 08, 2022

In digital electronics, the fan-out is the number of gate inputs driven by the output of another single logic gate.

In most designs, logic gates are connected to form more complex circuits. While no logic gate input can be fed by more than one output at a time without causing contention, it is common for one output to be connected to several inputs. The technology used to implement logic gates usually allows a certain number of gate inputs to be wired directly together without additional interfacing circuitry. The maximum fan-out of an output measures its load-driving capability: it is the greatest number of inputs of gates of the same type to which the output can be safely connected.

Logical practice

Maximum limits on fan-out are usually stated for a given logic family or device in the manufacturer's datasheets. These limits assume that the driven devices are members of the same family.

More complex analysis than fan-in and fan-out is required when two different logic families are interconnected. Fan-out is ultimately determined by the maximum source and sink currents of an output and the maximum source and sink currents of the connected inputs; the driving device must be able to supply or sink at its output the sum of the currents needed or provided (depending on whether the output is a logic high or low voltage level) by all of the connected inputs, while maintaining the output voltage specifications. For each logic family, typically a "standard" input is defined by the manufacturer with maximum input currents at each logic level, and the fan-out for an output is computed as the number of these standard inputs that can be driven in the worst case. (Therefore, it is possible that an output can actually drive more inputs than specified by fan-out, even of devices within the same family, if the particular devices being driven sink and/or source less current, as reported on their data sheets, than a "standard" device of that family.) Ultimately, whether a device has the fan-out capability to drive (with guaranteed reliability) a set of inputs is determined by adding up all the input-low (max.) source currents specified on the datasheets of the driven devices, adding up all the input-high (max.) sink currents of those same devices, and comparing those sums to the driving device's guaranteed maximum output-low sink current and output-high source current specifications, respectively. If both totals are within the driving device's limits, then it has the DC fan-out capacity to drive those inputs on those devices as a group, and otherwise it doesn't, regardless of the manufacturer's given fan-out number. However, for any reputable manufacturer, if this current analysis reveals that the device cannot drive the inputs, the fan-out number will agree.

When high-speed signal switching is required, the AC impedance of the output, the inputs, and the conductors between may significantly reduce the effective drive capacity of output, and this DC analysis may not be enough. See AC Fan-out below.

Theory

DC fan-out

A perfect logic gate would have infinite input impedance and zero output impedance, allowing a gate output to drive any number of gate inputs. However, since real-world fabrication technologies exhibit less than perfect characteristics, a limit will be reached where a gate output cannot drive any more current into subsequent gate inputs - attempting to do so causes the voltage to fall below the level defined for the logic level on that wire, causing errors.

The fan-out is the number of inputs that can be connected to an output before the current required by the inputs exceeds the current that can be delivered by the output while still maintaining correct logic levels. The current figures may be different for the logic zero and logic one states and in that case we must take the pair that give the lower fan-out. This can be expressed mathematically as

{\text{DC Fan-out}}=\operatorname {min} \left(\left\lfloor {\frac {I_{\text{out high}}}{I_{\text{in high}}}}\right\rfloor ,\left\lfloor {\frac {I_{\text{out low}}}{I_{\text{in low}}}}\right\rfloor \right)

where $\lfloor \;\rfloor$ is the floor function.

Going on these figures alone TTL logic gates are limited to perhaps 2 to 10, depending on the type of gate, while CMOS gates have DC fan-outs that are generally far higher than is likely to occur in practical circuits (e.g. using NXP Semiconductor specifications for their HEF4000 series CMOS chips at 25 °C and 15 V gives a fan-out of 34 000).

AC fan-out

However, inputs of real gates have capacitance as well as resistance to the power supply rails. This capacitance will slow the output transition of the previous gate and hence increase its propagation delay. As a result, rather than a fixed fan-out the designer is faced with a trade off between fan-out and propagation delay (which affects the maximum speed of the overall system). This effect is less marked for TTL systems, which is one reason why TTL maintained a speed advantage over CMOS for many years.

Often a single signal (as an extreme example, the clock signal) needs to drive far more than 10 things on a chip. Rather than simply wiring the output of a gate to 1000 different inputs, circuit designers have found that it runs much faster to have a tree (as an extreme example, a clock tree) – for example, have the output of that gate drive 10 buffers (or equivalently a buffer scaled 10 times as big as the minimum-size buffer), those buffers drive 100 other buffers (or equivalently a buffer scaled 100 times as big as the minimum-size buffer), and those final buffers to drive the 1000 desired inputs. During physical design, some VLSI design tools do buffer insertion as part of signal integrity design closure.

Likewise, rather than simply wiring all 64 output bits to a single 64-input NOR gate to generate the Z flag on a 64-bit ALU, circuit designers have found that it runs much faster to have a tree – for example, have the Z flag generated by an 8-input NOR gate, and each of their inputs generated by an 8-input OR gate.

Reminiscent of radix economy, one estimate for the total delay of such a tree—the total number of stages by the delay of each stage – gives an optimum (minimum delay) when each stage of the tree is scaled by e, approximately 2.7. People who design digital integrated circuits typically insert trees whenever necessary such that the fan-in and fan-out of each and every gate on the chip is between 2 and 10.^[1]

Dynamic or AC fan-out, not DC fan-out is therefore the primary limiting factor in many practical cases, due to the speed limitation. For example, suppose a microcontroller has 3 devices on its address and data lines, and the microcontroller can drive 35 pF of bus capacitance at its maximum clock speed. If each device has 8 pF of input capacitance, then only 11 pF of trace capacitance is allowable. (Routing traces on printed circuit boards usually have 1-2 pF per inch so the traces in this case can be 5.5 inches long max.) If this trace length condition can't be met, then the microcontroller must be run at a slower bus speed for reliable operation, or a buffer chip with higher current drive must be inserted into the circuit. Higher current drive increases speed since $\textstyle \ I=C{\frac {dV}{dt}}$ ; more simply, current is rate of flow of charge, so increased current charges the capacitance faster, and the voltage across a capacitor is equal to the charge on it divided by the capacitance. So with more current, voltage changes faster, which allows faster signaling over the bus.

Unfortunately, due to the higher speeds of modern devices, IBIS simulations may be required for exact determination of the dynamic fan-out since dynamic fan-out is not clearly defined in most datasheets. (See the external link for more information.)

Related Research Articles

A logic gate is an idealized or physical device implementing a Boolean function, a logical operation performed on one or more binary inputs that produces a single binary output. Depending on the context, the term may refer to an ideal logic gate, one that has for instance zero rise time and unlimited fan-out, or it may refer to a non-ideal physical device.

Transistor–transistor logic (TTL) is a logic family built from bipolar junction transistors. Its name signifies that transistors perform both the logic function and the amplifying function, as opposed to resistor–transistor logic (RTL) or diode–transistor logic (DTL).

In digital logic, an inverter or NOT gate is a logic gate which implements logical negation. In mathematical logic it is equivalent to the logical negation operator (¬). The truth table is shown on the right.

In electronics, emitter-coupled logic (ECL) is a high-speed integrated circuit bipolar transistor logic family. ECL uses an overdriven bipolar junction transistor (BJT) differential amplifier with single-ended input and limited emitter current to avoid the saturated region of operation and its slow turn-off behavior. As the current is steered between two legs of an emitter-coupled pair, ECL is sometimes called current-steering logic (CSL), current-mode logic (CML) or current-switch emitter-follower (CSEF) logic.

Resistor–transistor logic (RTL) is a class of digital circuits built using resistors as the input network and bipolar junction transistors (BJTs) as switching devices. RTL is the earliest class of transistorized digital logic circuit used; other classes include diode–transistor logic (DTL) and transistor–transistor logic (TTL). RTL circuits were first constructed with discrete components, but in 1961 it became the first digital logic family to be produced as a monolithic integrated circuit. RTL integrated circuits were used in the Apollo Guidance Computer, whose design was begun in 1961 and which first flew in 1966.

Diode–transistor logic (DTL) is a class of digital circuits that is the direct ancestor of transistor–transistor logic. It is called so because the logic gating function is performed by a diode network and the amplifying function is performed by a transistor.

A buffer amplifier is one that provides electrical impedance transformation from one circuit to another, with the aim of preventing the signal source from being affected by whatever currents that the load may be produced with. The signal is 'buffered from' load currents. Two main types of buffer exist: the voltage buffer and the current buffer.

In computer engineering, a logic family is one of two related concepts:

Propagation delay is the time duration taken for a signal to reach its destination. It can relate to networking, electronics or physics. Hold time is the minimum interval required for the logic level to remain on the input after triggering edge of the clock pulse.

In electronic logic circuits, a pull-up resistor (PU) or pull-down resistor (PD) is a resistor used to ensure a known state for a signal. It is typically used in combination with components such as switches and transistors, which physically interrupt the connection of subsequent components to ground or to V_CC. Closing the switch creates a direct connection to ground or V_CC, but when the switch is open, the rest of the circuit would be left floating.

In digital electronics three-state, tri-state, or 3-state logic allows an output or input pin/pad to assume a high impedance state, effectively removing the output from the circuit, in addition to the 0 and 1 logic levels.

Diode logic (DL), or diode-resistor logic (DRL), is the construction of Boolean logic gates from diodes. Diode logic was used extensively in the construction of early computers, where semiconductor diodes could replace bulky and costly active vacuum tube elements. The most common use for diode logic is in diode–transistor logic (DTL) integrated circuits that, in addition to diodes, include inverter logic to provide a NOT function and signal restoration.

Integrated injection logic (IIL, I²L, or I2L) is a class of digital circuits built with multiple collector bipolar junction transistors (BJT). When introduced it had speed comparable to TTL yet was almost as low power as CMOS, making it ideal for use in VLSI (and larger) integrated circuits. The gates can be made smaller with this logic family than with CMOS because complementary transistors are not needed. Although the logic voltage levels are very close (High: 0.7V, Low: 0.2V), I2L has high noise immunity because it operates by current instead of voltage. I2L was developed in 1971 by Siegfried K. Wiedmann and Horst H. Berger who originally called it merged-transistor logic (MTL). A disadvantage of this logic family is that the gates draw power when not switching unlike with CMOS.

An open collector is a common type of output found on many integrated circuits (IC), which behaves like a switch that is either connected to ground or disconnected. Instead of outputting a signal of a specific voltage or current, the output signal is applied to the base of an internal NPN transistor whose collector is externalized (open) on a pin of the IC. The emitter of the NPN transistor is connected internally to the ground pin. If the output device is a MOSFET the output is called open drain and it functions in a similar way. For example, the I²C bus and 1-Wire bus are based on this concept.

In integrated circuit design, dynamic logic is a design methodology in combinatory logic circuits, particularly those implemented in MOS technology. It is distinguished from the so-called static logic by exploiting temporary storage of information in stray and gate capacitances. It was popular in the 1970s and has seen a recent resurgence in the design of high speed digital electronics, particularly computer CPUs. Dynamic logic circuits are usually faster than static counterparts, and require less surface area, but are more difficult to design. Dynamic logic has a higher toggle rate than static logic but the capacitive loads being toggled are smaller so the overall power consumption of dynamic logic may be higher or lower depending on various tradeoffs. When referring to a particular logic family, the dynamic adjective usually suffices to distinguish the design methodology, e.g. dynamic CMOS or dynamic SOI design.

In digital circuits, a logic level is one of a finite number of states that a digital signal can inhabit. Logic levels are usually represented by the voltage difference between the signal and ground, although other standards exist. The range of voltage levels that represent each state depends on the logic family being used. A logic-level shifter can be used to allow compatibility between different circuits.

PMOS or pMOS logic is a family of digital circuits based on p-channel, enhancement mode metal–oxide–semiconductor field-effect transistors (MOSFETs). In the late 1960s and early 1970s, PMOS logic was the dominant semiconductor technology for large-scale integrated circuits before being superseded by NMOS and CMOS devices.

HCMOS is the set of specifications for electrical ratings and characteristics, forming the 74HC00 family, a part of the 7400 series of integrated circuits.

High Threshold Logic (HTL), also known as Low-Speed Logic (LSL) or High Level Logic (HLL), is a variant of Diode–transistor logic which is used in such environments where noise is very high.

References

↑ Miles Murdocca, Apostolos Gerasoulis, and Saul Levy. "Novel Optical Computer Architecture Utilizing Reconfigurable Interconnects". 1991. p. 60-61.

External links

HIGH-SPEED DIGITAL DESIGN — online newsletter — Vol. 8 Issue 07

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[1] Miles Murdocca, Apostolos Gerasoulis, and Saul Levy. "Novel Optical Computer Architecture Utilizing Reconfigurable Interconnects". 1991. p. 60-61.

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