Last updated Simulated eye diagram displaying a DDR3 signal waveform
Signal integrity or SI is a set of measures of the quality of an electrical signal. In digital electronics, a stream of binary values is represented by a voltage (or current) waveform. However, digital signals are fundamentally analog in nature, and all signals are subject to effects such as noise, distortion, and loss. Over short distances and at low bit rates, a simple conductor can transmit this with sufficient fidelity. At high bit rates and over longer distances or through various mediums, various effects can degrade the electrical signal to the point where errors occur and the system or device fails. Signal integrity engineering is the task of analyzing and mitigating these effects. It is an important activity at all levels of electronics packaging and assembly, from internal connections of an integrated circuit (IC),[1] through the package, the printed circuit board (PCB), the backplane, and inter-system connections.[2] While there are some common themes at these various levels, there are also practical considerations, in particular the interconnect flight time versus the bit period, that cause substantial differences in the approach to signal integrity for on-chip connections versus chip-to-chip connections.
Signal integrity primarily involves the electrical performance of the wires and other packaging structures used to move signals about within an electronic product. Such performance is a matter of basic physics and as such has remained relatively unchanged since the inception of electronic signaling. The first transatlantic telegraph cable suffered from severe signal integrity problems, and analysis of the problems yielded many of the mathematical tools still used today to analyze signal integrity problems, such as the telegrapher's equations. Products as old as the Western Electric crossbar telephone exchange (circa 1940), based on the wire-spring relay, suffered almost all the effects seen today - the ringing, crosstalk, ground bounce, and power supply noise that plague modern digital products.
On printed circuit boards, signal integrity became a serious concern when the transition (rise and fall) times of signals started to become comparable to the propagation time across the board. Very roughly speaking, this typically happens when system speeds exceed a few tens of MHz. At first, only a few of the most important, or highest speed, signals needed detailed analysis or design. As speeds increased, a larger and larger fraction of signals needed SI analysis and design practices. In modern (> 100MHz) circuit designs, essentially all signals must be designed with SI in mind.
For ICs, SI analysis became necessary as an effect of reduced design rules. In the early days of the modern VLSI era, digital chip circuit design and layout were manual processes. The use of abstraction and the application of automatic synthesis techniques have since allowed designers to express their designs using high-level languages and apply an automated design process to create very complex designs, ignoring the electrical characteristics of the underlying circuits to a large degree. However, scaling trends (see Moore's law) brought electrical effects back to the forefront in recent technology nodes. With scaling of technology below 0.25µm, the wire delays have become comparable or even greater than the gate delays. As a result, the wire delays needed to be considered to achieve timing closure. In nanometer technologies at 0.13µm and below, unintended interactions between signals (e.g. crosstalk) became an important consideration for digital design. At these technology nodes, the performance and correctness of a design cannot be assured without considering noise effects.
Most of this article is about SI in relation to modern electronic technology - notably the use integrated circuits and printed circuit board technology. Nevertheless, the principles of SI are not exclusive to the signalling technology used. SI existed long before the advent of either technology, and will do so as long as electronic communications persist.
On-chip signal integrity
Signal integrity problems in modern integrated circuits (ICs) can have many drastic consequences for digital designs:
Products can fail to operate at all, or worse yet, become unreliable in the field.
The design may work, but only at speeds slower than planned
Yield may be lowered, sometimes drastically
The cost of these failures is very high, and includes photomask costs, engineering costs and opportunity cost due to delayed product introduction. Therefore, electronic design automation (EDA) tools have been developed to analyze, prevent, and correct these problems.[1] In integrated circuits, or ICs, the main cause of signal integrity problems is crosstalk. In CMOS technologies, this is primarily due to coupling capacitance, but in general it may be caused by mutual inductance, substrate coupling, non-ideal gate operation, and other sources. The fixes normally involve changing the sizes of drivers and/or spacing of wires.
In analog circuits, designers are also concerned with noise that arise from physical sources, such as thermal noise, flicker noise, and shot noise. These noise sources on the one hand present a lower limit to the smallest signal that can be amplified, and on the other, define an upper limit to the useful amplification.
In digital ICs, noise in a signal of interest arises primarily from coupling effects from switching of other signals. Increasing interconnect density has led to each wire having neighbors that are physically closer together, leading to increased crosstalk between neighboring nets. As circuits have continued to shrink in accordance with Moore's law, several effects have conspired to make noise problems worse:
To keep resistance tolerable despite decreased width, modern wire geometries are thicker in proportion to their spacing. This increases the sidewall capacitance at the expense of capacitance to ground, hence increasing the induced noise voltage (expressed as a fraction of supply voltage).
Technology scaling has led to lower threshold voltages for MOS transistors, and has also reduced the difference between threshold and supply voltages, thereby reducing noise margins.
Logic speeds, and clock speeds in particular, have increased significantly, thus leading to faster transition (rise and fall) times. These faster transition times are closely linked to higher capacitive crosstalk. Also, at such high speeds the inductive properties of the wires come into play, especially mutual inductance.
These effects have increased the interactions between signals and decreased the noise immunity of digital CMOS circuits. This has led to noise being a significant problem for digital ICs that must be considered by every digital chip designer prior to tape-out. There are several concerns that must be mitigated:
Noise may cause a signal to assume the wrong value. This is particularly critical when the signal is about to be latched (or sampled), for a wrong value could be loaded into a storage element, causing logic failure.
Noise may delay the settling of the signal to the correct value. This is often called noise-on-delay.
Noise (e.g. ringing) may cause the input voltage of a gate to drop below ground level, or to exceed the supply voltage. This can reduce the lifetime of the device by stressing components, induce latchup, or cause multiple cycling of signals that should only cycle once in a given period.
Finding IC signal integrity problems
Typically, an IC designer would take the following steps for SI verification:
Perform a layout extraction to get the parasitics associated with the layout. Usually worst-case parasitics and best-case parasitics are extracted and used in the simulations. For ICs, unlike PCBs, physical measurement of the parasitics is almost never done, since in-situ measurements with external equipment are extremely difficult. Furthermore, any measurement would occur after the chip has been created, which is too late to fix any problems observed.
Create a list of expected noise events, including different types of noise, such as coupling and charge sharing.
Create a model for each noise event. It is critical that the model is as accurate as necessary to model the given noise event.
For each signal event, decide how to excite the circuit so that the noise event will occur.
Create a SPICE (or another circuit simulator) netlist that represents the desired excitation, to include as many effects (such as parasitic inductance and capacitance, and various distortion effects) as necessary.
Run SPICE simulations. Analyze the simulation results and decide whether any re-design is required. It is common to analyze the results with an eye pattern and by calculating a timing budget.[3]
Modern signal integrity tools for IC design perform all these steps automatically, producing reports that give a design a clean bill of health, or a list of problems that must be fixed. However, such tools generally are not applied across an entire IC, but only selected signals of interest.
Fixing IC signal integrity problems
Once a problem is found, it must be fixed. Typical fixes for IC on-chip problems include:
Removing impedance discontinuities. Finding places where significant shifts in the impedance exist and adjusting the geometry of the path to shift the impedance to better match the rest of the path.
Driver optimization. You can have too much drive, and also not enough.
Buffer insertion. In this approach, instead of upsizing the victim driver, a buffer is inserted at an appropriate point in the victim net.
Aggressor downsizing. This works by increasing the transition time of the attacking net by reducing the strength of its driver.
Add shielding. Add shielding of critical nets or clock nets using GND and VDD shields to reduce the effect of crosstalk (this technique may lead to routing overhead).
Routing changes. Routing changes can be very effective in fixing noise problems, mainly by reducing the most troublesome coupling effects via separation.
Each of these fixes may possibly cause other problems. This type of issue must be addressed as part of design flows and design closure. Re-analysis after design changes is a prudent measure.
On-die termination
On-die termination (ODT) or Digitally Controlled Impedance (DCI[4]) is the technology where the termination resistor for impedance matching in transmission lines is located within a semiconductor chip, instead of a separate, discrete device mounted on a circuit board. The closeness of the termination from the receiver shorten the stub between the two, thus improving the overall signal integrity.
For wired connections, it is important to compare the interconnect flight time to the bit period to decide whether an impedance matched or unmatched connection is needed.
The channel flight time (delay) of the interconnect is roughly 1 ns per 15 cm (6 in) of FR-4stripline (the propagation velocity depends on the dielectric and the geometry).[5] Reflections of previous pulses at impedance mismatches die down after a few bounces up and down the line (i.e. on the order of the flight time). At low bit rates, the echoes die down on their own, and by midpulse, they are not a concern. Impedance matching is neither necessary nor desirable. There are many circuit board types other than FR-4, but usually they are more costly to manufacture.
The gentle trend to higher bit rates accelerated dramatically in 2004, with the introduction by Intel of the PCI-Express standard. Following this lead, the majority of chip-to-chip connection standards underwent an architectural shift from parallel buses to serializer/deserializer (SERDES) links called "lanes." Such serial links eliminate parallel bus clock skew and reduce the number of traces and resultant coupling effects but these advantages come at the cost of a large increase in bit rate on the lanes, and shorter bit periods.
At multigigabit/s data rates, link designers must consider reflections at impedance changes (e.g. where traces change levels at vias, see Transmission lines), noise induced by densely packed neighboring connections (crosstalk), and high-frequency attenuation caused by the skin effect in the metal trace and dielectric loss tangent. Examples of mitigation techniques for these impairments are a redesign of the via geometry to ensure an impedance match, use of differential signaling, and preemphasis filtering, respectively.[6][7]
At these new multigigabit/s bit rates, the bit period is shorter than the flight time; echoes of previous pulses can arrive at the receiver on top of the main pulse and corrupt it. In communication engineering this is called intersymbol interference (ISI). In signal integrity engineering it is usually called eye closure (a reference to the clutter in the center of a type of oscilloscope trace called an eye diagram). When the bit period is shorter than the flight time, elimination of reflections using classic microwave techniques like matching the electrical impedance of the transmitter to the interconnect, the sections of interconnect to each other, and the interconnect to the receiver, is crucial. Termination with a source or load is a synonym for matching at the two ends. The interconnect impedance that can be selected is constrained by the impedance of free space (~377 Ω), a geometric form factor and by the square root of the relative dielectric constant of the stripline filler (typically FR-4, with a relative dielectric constant of ~4). Together, these properties determine the trace's characteristic impedance. 50 Ω is a convenient choice for single-end lines,[8] and 100 ohm for differential.
As a consequence of the low impedance required by matching, PCB signal traces carry much more current than their on-chip counterparts. This larger current induces crosstalk primarily in a magnetic or inductive mode as opposed to a capacitive mode. To combat this crosstalk, digital PCB designers must remain acutely aware of not only the intended signal path for every signal, but also the path of returning signal current for every signal. The signal itself and its returning signal current path are equally capable of generating inductive crosstalk. Differential trace pairs help to reduce these effects.
A third difference between on-chip and chip-to-chip connection involves the cross-sectional size of the signal conductor, namely that PCB conductors are much larger (typically 100 µm or more in width). Thus, PCB traces have a small series resistance (typically 0.1 Ω/cm) at DC. The high frequency component of the pulse is however attenuated by additional resistance due to the skin effect and dielectric loss tangent associated with the PCB material.
The main challenge often depends on whether the project is a cost-driven consumer application or a performance-driven infrastructure application.[9] They tend to require extensive post-layout verification (using an EM simulator) and pre-layout design optimization (using SPICE and a channel simulator), respectively.
Routing topology
Tree topology similar to that of the DDR2 Command/Address (CA) bankFly-by topology similar to that of the DDR3 Command/Address (CA) bank
The noise levels on a trace/network is highly dependent on the routing topology selected. In a point-to-point topology, the signal is routed from the transmitter directly to the receiver (this is applied in PCIe, RapidIO, Gigabit Ethernet, DDR2/DDR3/DDR4 DQ/DQS etc.). A point-to-point topology has the least SI-problems since there is no large impedance matches being introduced by line T's (a two-way split of a trace).
For interfaces where multiple packages are receiving from the same line, (for example with a backplane configuration), the line must be split at some point to service all receivers. Some stubs and impedance mismatches are deemed to occur. Multipackage interfaces include BLVDS, DDR2/DDR3/DDR4 C/A bank, RS485 and CAN Bus. There are two main multipackage topologies: Tree and fly-by.
Finding signal integrity problems
Perform a layout extraction to get the parasitics associated with the layout. Usually worst-case parasitics and best-case parasitics are extracted and used in the simulations. Because of the distributed nature of many of the impairments, electromagnetic simulation[10] is used for extraction.
If the PCB or package already exists, the designer can also measure the impairment presented by the connection using high speed instrumentation such as a vector network analyzer. For example, IEEE P802.3ap Task Force uses measured S-parameters as test cases[11] for proposed solutions to the problem of 10 Gbit/sEthernet over backplanes.
Accurate noise modeling is a must. Create a list of expected noise events, including different types of noise, such as coupling and charge sharing. Input Output Buffer Information Specification (IBIS) or circuit models may be used to represent drivers and receivers.
For each noise event, decide how to excite the circuit so that the noise event will occur.
Create a SPICE (or another circuit simulator) netlist that represents the desired excitation.
Run SPICE and record the results.
Analyze the simulation results and decide whether any re-design is required. To analyze the results quite often a data eye is generated and a timing budget is calculated. An example video for generating a data eye can be found on YouTube: An Eye is Born.
There are special purpose EDA tools[12] that help the engineer perform all these steps on each signal in a design, pointing out problems or verifying the design is ready for manufacture. In selecting which tool is best for a particular task, one must consider characteristics of each such as capacity (how many nodes or elements), performance (simulation speed), accuracy (how good are the models), convergence (how good is the solver), capability (non-linear versus linear, frequency dependent versus frequency independent etc.), and ease of use.
Fixing signal integrity problems
An IC package or PCB designer removes signal integrity problems through these techniques:
Route traces perpendicular on adjacent layers to reduce crosstalk
Increasing spacing between traces to reduce crosstalk
Providing sufficient ground (and power) connections to limit ground bounce (this sub-discipline of signal integrity is sometimes called out separately as power integrity)
Distributing power with solid plane layers to limit power supply noise
Adding a pre-emphasis filter to the transmitter driving cell[13]
1 2 Louis Kossuth Scheffer; Luciano Lavagno; Grant Martin (eds) (2006). Electronic design automation for integrated circuits handbook. Boca Raton, Florida: CRC/Taylor & Francis. ISBN0-8493-3096-3.{{cite book}}: |author= has generic name (help)CS1 maint: multiple names: authors list (link) A survey of the field of electronic design automation. Portions of IC section of this article were derived (with permission) from Vol II, Chapter 21, Noise Considerations in Digital ICs, by Vinod Kariat.
↑ Howard W. Johnson; Martin Graham (1993). High speed digital design a handbook of black magic. Englewood Cliffs, New Jersey: Prentice Hall PTR. ISBN0-13-395724-1. A book for digital PCB designers, highlighting and explaining analog circuit principles relevant to high-speed digital design.
↑ Breed, Gary (August 2008). "High Speed Digital Design Benefits from Recent EDA Tools Development"(PDF). High Frequency Electronics. p.52. Retrieved May 1, 2009. ...with continued increase in clock rates of digital circuits, the realms of RF and digital circuits are now more closely tied than ever before.
Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining millions or billions of MOS transistors onto a single chip. VLSI began in the 1970s when MOS integrated circuit chips were developed and then widely adopted, enabling complex semiconductor and telecommunication technologies. The microprocessor and memory chips are VLSI devices.
Electromagnetic compatibility (EMC) is the ability of electrical equipment and systems to function acceptably in their electromagnetic environment, by limiting the unintentional generation, propagation and reception of electromagnetic energy which may cause unwanted effects such as electromagnetic interference (EMI) or even physical damage to operational equipment. The goal of EMC is the correct operation of different equipment in a common electromagnetic environment. It is also the name given to the associated branch of electrical engineering.
In electrical engineering, a ground plane is an electrically conductive surface, usually connected to electrical ground.
A printed circuit board (PCB), also called printed wiring board (PWB), is a medium used to connect or "wire" components to one another in a circuit. It takes the form of a laminated sandwich structure of conductive and insulating layers: each of the conductive layers is designed with a pattern of traces, planes and other features etched from one or more sheet layers of copper laminated onto and/or between sheet layers of a non-conductive substrate. Electrical components may be fixed to conductive pads on the outer layers in the shape designed to accept the component's terminals, generally by means of soldering, to both electrically connect and mechanically fasten them to it. Another manufacturing process adds vias, plated-through holes that allow interconnections between layers.
A breadboard, solderless breadboard, or protoboard is a construction base used to build semi-permanent prototypes of electronic circuits. Unlike a perfboard or stripboard, breadboards do not require soldering or destruction of tracks and are hence reusable. For this reason, breadboards are also popular with students and in technological education.
In digital electronics, the fan-out is the number of gate inputs driven by the output of another single logic gate.
Integrated circuit packaging is the final stage of semiconductor device fabrication, in which the die is encapsulated in a supporting case that prevents physical damage and corrosion. The case, known as a "package", supports the electrical contacts which connect the device to a circuit board.
A mixed-signal integrated circuit is any integrated circuit that has both analog circuits and digital circuits on a single semiconductor die. Their usage has grown dramatically with the increased use of cell phones, telecommunications, portable electronics, and automobiles with electronics and digital sensors.
Differential signalling is a method for electrically transmitting information using two complementary signals. The technique sends the same electrical signal as a differential pair of signals, each in its own conductor. The pair of conductors can be wires in a twisted-pair or ribbon cable or traces on a printed circuit board.
In semiconductor design, standard-cell methodology is a method of designing application-specific integrated circuits (ASICs) with mostly digital-logic features. Standard-cell methodology is an example of design abstraction, whereby a low-level very-large-scale integration (VLSI) layout is encapsulated into an abstract logic representation.
Integrated circuit design, semiconductor design, chip design or IC design, is a sub-field of electronics engineering, encompassing the particular logic and circuit design techniques required to design integrated circuits, or ICs. ICs consist of miniaturized electronic components built into an electrical network on a monolithic semiconductor substrate by photolithography.
In electronics, crosstalk is a phenomenon by which a signal transmitted on one circuit or channel of a transmission system creates an undesired effect in another circuit or channel. Crosstalk is usually caused by undesired capacitive, inductive, or conductive coupling from one circuit or channel to another.
In an integrated circuit, a signal can couple from one node to another via the substrate. This phenomenon is referred to as substrate coupling or substrate noise coupling.
In electronics, a decoupling capacitor is a capacitor used to decouple one part of a circuit from another. Noise caused by other circuit elements is shunted through the capacitor, reducing its effect on the rest of the circuit. For higher frequencies, an alternative name is bypass capacitor as it is used to bypass the power supply or other high-impedance component of a circuit.
In the design of integrated circuits, power network design is the analysis and design of on-chip conductor networks that distribute electrical power on a chip. As in all engineering, this involves tradeoffs - the network must have adequate performance, be sufficiently reliable, but should not use more resources than required.
An electronic circuit is composed of individual electronic components, such as resistors, transistors, capacitors, inductors and diodes, connected by conductive wires or traces through which electric current can flow. It is a type of electrical circuit. For a circuit to be referred to as electronic, rather than electrical, generally at least one active component must be present. The combination of components and wires allows various simple and complex operations to be performed: signals can be amplified, computations can be performed, and data can be moved from one place to another.
Bead probe technology (BPT) is technique used to provide electrical access to printed circuit board (PCB) circuitry for performing in-circuit testing (ICT). It makes use of small beads of solder placed onto the board's traces to allow measuring and controlling of the signals using a test probe. This permits test access to boards on which standard ICT test pads are not feasible due to space constraints.
On-die termination (ODT) is the technology where the termination resistor for impedance matching in transmission lines is located inside a semiconductor chip instead of on a printed circuit board (PCB).
In electronic design automation, parasitic extraction is the calculation of the parasitic effects in both the designed devices and the required wiring interconnects of an electronic circuit: parasitic capacitances, parasitic resistances and parasitic inductances, commonly called parasitic devices, parasitic components, or simply parasitics.
Power integrity or PI is an analysis to check whether the desired voltage and current are met from source to destination. Today, power integrity plays a major role in the success and failure of new electronic products. There are several coupled aspects of PI: on the chip, in the chip package, on the circuit board, and in the system. Four main issues must be resolved to ensure power integrity at the printed circuit board level:
Keep the voltage ripple at the chips pads lower than the specification
Control ground bounce
Control electromagnetic interference and maintain electromagnetic compatibility: the power distribution network is generally the largest set of conductors on the circuit board and therefore the largest (unwanted) antenna for emission and reception of noise.
Maintaining a proper DC voltage level at the load at high currents. A modern processor or field-programmable gate array can pull 1–100A from a sub-1V power rail with voltage margins in the tens of millivolts. Very little DC voltage drop can thus be tolerated on the power distribution network.
References
Howard Johnson; Martin Graham. (2002). High-speed signal propagation: advanced black magic. Upper Saddle River, New Jersey: Prentice Hall PTR. ISBN0-13-084408-X. Advanced-level reference text for experienced digital designers who want to press their designs to the upper limits of speed and distance.
Stephen H. Hall; Garrett W. Hall; James A. McCall. (2000). High speed digital system design: a handbook of interconnect theory and design practices. New York: Wiley. ISBN0-471-36090-2.
William J. Dally; John W. Poulton. (1999). Digital systems engineering. Cambridge: Cambridge Univ. Press. ISBN0-521-59292-5. Textbook on the problems of building digital systems, including signal integrity.
Douglas Brooks. (2003). Signal integrity issues and printed circuit board design. Upper Saddle River, New Jersey: Prentice Hall PTR. ISBN0-13-141884-X. This book approaches electrical engineering and signal integrity principles from a basic level, assuming little prior understanding.
Geoff Lawday; David Ireland & Greg Edlund. (2008). A signal integrity engineer's companion: real-time test and measurement and design simulation. Upper Saddle River, New Jersey: Prentice Hall. ISBN978-0-13-186006-3.
Raj; A. Ege Engin. (2008). Power integrity modeling and design for semiconductors and systems. Upper Saddle River, New Jersey: Prentice Hall. ISBN978-0-13-615206-4. Using realistic case studies and downloadable software examples, two leading experts demonstrate today's best techniques for designing and modeling interconnects to efficiently distribute power and minimize noise. The authors carefully introduce the core concepts of power distribution design, systematically present and compare leading techniques for modeling noise, and link these techniques to specific applications. Their many examples range from the simplest (using analytical equations to compute power supply noise) through complex system-level applications.
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