Power integrity

Power integrity or PI involves a series of electronic engineering efforts aimed at ensuring that power supply subsystems adequately support the performance of an entire electronic system ^[1] .

PI engineering focuses on designing and evaluating power supply subsystems to prevent any degradation in system performance due to potential adverse effects from the power supplies. For instance, a noisy power supply can cause audible or visible disturbances or slow down data communication. PI engineering employs various methods to minimize or eliminate such noise. The effectiveness of PI engineering is measured by the overall system performance, even though it specifically addresses power supply circuits. In other words, PI engineering identifies circuit blocks that are sensitive to power supply perturbations and requires careful attention.

PI is essential for achieving successful signal integrity (SI) engineering, which deals with impedance matching among multiple elements. Like SI, PI also ensures proper connections between a power supply and a load device, which is often a concern for SI. This connection path is known as a power delivery network (PDN), and tuning the PDN path from the power source to load devices is referred to as PDN impedance design.

History

Before 2000

In the Computer industry, the increasing power demands of Microprocessors necessitated dedicated decoupling capacitor designs for power supply buses on printed circuit boards. ^{[2] [3]} As a microprocessor transitions between idle and heavy computation states, it draws rapidly changing current from its power supply unit, often referred to as a voltage regulator module (VRM).

At a high level, this effort involved balancing two scenarios:

From heavy computation state to idle state

When a microprocessor suddenly stops drawing current from the VRM, the slower response time of the VRM compared to the microprocessor causes an increase in power bus voltage (overshoot). This can lead to potential over-voltage damage to the microprocessor.

From idle state to heavy computation state

When a microprocessor suddenly starts drawing electric charge from a power bus, the instantaneous current supply comes from decoupling capacitors until the VRM begins supplying current. This causes a drop in power bus voltage (undershoot), potentially leading to digital data loss as the microprocessor's internal logic circuitry may fail to maintain digital high or low states.

The engineering efforts involved in designing these decoupling capacitors laid the foundation for PDN impedance design.

Importance of Power Integrity ^[4]

• Stable operation
• Reduced noise and interference
• Thermal management
• Component longevity
• EMI Compliance and reliability

Key Elements in Power Integrity

• Power Delivery Network (PDN)
• Voltage Ripple and Noise
• Impedance Control
• Decoupling Capacitors
• Ground Planes

Power distribution network

Power Distribution Network

The current path from the power supply through the PCB and IC package to the die (consumer) is called the power distribution network. Its role is to transfer the power to the consumers with little DC voltage drop, and to allow little ripple induced by dynamic current at the consumer (switching current). The DC voltage drop occurs if there is too much resistance in the plane or power traces leading from the VRM (Voltage Regulator Module) to the consumer. This can be countered by raising the voltage on the VRM, or extending the "sense" point of the VRM to the consumer.

Dynamic current occurs when the consumer switches its transistors, typically triggered by a clock signal. This dynamic current can be considerably larger than the static current (internal leakage) of the consumer. This fast change in current consumption can pull the voltage of the rail down, or cause it to spike, creating a voltage ripple. This change in current happens much faster than the VRM can react. The switching current must therefore be handled by decoupling capacitors.

The noise or voltage ripple must be handled differently depending on the frequency of operation. The highest frequencies must be handled on-die. This noise is decoupled by parasitic coupling on the die, and capacitive coupling between metal layers. Frequencies above 50–100 MHz must be handled on the package.^{[ citation needed ]} This is done by on-package capacitors. Frequencies below 100 MHz are handled on the PCB by plane capacitance and using decoupling capacitors. Capacitors work on different frequencies depending on their type, capacitance and physical size. It is therefore necessary to utilize multiple capacitors of different sizes to ensure a low PDN impedance across the frequency range.

The physical size of the capacitors affect its parasitic inductance. The parasitic inductance creates impedance spikes at certain frequencies. Physically smaller capacitors are therefore better. The placement of the capacitors is of varying importance depending on its frequency of operation. The smallest value capacitors should be as close as possible to the consumer to minimize the AC current loop area. Larger capacitors in the microfarad range can be placed more or less anywhere. ^{[5] [6]}

Target impedance

The target impedance is the impedance at which the ripple created by the dynamic current of the specific consumer is within the specified range. The target impedance is given by the following equation ^[7]

${\displaystyle Z_{\textrm {Target}}={\frac {\Delta V}{\Delta I}}[\Omega ]}$

In addition to the target impedance, it is important to know which frequencies it applies, and at which frequency the consumer package is responsible (this is specified in the datasheet of the specific consumer IC).

PDN with frequencies of operation

On-package capacitors

Power Integrity Tools

• "K-SIM". KEMET. Retrieved 2018-03-18.
• "CST PDN ANALYZER". Altium. Retrieved 2018-03-18.
• "W3036E Conducted EMI (CEMI) with PIPro". Keysight. Retrieved 2025-01-02.
• "HyperLynx Power Integrity". Siemens. 2018. Retrieved 2018-03-18.

See also

• Signal integrity
• Electromagnetic interference
• Electromagnetic compatibility

Notes

1. Sandler 2019.
2. Hubing et al. 1995, pp. 155–166.
3. Smith et al. 1999, pp. 284–291.
4. Siemens 2018.
5. Signal Integrity Journal 2016a.
6. Signal Integrity Journal 2016b.
7. Smith & Bogatin 2017.

References

Journals

• T. H. Hubing; J. L. Drewniak; Van Doren, T. P.; D. M. Hockanson (1995). "Power bus decoupling on multilayer printed circuit boards". IEEE Transactions on Electromagnetic Compatibility. 37 (2). IEEE: 155–166. doi:10.1109/15.385878.
• L. D. Smith; R. E. Anderson; D. W. Forehand; T. J. Pelc; T. Roy (1999). "Power distribution system design methodology and capacitor selection for modern CMOS technology". IEEE Transactions on Advanced Packaging. 22 (3). IEEE: 284–291. doi:10.1109/6040.784476. ISSN   1557-9980.
• I. Novak; L. M. Noujeim; V. St Cyr; N. Biunno; A. Patel; G. Korony; A. Ritter (2002). "Distributed matched bypassing for board-level power distribution networks". IEEE Transactions on Advanced Packaging. 25 (2). IEEE: 230–243. doi:10.1109/TADVP.2002.803265. ISSN   1557-9980.

Books

• Bogatin, Eric (2009-07-13). Signal and Power Integrity - Simplified. Pearson Education. ISBN   978-0-13-703503-8.
• Lee W. Ritchey (2003). Right the First Time—A Practical Handbook on High-speed PCB and System Design. SPEEDING EDGE. ISBN   978-0-9741936-0-1.
• Smith, Larry D.; Bogatin, Eric (2017-03-30). Principles of Power Integrity for PDN Design-Simplified: Robust and Cost Effective Design for High Speed Digital Products. Pearson. ISBN   978-0132735551.

Web Pages

• Sandler, Steve (2019-01-18). "Power Electronics vs. Power Integrity". Signal Integrity Journal. Retrieved 2025-01-03.
• Sandler, Steve; Barnes, Heidi (2016-11-28). "Power Integrity Course - Part 1 (EDI CON USA 2016)". Signal Integrity Journal. Retrieved 2025-01-02.
• Sandler, Steve; Barnes, Heidi (2016-11-28). "Power Integrity Course - Part 2 (EDI CON USA 2016)". Signal Integrity Journal. Retrieved 2025-01-02.
• "Simulating FPGA Power Integrity Using S-Parameter Models" (PDF). Xilinx. 2012-01-30. Retrieved 2018-03-18.