System in a package

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CAD drawing of a SiP multi-chip which contains a processor, memory and storage on a single substrate System in package.png
CAD drawing of a SiP multi-chip which contains a processor, memory and storage on a single substrate

A system in a package (SiP) or system-in-package is a number of integrated circuits (ICs) enclosed in one chip carrier package or encompassing an IC package substrate that may include passive components and perform the functions of an entire system. The ICs may be stacked using package on package, placed side by side, and/or embedded in the substrate. [1] The SiP performs all or most of the functions of an electronic system, and is typically used when designing components for mobile phones, digital music players, etc. [2] Dies containing integrated circuits may be stacked vertically on the package substrate. They are internally connected by fine wires that are bonded to the package substrate. Alternatively, with a flip chip technology, solder bumps are used to join stacked chips together and to the package substrate, or even both techniques can be used in a single package. SiPs are like systems on a chip (SoCs) but less tightly integrated and not on a single semiconductor die. [3]

Contents

SIPs can be used either to reduce the size of a system, improve performance or to reduce costs. [4] [5] The technology evolved from multi chip module (MCM) technology, the difference being that SiPs also use die stacking, which stacks several chips or dies on top of each other. [6] [7]

Technology

SiP dies can be stacked vertically or tiled horizontally, with techniques like chiplets or quilt packaging. SiPs connect the dies with standard off-chip wire bonds or solder bumps, unlike slightly denser three-dimensional integrated circuits which connect stacked silicon dies with conductors running through the die using through-silicon vias. Many different 3D packaging techniques have been developed for stacking many fairly standard chip dies into a compact area. [8]

SiPs can contain several chips or diessuch as a specialized processor, DRAM, flash memory combined with passive components resistors and capacitors all mounted on the same substrate. This means that a complete functional unit can be built in a single package, so that few external components need to be added to make it work. This is particularly valuable in space constrained environments like MP3 players and mobile phones as it reduces the complexity of the printed circuit board and overall design. Despite its benefits, this technique decreases the yield of fabrication since any defective chip in the package will result in a non-functional packaged integrated circuit, even if all other modules in that same package are functional.

SiPs are in contrast to the common system on a chip (SoC) integrated circuit architecture which integrates components based on function into a single circuit die. An SoC will typically integrate a CPU, graphics and memory interfaces, hard-disk and USB connectivity, random-access and read-only memories, and secondary storage and/or their controllers on a single die. In comparison an SiP would connect these modules as discrete components in one or more chip packages or dies. An SiP resembles the common traditional motherboard-based PC architecture, as it separates components based on function and connects them through a central interfacing circuit board. An SiP has a lower grade of integration in comparison to an SoC. Hybrid integrated circuits (HICs) are somewhat similar to SiPs, however they tend to handle analog signals [9] whereas SiPs usually handle digital signals, [10] [11] [12] [13] [14] because of this HICs use older or less advanced technology (tend to use single layer circuit boards or substrates, not use die stacking, do not use flip chip or BGA for connecting components or dies, use only wire bonding for connecting dies or Small outline integrated circuit packages, use Dual in-line packages, or Single in-line packages for interfacing outside the Hybrid IC instead of BGA, etc.). [15]

SiP technology is primarily being driven by early market trends in wearables, mobile devices and the internet of things which do not demand the high numbers of produced units as in the established consumer and business SoC market. As the internet of things becomes more of a reality and less of a vision, there is innovation going on at the system on a chip and SiP level so that microelectromechanical (MEMS) sensors can be integrated on a separate die and control the connectivity. [16]

SiP solutions may require multiple packaging technologies, such as flip chip, wire bonding, wafer-level packaging, Through-silicon vias (TSVs), chiplets and more. [17] [7]

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Related Research Articles

<span class="mw-page-title-main">Integrated circuit</span> Electronic circuit formed on a small, flat piece of semiconductor material

An integrated circuit (IC), also known as a microchip, computer chip, or simply chip, is a small electronic device made up of multiple interconnected electronic components such as transistors, resistors, and capacitors. These components are etched onto a small piece of semiconductor material, usually silicon. Integrated circuits are used in a wide range of electronic devices, including computers, smartphones, and televisions, to perform various functions such as processing and storing information. They have greatly impacted the field of electronics by enabling device miniaturization and enhanced functionality.

<span class="mw-page-title-main">Flip chip</span> Technique that flips a microchip upside down to connect it

Flip chip, also known as controlled collapse chip connection or its abbreviation, C4, is a method for interconnecting dies such as semiconductor devices, IC chips, integrated passive devices and microelectromechanical systems (MEMS), to external circuitry with solder bumps that have been deposited onto the chip pads. The technique was developed by General Electric's Light Military Electronics Department, Utica, New York. The solder bumps are deposited on the chip pads on the top side of the wafer during the final wafer processing step. In order to mount the chip to external circuitry, it is flipped over so that its top side faces down, and aligned so that its pads align with matching pads on the external circuit, and then the solder is reflowed to complete the interconnect. This is in contrast to wire bonding, in which the chip is mounted upright and fine wires are welded onto the chip pads and lead frame contacts to interconnect the chip pads to external circuitry.

<span class="mw-page-title-main">Integrated circuit packaging</span> Final stage of semiconductor device fabrication

Integrated circuit packaging is the final stage of semiconductor device fabrication, in which the die is encapsulated in a supporting case that prevents physical damage and corrosion. The case, known as a "package", supports the electrical contacts which connect the device to a circuit board.

<span class="mw-page-title-main">Mixed-signal integrated circuit</span> Integrated circuit

A mixed-signal integrated circuit is any integrated circuit that has both analog circuits and digital circuits on a single semiconductor die. Their usage has grown dramatically with the increased use of cell phones, telecommunications, portable electronics, and automobiles with electronics and digital sensors.

<span class="mw-page-title-main">Hybrid integrated circuit</span> Type of miniature electronic circuit

A hybrid integrated circuit (HIC), hybrid microcircuit, hybrid circuit or simply hybrid is a miniaturized electronic circuit constructed of individual devices, such as semiconductor devices and passive components, bonded to a substrate or printed circuit board (PCB). A PCB having components on a Printed wiring board (PWB) is not considered a true hybrid circuit according to the definition of MIL-PRF-38534.

<span class="mw-page-title-main">Multi-chip module</span> Electronic assembly containing multiple integrated circuits that behaves as a unit

A multi-chip module (MCM) is generically an electronic assembly where multiple integrated circuits, semiconductor dies and/or other discrete components are integrated, usually onto a unifying substrate, so that in use it can be treated as if it were a larger IC. Other terms for MCM packaging include "heterogeneous integration" or "hybrid integrated circuit". The advantage of using MCM packaging is it allows a manufacturer to use multiple components for modularity and/or to improve yields over a conventional monolithic IC approach.

Package on a package (PoP) is an integrated circuit packaging method to vertically combine discrete logic and memory ball grid array (BGA) packages. Two or more packages are installed atop each other, i.e. stacked, with a standard interface to route signals between them. This allows higher component density in devices, such as mobile phones, personal digital assistants (PDA), and digital cameras, at the cost of slightly higher height requirements. Stacks with more than 2 packages are uncommon, due to heat dissipation considerations.

<span class="mw-page-title-main">Through-silicon via</span> Electrical connection

In electronic engineering, a through-silicon via (TSV) or through-chip via is a vertical electrical connection (via) that passes completely through a silicon wafer or die. TSVs are high-performance interconnect techniques used as an alternative to wire-bond and flip chips to create 3D packages and 3D integrated circuits. Compared to alternatives such as package-on-package, the interconnect and device density is substantially higher, and the length of the connections becomes shorter.

<span class="mw-page-title-main">Interposer</span> Layer between an integrated circuit and a printed circuit board

An interposer is an electrical interface routing between one socket or connection to another. The purpose of an interposer is to spread a connection to a wider pitch or to reroute a connection to a different connection.

A three-dimensional integrated circuit is a MOS integrated circuit (IC) manufactured by stacking as many as 16 or more ICs and interconnecting them vertically using, for instance, through-silicon vias (TSVs) or Cu-Cu connections, so that they behave as a single device to achieve performance improvements at reduced power and smaller footprint than conventional two dimensional processes. The 3D IC is one of several 3D integration schemes that exploit the z-direction to achieve electrical performance benefits in microelectronics and nanoelectronics.

<span class="mw-page-title-main">Integrated passive devices</span>

Integrated passive devices (IPDs), also known as integrated passive components (IPCs) or embedded passive components (EPC), are electronic components where resistors (R), capacitors (C), inductors (L)/coils/chokes, microstriplines, impedance matching elements, baluns or any combinations of them are integrated in the same package or on the same substrate. Sometimes integrated passives can also be called as embedded passives, and still the difference between integrated and embedded passives is technically unclear. In both cases passives are realized in between dielectric layers or on the same substrate.

<span class="mw-page-title-main">Thick-film technology</span>

Thick-film technology is used to produce electronic devices/modules such as surface mount devices modules, hybrid integrated circuits, heating elements, integrated passive devices and sensors. The main manufacturing technique is screen printing (stenciling), which in addition to use in manufacturing electronic devices can also be used for various graphic reproduction targets. It became one of the key manufacturing/miniaturisation techniques of electronic devices/modules during 1950s. Typical film thickness – manufactured with thick film manufacturing processes for electronic devices – is 0.0001 to 0.1 mm.

<span class="mw-page-title-main">Wafer-level packaging</span> Means of packaging an integrated circuit

Wafer-level packaging (WLP) is a process in integrated circuit manufacturing where packaging components are attached to an integrated circuit (IC) before the wafer – on which the IC is fabricated – is diced. In WLP, the top and bottom layers of the packaging and the solder bumps are attached to the integrated circuits while they are still in the wafer. This process differs from a conventional process, in which the wafer is sliced into individual circuits (dice) before the packaging components are attached.

A semiconductor package is a metal, plastic, glass, or ceramic casing containing one or more discrete semiconductor devices or integrated circuits. Individual components are fabricated on semiconductor wafers before being diced into die, tested, and packaged. The package provides a means for connecting it to the external environment, such as printed circuit board, via leads such as lands, balls, or pins; and protection against threats such as mechanical impact, chemical contamination, and light exposure. Additionally, it helps dissipate heat produced by the device, with or without the aid of a heat spreader. There are thousands of package types in use. Some are defined by international, national, or industry standards, while others are particular to an individual manufacturer.

A chiplet is a tiny integrated circuit (IC) that contains a well-defined subset of functionality. It is designed to be combined with other chiplets on an interposer in a single package to create a complex component such as a computer processor. Each chiplet in a computer processor provides only a portion of the processor's total functionality. A set of chiplets can be implemented in a mix-and-match "Lego-like" assembly. This provides several advantages over a traditional system on chip (SoC) which is monolithic as it comprises a single silicon die:

A 2.5D integrated circuit is an advanced packaging technique that combines multiple integrated circuit dies in a single package without stacking them into a three-dimensional integrated circuit (3D-IC) with through-silicon vias (TSVs). The term "2.5D" originated when 3D-ICs with TSVs were quite new and still very difficult. Chip designers realized that many of the advantages of 3D integration could be approximated by placing bare dies side by side on an interposer instead of stacking them vertically. If the pitch is very fine and the interconnect very short, the assembly can be packaged as a single component with better size, weight, and power characteristics than a comparable 2D circuit board assembly. This half-way 3D integration was facetiously named "2.5D" and the name stuck. Since then, 2.5D has proven to be far more than just "half-way to 3D." Some benefits:

Glossary of microelectronics manufacturing terms

Advanced packaging is the aggregation and interconnection of components before traditional integrated circuit packaging where a single die is packaged. Advanced packaging allows multiple devices, including electrical, mechanical, or semiconductor devices, to be merged and packaged as a single electronic device. Advanced packaging uses processes and techniques that are typically performed at semiconductor fabrication facilities, unlike traditional integrated circuit packaging, which does not. Advanced packaging thus sits between fabrication and traditional packaging -- or, in other terminology, between BEoL and post-fab. Advanced packaging includes multi-chip modules, 3D ICs, 2.5D ICs, heterogeneous integration, fan-out wafer-level packaging, system-in-package, quilt packaging, combining logic (processors) and memory in a single package, die stacking, wafer bonding/stacking, several chiplets or dies in a package, combinations of these techniques, and others. 2.5D and 3D ICs are also called 2.5D or 3D packages.

Universal Chiplet Interconnect Express (UCIe) is an open specification for a die-to-die interconnect and serial bus between chiplets. It is co-developed by AMD, Arm, ASE Group, Google Cloud, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC.

References

  1. INEMI System in Package Technology, thor.inemi.org, June 2005, Retrieved 2024-01-24
  2. By Pushkar Apte, W. R. Bottoms, William Chen and George Scalise, IEEE Spectrum. “Advanced Chip Packaging Satisfies Smartphone Needs.” February 8, 2011. Retrieved July 31, 2015.
  3. System-in-Package (SiP), a success story // AnySilicon, February 21, 2020
  4. "System-in-Package (SiP), a success story". 21 February 2020.
  5. "Here's why System-in-Package is a big deal for Apple's upcoming iWatch, and everything else". 30 April 2014.
  6. "MCM, SiP, SoC, and Heterogeneous Integration Defined and Explained". 7 August 2017.
  7. 1 2 "SiP is the new SoC @ 56thDAC". 21 February 2024.
  8. By R. Wayne Johnson, Mark Strickland and David Gerke, NASA Electronic Parts and Packaging Program. “3-D Packaging: A Technology Review.” June 23, 2005. Retrieved July 31, 2015.
  9. "Definition of hybrid microcircuit".
  10. "The Apple Watch Review".
  11. "Apple Watch Teardown". 23 April 2015.
  12. "Analysis of Apple Watch's S1 chip reveals 30 individual components in 'very unique' package". 7 May 2015.
  13. "Introduction to MEMS Microphone Technology—Analog vs Digital Microphones - Technical Articles".
  14. All components in the Apple S1 SIP have digital interfaces for example amplifiers, the STM32 microcontroller, gyroscopes, MEMS microphones, power management ICs, NFC chips which can be seen by looking at their datasheets or datasheets of similar products from the same manufacturers like https://www.analog.com/media/en/technical-documentation/data-sheets/MAX98390.pdf https://www.renesas.com/us/en/document/dst/da9080-datasheet https://www.st.com/resource/en/datasheet/lsm6dsox.pdf www.sensors.ch/doc/wearables_eloy_markets.pdf www.alldatasheet.com/datasheet-pdf/pdf/1132058/BOARDCOM/BCM4334X.html
  15. Ko, Cheng-Ta; Yang, Henry; Lau, John; Li, Ming; Li, Margie; Lin, Curry; Lin, J. W.; Chang, Chieh-Lin; Pan, Jhih-Yuan; Wu, Hsing-Hui; Chen, Yu-Hua; Chen, Tony; Xu, Iris; Lo, Penny; Fan, Nelson (2018-10-01). "Design, Materials, Process, and Fabrication of Fan-Out Panel-Level Heterogeneous Integration". Journal of Microelectronics and Electronic Packaging. 15 (4): 141–147. doi:10.4071/imaps.734552. ISSN   1551-4897. S2CID   226940879.
  16. By Ed Sperling, Semiconductor Engineering. “Why Packaging Matters.” November 19, 2015. Retrieved March 16, 2016.
  17. By Tech Search International and Chip Scale Review Staff, Chip Scale Review. “Major OSATs positioned for growth opportunities in SiP.” May/June Issue. Retrieved June 22, 2016.