Chiplet

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A chiplet [1] [2] [3] [4] is a tiny integrated circuit (IC) that contains a well-defined subset of functionality. It is designed to be combined with other chiplets on an interposer in a single package to create a complex component such as a computer processor. Each chiplet in a computer processor provides only a portion of the processor's total functionality. A set of chiplets can be implemented in a mix-and-match "Lego-like" assembly. This provides several advantages over a traditional system on chip (SoC) which is monolithic as it comprises a single silicon die:

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Multiple chiplets working together in a single integrated circuit may be called a multi-chip module, hybrid IC, 2.5D IC, or an advanced package.

Chiplets may be connected with standards such as UCIe, bunch of wires (BoW), AIB, OpenHBI, and OIF XSR. [8] [9] Chiplets not designed by the same company must be designed with interoperability in mind. [10]

The term was coined by University of California, Berkeley professor John Wawrzynek as a component of the RAMP Project (research accelerator for multiple processors) in 2006 [11] [12] extension for the Department of Energy.

Common examples include:

See also

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Advanced packaging is the aggregation and interconnection of components before traditional integrated circuit packaging where a single die is packaged. Advanced packaging allows multiple devices, including electrical, mechanical, or semiconductor devices, to be merged and packaged as a single electronic device. Advanced packaging uses processes and techniques that are typically performed at semiconductor fabrication facilities, unlike traditional integrated circuit packaging, which does not. Advanced packaging thus sits between fabrication and traditional packaging -- or, in other terminology, between BEoL and post-fab. Advanced packaging includes multi-chip modules, 3D ICs, 2.5D ICs, heterogeneous integration, fan-out wafer-level packaging, system-in-package, quilt packaging, combining logic (processors) and memory in a single package, die stacking, wafer bonding/stacking, several chiplets or dies in a package, combinations of these techniques, and others. 2.5D and 3D ICs are also called 2.5D or 3D packages.

References

  1. Brookes (25 July 2021). "What Is a Chiplet?". How-To Geek. Retrieved 28 December 2021.
  2. "Chiplet". WikiChip. Retrieved 28 December 2021.
  3. Semi Engineering "Chiplets" Retrieved 5 December 2022
  4. Don Scansen, EE Times "Chiplets: A Short History Retrieved 5 December 2022
  5. Keeler. "Common Heterogeneous Integration and IP Reuse Strategies (CHIPS)". DARPA. Retrieved 28 December 2021.
  6. Kenyon (6 April 2021). "Heterogeneous Integration and the Evolution of IC Packaging". EE Times Europe. Retrieved 28 December 2021.
  7. Bertin, Claude L.; Su, Lo-Soun; Van Horn, Jody (2001). "Known Good die (KGD)". Area Array Interconnection Handbook. SpringerLink. pp. 149–200. doi:10.1007/978-1-4615-1389-6_4. ISBN   978-1-4613-5529-8 . Retrieved 7 October 2022.
  8. "Waiting for Chiplet Standards". 25 March 2021.
  9. "Is UCIe Really Universal?". 22 November 2022.
  10. "UCIe Goes Back to the Drawing Board". 22 February 2024.
  11. Patterson, D.A. (March 2006). "RAMP: Research accelerator for multiple processors - a community vision for a shared experimental parallel HW/SW platform". 2006 IEEE International Symposium on Performance Analysis of Systems and Software. pp. 1–. doi:10.1109/ISPASS.2006.1620784. ISBN   1-4244-0186-0.
  12. Wawrzynek, John (2015-05-01). "Accelerating Science Driven System Design With RAMP". UCB. doi:10.2172/1186854. OSTI   1186854.

Further reading