Advanced packaging (semiconductors)

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Advanced packaging [1] is the aggregation and interconnection of components before traditional integrated circuit packaging where a single die is packaged. Advanced packaging allows multiple devices, including electrical, mechanical, or semiconductor devices, to be merged and packaged as a single electronic device. Advanced packaging uses processes and techniques that are typically performed at semiconductor fabrication facilities, unlike traditional integrated circuit packaging, which does not. Advanced packaging thus sits between fabrication and traditional packaging -- or, in other terminology, between BEoL and post-fab. Advanced packaging includes multi-chip modules, 3D ICs, [2] 2.5D ICs, [2] heterogeneous integration, [3] fan-out wafer-level packaging, [2] system-in-package, quilt packaging, combining logic (processors) and memory in a single package, die stacking, wafer bonding/stacking, several chiplets or dies in a package, [2] combinations of these techniques, and others. 2.5D and 3D ICs are also called 2.5D or 3D packages. [3]

Advanced packaging can help achieve performance gains through the integration of several devices in one package and associated efficiency gains (by reducing the distances signals have to travel, in other words reducing signal paths), and allowing for high numbers of connections between devices, without having to resort to smaller transistors which have become increasingly more difficult to manufacture. [4] Fan-out packaging is seen as a low cost option for advanced packaging. [5]

Advanced Packaging is considered fundamental in expanding the Moore’s Law. [6] [2] An example of heterogeneus integration is Intel's EMIB, which uses "bridges" made on silicon substrates, to connect different dies together. [7] Another example is TSMC's CoWoS technology which uses an interposer. [8] [9] Advanced packaging is closely related to system integration, [10] used in systems related to "artificial intelligence, machine learning, automotive, and 5G" to name a few. [11] System integration consists of "ways to avoid putting everything on a single chip by creating a system that interconnects multiple smaller chips, or chiplets" [12] Advanced packages can have chiplets from several vendors. [13] [14] To enable this, standards for connecting chiplets have been developed such as UCie. [15]

Related Research Articles

<span class="mw-page-title-main">Integrated circuit</span> Electronic circuit formed on a small, flat piece of semiconductor material

An integrated circuit (IC), also known as a microchip, computer chip, or simply chip, is a small electronic device made up of multiple interconnected electronic components such as transistors, resistors, and capacitors. These components are etched onto a small piece of semiconductor material, usually silicon. Integrated circuits are used in a wide range of electronic devices, including computers, smartphones, and televisions, to perform various functions such as processing and storing information. They have greatly impacted the field of electronics by enabling device miniaturization and enhanced functionality.

<span class="mw-page-title-main">Semiconductor device fabrication</span> Manufacturing process used to create integrated circuits

Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically integrated circuits (ICs) such as computer processors, microcontrollers, and memory chips. It is a multiple-step photolithographic and physico-chemical process during which electronic circuits are gradually created on a wafer, typically made of pure single-crystal semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.

<span class="mw-page-title-main">Wafer (electronics)</span> Thin slice of semiconductor used for the fabrication of integrated circuits

In electronics, a wafer is a thin slice of semiconductor, such as a crystalline silicon, used for the fabrication of integrated circuits and, in photovoltaics, to manufacture solar cells.

Fabless manufacturing is the design and sale of hardware devices and semiconductor chips while outsourcing their fabrication to a specialized manufacturer called a semiconductor foundry. These foundries are typically, but not exclusively, located in the United States, China, and Taiwan. Fabless companies can benefit from lower capital costs while concentrating their research and development resources on the end market. Some fabless companies and pure play foundries may offer integrated-circuit design services to third parties.

<span class="mw-page-title-main">Multi-chip module</span> Electronic assembly containing multiple integrated circuits that behaves as a unit

A multi-chip module (MCM) is generically an electronic assembly where multiple integrated circuits, semiconductor dies and/or other discrete components are integrated, usually onto a unifying substrate, so that in use it can be treated as if it were a larger IC. Other terms for MCM packaging include "heterogeneous integration" or "hybrid integrated circuit". The advantage of using MCM packaging is it allows a manufacturer to use multiple components for modularity and/or to improve yields over a conventional monolithic IC approach.

<span class="mw-page-title-main">System in a package</span> Electronic component

A system in a package (SiP) or system-in-package is a number of integrated circuits (ICs) enclosed in one chip carrier package or encompassing an IC package substrate that may include passive components and perform the functions of an entire system. The ICs may be stacked using package on package, placed side by side, and/or embedded in the substrate. The SiP performs all or most of the functions of an electronic system, and is typically used when designing components for mobile phones, digital music players, etc. Dies containing integrated circuits may be stacked vertically on the package substrate. They are internally connected by fine wires that are bonded to the package substrate. Alternatively, with a flip chip technology, solder bumps are used to join stacked chips together and to the package substrate, or even both techniques can be used in a single package. SiPs are like systems on a chip (SoCs) but less tightly integrated and not on a single semiconductor die.

<span class="mw-page-title-main">Multi-project wafer service</span>

Multi-project chip (MPC), and multi-project wafer (MPW) semiconductor manufacturing arrangements allow customers to share tooling and microelectronics wafer fabrication cost between several designs or projects.

Package on a package (PoP) is an integrated circuit packaging method to vertically combine discrete logic and memory ball grid array (BGA) packages. Two or more packages are installed atop each other, i.e. stacked, with a standard interface to route signals between them. This allows higher component density in devices, such as mobile phones, personal digital assistants (PDA), and digital cameras, at the cost of slightly higher height requirements. Stacks with more than 2 packages are uncommon, due to heat dissipation considerations.

<span class="mw-page-title-main">Through-silicon via</span> Electrical connection

In electronic engineering, a through-silicon via (TSV) or through-chip via is a vertical electrical connection (via) that passes completely through a silicon wafer or die. TSVs are high-performance interconnect techniques used as an alternative to wire-bond and flip chips to create 3D packages and 3D integrated circuits. Compared to alternatives such as package-on-package, the interconnect and device density is substantially higher, and the length of the connections becomes shorter.

<span class="mw-page-title-main">Interposer</span> Layer between an integrated circuit and a printed circuit board

An interposer is an electrical interface routing between one socket or connection to another. The purpose of an interposer is to spread a connection to a wider pitch or to reroute a connection to a different connection.

A three-dimensional integrated circuit is a MOS integrated circuit (IC) manufactured by stacking as many as 16 or more ICs and interconnecting them vertically using, for instance, through-silicon vias (TSVs) or Cu-Cu connections, so that they behave as a single device to achieve performance improvements at reduced power and smaller footprint than conventional two dimensional processes. The 3D IC is one of several 3D integration schemes that exploit the z-direction to achieve electrical performance benefits in microelectronics and nanoelectronics.

eSilicon is a company engaged in semiconductor design and manufacturing services, that delivers custom ICs and IPs to OEMs.

<span class="mw-page-title-main">Integrated passive devices</span>

Integrated passive devices (IPDs), also known as integrated passive components (IPCs) or embedded passive components (EPC), are electronic components where resistors (R), capacitors (C), inductors (L)/coils/chokes, microstriplines, impedance matching elements, baluns or any combinations of them are integrated in the same package or on the same substrate. Sometimes integrated passives can also be called as embedded passives, and still the difference between integrated and embedded passives is technically unclear. In both cases passives are realized in between dielectric layers or on the same substrate.

<span class="mw-page-title-main">Wafer-level packaging</span> Means of packaging an integrated circuit

Wafer-level packaging (WLP) is a process in integrated circuit manufacturing where packaging components are attached to an integrated circuit (IC) before the wafer – on which the IC is fabricated – is diced. In WLP, the top and bottom layers of the packaging and the solder bumps are attached to the integrated circuits while they are still in the wafer. This process differs from a conventional process, in which the wafer is sliced into individual circuits (dice) before the packaging components are attached.

<span class="mw-page-title-main">ASE Group</span> Taiwanese manufacturer of semiconductor testing products

Advanced Semiconductor Engineering, Inc., previously known as ASE Group, is a leading provider of independent semiconductor packaging and test manufacturing services, with its headquarters in Kaohsiung, Taiwan.

<span class="mw-page-title-main">Fan-out wafer-level packaging</span>

Fan-out wafer-level packaging is an integrated circuit packaging technology, and an enhancement of standard wafer-level packaging (WLP) solutions. Fan-out packaging is seen as a low cost advanced packaging alternative to packages that use silicon interposers, such as those seen in 2.5D and 3D packages.

A chiplet is a tiny integrated circuit (IC) that contains a well-defined subset of functionality. It is designed to be combined with other chiplets on an interposer in a single package to create a complex component such as a computer processor. A set of chiplets can be implemented in a mix-and-match "Lego-like" assembly. This provides several advantages over a traditional system on chip (SoC) which is monolithic as it comprises a single silicon die:

A 2.5D integrated circuit is an advanced packaging technique that combines multiple integrated circuit dies in a single package without stacking them into a three-dimensional integrated circuit (3D-IC) with through-silicon vias (TSVs). The term "2.5D" originated when 3D-ICs with TSVs were quite new and still very difficult. Chip designers realized that many of the advantages of 3D integration could be approximated by placing bare dies side by side on an interposer instead of stacking them vertically. If the pitch is very fine and the interconnect very short, the assembly can be packaged as a single component with better size, weight, and power characteristics than a comparable 2D circuit board assembly. This half-way 3D integration was facetiously named "2.5D" and the name stuck. Since then, 2.5D has proven to be far more than just "half-way to 3D." Some benefits:

Glossary of microelectronics manufacturing terms

Universal Chiplet Interconnect Express (UCIe) is an open specification for a die-to-die interconnect and serial bus between chiplets. It is co-developed by AMD, Arm, ASE Group, Google Cloud, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC.

References

  1. ↑ "Advanced Packaging". Semiconductor Engineering. Retrieved 17 December 2021.
  2. 1 2 3 4 5 LaPedus, Mark (January 15, 2019). "More 2.5D/3D, Fan-Out Packages Ahead". Semiconductor Engineering.
  3. 1 2 LaPedus, Mark (May 20, 2021). "Advanced Packaging's Next Wave". Semiconductor Engineering.
  4. ↑ "Advanced Packaging's Next Wave". 20 May 2021.
  5. ↑ Sperling, Ed (March 5, 2018). "Toward High-End Fan-Outs". Semiconductor Engineering.
  6. ↑ Shivakumar, Sujai; Borges, Chris (June 26, 2023). "Advanced Packaging and the Future of Moore's Law" – via www.csis.org.{{cite journal}}: Cite journal requires |journal= (help)
  7. ↑ Lau, John H. (April 3, 2019). Heterogeneous Integrations. Springer. ISBN   978-981-13-7224-7 – via Google Books.
  8. ↑ https://www.anandtech.com/show/21405/tsmc-to-expand-cowos-capacity-by-60-every-year-through-2026
  9. ↑ https://semiwiki.com/semiconductor-manufacturers/tsmc/299955-highlights-of-the-tsmc-technology-symposium-2021-packaging/
  10. ↑ https://semiengineering.com/advanced-packaging-shifts-design-focus-to-system-level/
  11. ↑ https://semiengineering.com/system-level-packaging-tradeoffs/
  12. ↑ https://www.semiconductor-digest.com/new-institute-accelerates-future-of-microelectronic-system-integration-advanced-packaging/
  13. ↑ https://semiengineering.com/commercial-chiplet-ecosystem-may-be-a-decade-away/
  14. ↑ https://semiengineering.com/chiplets-taking-root-as-silicon-proven-hard-ip/
  15. ↑ https://semiengineering.com/chiplet-ip-standards-are-just-the-beginning/


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