2.5D integrated circuit

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A 2.5D integrated circuit (2.5D IC) is an advanced packaging technique [1] that combines multiple integrated circuit dies in a single package [2] without stacking them into a three-dimensional integrated circuit (3D-IC) with through-silicon vias (TSVs). [3] The term "2.5D" originated when 3D-ICs with TSVs were quite new and still very difficult. Chip designers realized that many of the advantages of 3D integration could be approximated by placing bare dies side by side on an interposer instead of stacking them vertically. If the pitch is very fine and the interconnect very short, the assembly can be packaged as a single component with better size, weight, and power characteristics than a comparable 2D circuit board assembly. This half-way 3D integration was facetiously named "2.5D" and the name stuck. [3] Since then, 2.5D has proven to be far more than just "half-way to 3D." [4] Some benefits:

Some sophisticated 2.5D assemblies even incorporate TSVs and 3D components. Several foundries now support 2.5D packaging. [7] [8] [9] [10] [11] The success of 2.5D assembly has given rise to "chiplets" – small, functional circuit blocks designed to be combined in mix-and-match fashion on interposers. Several high-end products [12] [13] already take advantage of these LEGO-style chiplets; some experts predict [14] the emergence of an industry-wide chiplet ecosystem. Interposers can be larger than the reticle size which is the maximum area that can be projected by a photolithography scanner or stepper. [15]

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<span class="mw-page-title-main">Integrated circuit</span> Electronic circuit formed on a small, flat piece of semiconductor material

An integrated circuit (IC), also known as a microchip, computer chip, or simply chip, is a small electronic device made up of multiple interconnected electronic components such as transistors, resistors, and capacitors. These components are etched onto a small piece of semiconductor material, usually silicon. Integrated circuits are used in a wide range of electronic devices, including computers, smartphones, and televisions, to perform various functions such as processing and storing information. They have greatly impacted the field of electronics by enabling device miniaturization and enhanced functionality.

<span class="mw-page-title-main">Multi-chip module</span> Electronic assembly containing multiple integrated circuits that behaves as a unit

A multi-chip module (MCM) is generically an electronic assembly where multiple integrated circuits, semiconductor dies and/or other discrete components are integrated, usually onto a unifying substrate, so that in use it can be treated as if it were a larger IC. Other terms for MCM packaging include "heterogeneous integration" or "hybrid integrated circuit". The advantage of using MCM packaging is it allows a manufacturer to use multiple components for modularity and/or to improve yields over a conventional monolithic IC approach.

<span class="mw-page-title-main">Integrated circuit design</span> Engineering process for electronic hardware

Integrated circuit design, semiconductor design, chip design or IC design, is a sub-field of electronics engineering, encompassing the particular logic and circuit design techniques required to design integrated circuits, or ICs. ICs consist of miniaturized electronic components built into an electrical network on a monolithic semiconductor substrate by photolithography.

<span class="mw-page-title-main">System in a package</span> Electronic component

A system in a package (SiP) or system-in-package is a number of integrated circuits (ICs) enclosed in one chip carrier package or encompassing an IC package substrate that may include passive components and perform the functions of an entire system. The ICs may be stacked using package on package, placed side by side, and/or embedded in the substrate. The SiP performs all or most of the functions of an electronic system, and is typically used when designing components for mobile phones, digital music players, etc. Dies containing integrated circuits may be stacked vertically on the package substrate. They are internally connected by fine wires that are bonded to the package substrate. Alternatively, with a flip chip technology, solder bumps are used to join stacked chips together and to the package substrate, or even both techniques can be used in a single package. SiPs are like systems on a chip (SoCs) but less tightly integrated and not on a single semiconductor die.

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Package on a package (PoP) is an integrated circuit packaging method to vertically combine discrete logic and memory ball grid array (BGA) packages. Two or more packages are installed atop each other, i.e. stacked, with a standard interface to route signals between them. This allows higher component density in devices, such as mobile phones, personal digital assistants (PDA), and digital cameras, at the cost of slightly higher height requirements. Stacks with more than 2 packages are uncommon, due to heat dissipation considerations.

<span class="mw-page-title-main">Through-silicon via</span> Electrical connection

In electronic engineering, a through-silicon via (TSV) or through-chip via is a vertical electrical connection (via) that passes completely through a silicon wafer or die. TSVs are high-performance interconnect techniques used as an alternative to wire-bond and flip chips to create 3D packages and 3D integrated circuits. Compared to alternatives such as package-on-package, the interconnect and device density is substantially higher, and the length of the connections becomes shorter.

<span class="mw-page-title-main">Interposer</span> Layer between an integrated circuit and a printed circuit board

An interposer is an electrical interface routing between one socket or connection to another. The purpose of an interposer is to spread a connection to a wider pitch or to reroute a connection to a different connection.

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<span class="mw-page-title-main">Quilt packaging</span>

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<span class="mw-page-title-main">High Bandwidth Memory</span> Type of memory used on processors that require high transfer rate memory

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A chiplet is a tiny integrated circuit (IC) that contains a well-defined subset of functionality. It is designed to be combined with other chiplets on an interposer in a single package. A set of chiplets can be implemented in a mix-and-match "Lego-like" assembly. This provides several advantages over a traditional system on chip (SoC):

Glossary of microelectronics manufacturing terms

Advanced packaging is the aggregation and interconnection of components before traditional integrated circuit packaging where a single die is packaged. Advanced packaging allows multiple devices, including electrical, mechanical, or semiconductor devices, to be merged and packaged as a single electronic device. Advanced packaging uses processes and techniques that are typically performed at semiconductor fabrication facilities, unlike traditional integrated circuit packaging, which does not. Advanced packaging thus sits between fabrication and traditional packaging -- or, in other terminology, between BEoL and post-fab. Advanced packaging includes multi-chip modules, 3D ICs, 2.5D ICs, heterogeneous integration, fan-out wafer-level packaging, system-in-package, quilt packaging, combining logic (processors) and memory in a single package, die stacking, several chiplets or dies in a package, combinations of these techniques, and others. 2.5D and 3D ICs are also called 2.5D or 3D packages.

Universal Chiplet Interconnect Express (UCIe) is an open specification for a die-to-die interconnect and serial bus between chiplets. It is co-developed by AMD, Arm, ASE Group, Google Cloud, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC.

References

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  5. Zhang, Xiaowu; Lin, Jong Kai; Wickramanayaka, Sunil; Zhang, Songbai; Weerasekera, Roshan; Dutta, Rahul; Chang, Ka Fai; Chui, King-Jien; Li, Hong Yu; Wee Ho, David Soon; Ding, Liang; Katti, Guruprasad; Bhattacharya, Suryanarayana; Kwong, Dim-Lee (June 1, 2015). "Heterogeneous 2.5D integration on through silicon interposer". Applied Physics Reviews. 2 (2): 021308. Bibcode:2015ApPRv...2b1308Z. doi:10.1063/1.4921463 via NASA ADS.
  6. "Cost and Thermal Analysis of High-Performance 2.5D and 3D Integrated Circuit Design Space" (PDF). Department of Electrical and Computer Engineering, UC Santa Barbara. 2016. Retrieved October 20, 2020.
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  8. "About 2.5D Technology". NHanced Semiconductors, Inc. March 23, 2017.
  9. "Custom ASICs". Marvell.com.
  10. Wong, William G. (June 6, 2016). "Q&A: A Deeper Look at Marvell's MoChi Technology". Electronicdesign.com.
  11. "What is SoIC?". Taiwan Semiconductor Manufacturing Company Ltd.
  12. "Elite Performance with AMD Ryzen 3000XT Series Processors". AMD.com. Retrieved October 20, 2020.
  13. "Marvell Introduces Industry's First Hyper-Scale Quad ARM Cortex-A72 and Dual Cortex-A53 Based Chips on Marvell's Revolutionary MoChi and FLC Architecture". Marvell.com. October 6, 2015.
  14. Moore, Samuel K. (April 12, 2019). "Intel's View of the Chiplet Revolution". IEEE Spectrum: Technology, Engineering, and Science News.
  15. "TSMC Announces 2x Reticle CoWoS for Next-Gen 5nm HPC Applications". 3 March 2020.