NVLink

Last updated
NVLink
NVidia NVLink two lines of text.png
Manufacturer Nvidia
TypeMulti-GPU and CPU technology
Predecessor Scalable Link Interface

NVLink is a wire-based serial multi-lane near-range communications link developed by Nvidia. Unlike PCI Express, a device can consist of multiple NVLinks, and devices use mesh networking to communicate instead of a central hub. The protocol was first announced in March 2014 and uses a proprietary high-speed signaling interconnect (NVHS). [1]

Contents

Principle

NVLink is a wire-based communications protocol for near-range semiconductor communications developed by Nvidia that can be used for data and control code transfers in processor systems between CPUs and GPUs and solely between GPUs. NVLink specifies a point-to-point connection with data rates of 20, 25 and 50 Gbit/s (v1.0/v2.0/v3.0+ resp.) per differential pair. For NVLink 1.0 and 2.0 eight differential pairs form a "sub-link" and two "sub-links", one for each direction, form a "link". Starting from NVlink 3.0 only four differential pairs form a "sub-link". For NVLink 2.0 and higher the total data rate for a sub-link is 25 GB/s and the total data rate for a link is 50 GB/s. Each V100 GPU supports up to six links. Thus, each GPU is capable of supporting up to 300 GB/s in total bi-directional bandwidth. [2] [3] NVLink products introduced to date focus on the high-performance application space. Announced May 14, 2020, NVLink 3.0 increases the data rate per differential pair from 25 Gbit/s to 50 Gbit/s while halving the number of pairs per NVLink from 8 to 4. With 12 links for an Ampere-based A100 GPU this brings the total bandwidth to 600 GB/s. [4] Hopper has 18 NVLink 4.0 links enabling a total of 900 GB/s bandwidth. [5] Thus NVLink 2.0, 3.0 and 4.0 all have a 50 GB/s per bidirectional link, and have 6, 12 and 18 links correspondingly.

Performance

The following table shows a basic metrics comparison based upon standard specifications:

InterconnectTransfer
rate		 Line code Effective payload rate
per lane
per direction		Max total
lane length
(PCIe: incl. 5" for PCBs)		Realized in design
PCIe 1.x2.5 GT/s 8b/10b ~0.25 GB/s20" = ~51 cm
PCIe 2.x5 GT/s8b/10b~0.5 GB/s20" = ~51 cm
PCIe 3.x8 GT/s 128b/130b ~1 GB/s20" = ~51 cm [6] Pascal,
Volta,
Turing
PCIe 4.016 GT/s128b/130b~2 GB/s8−12" = ~20−30 cm [6] Volta on Xavier
(8x, 4x, 1x),
Ampere,
Power 9
PCIe 5.032 GT/s [7] 128b/130b~4 GB/s Hopper
PCIe 6.064 GT/s1b/1b~8 GB/s Blackwell
NVLink 1.020 Gbit/s~2.5 GB/s Pascal,
Power 8+
NVLink 2.025 Gbit/s~3.125 GB/s Volta,
NVSwitch for Volta
Power 9
NVLink 3.050 Gbit/s~6.25 GB/s Ampere,
NVSwitch for Ampere
NVLink 4.0
(also as C2C, chip-to-chip)		100 Gbit/s [8] ~6.25 GB/s Hopper,
Nvidia Grace Datacenter/Server CPU
NVSwitch for Hopper
NVLink 5.0
(also as C2C, chip-to-chip)		200 Gbit/s Blackwell,
Nvidia Grace Datacenter/Server CPU
NVSwitch for Blackwell

The following table shows a comparison of relevant bus parameters for real world semiconductors that all offer NVLink as one of their options:

SemiconductorBoard/bus
delivery variant		InterconnectTransmission
technology
rate (per lane)		Lanes per
sub-link
(out + in)		Sub-link data rate
(per data direction)		Sub-link
or unit
count		Total data rate
(out + in)		Total
lanes
(out + in)		Total
data rate
(out + in)
Nvidia GP100P100 SXM, [9]
P100 PCI-E [10] 		PCIe 3.08 GT/s 16 + 16 Ⓑ128 Gbit/s = 16 GB/s116 + 16 GB/s [11] 32 Ⓒ32 GB/s
Nvidia GV100V100 SXM2, [12]
V100 PCI-E [13] 		PCIe 3.08 GT/s 16 + 16 Ⓑ128 Gbit/s = 16 GB/s116 + 16 GB/s32 Ⓒ32 GB/s
Nvidia TU104 GeForce RTX 2080,
Quadro RTX 5000		PCIe 3.08 GT/s 16 + 16 Ⓑ128 Gbit/s = 16 GB/s116 + 16 GB/s32 Ⓒ32 GB/s
Nvidia TU102GeForce RTX 2080 Ti,
Quadro RTX 6000/8000		PCIe 3.08 GT/s 16 + 16 Ⓑ128 Gbit/s = 16 GB/s116 + 16 GB/s32 Ⓒ32 GB/s
Nvidia Xavier [14] (generic)PCIe 4.0 Ⓓ
2 units: x8 (dual)
1 unit: x4 (dual)
3 units: x1 [15] [16] 		16 GT/s
8 + 8 Ⓑ
4 + 4 Ⓑ
1 + 1
128 Gbit/s = 16 GB/s
64 Gbit/s = 8 GB/s
16 Gbit/s = 2 GB/s		Ⓓ
2
1
3		Ⓓ
32 + 32 GB/s
8 + 8 GB/s
6 + 6 GB/s		40 Ⓑ80 GB/s
IBM Power9 [17] (generic)PCIe 4.016 GT/s16 + 16 Ⓑ256 Gbit/s = 32 GB/s396 + 96 GB/s96192 GB/s
Nvidia GA100 [18] [19]

Nvidia GA102 [20]

Ampere A100
(SXM4 & PCIe) [21] 		PCIe 4.016 GT/s16 + 16 Ⓑ256 Gbit/s = 32 GB/s132 + 32 GB/s32 Ⓒ64 GB/s
Nvidia GP100P100 SXM,
(not available with P100 PCI-E) [22] 		NVLink 1.020 GT/s8 + 8 Ⓐ160 Gbit/s = 20 GB/s480 + 80 GB/s64160 GB/s
Nvidia Xavier(generic)NVLink 1.0 [14] 20 GT/s [14] 8 + 8 Ⓐ160 Gbit/s = 20 GB/s [23]
IBM Power8+ (generic)NVLink 1.020 GT/s8 + 8 Ⓐ160 Gbit/s = 20 GB/s480 + 80 GB/s64160 GB/s
Nvidia GV100V100 SXM2 [24]
(not available with V100 PCI-E)		NVLink 2.025 GT/s8 + 8 Ⓐ200 Gbit/s = 25 GB/s6 [25] 150 + 150 GB/s96300 GB/s
IBM Power9 [26] (generic)NVLink 2.0
(BlueLink ports)		25 GT/s8 + 8 Ⓐ200 Gbit/s = 25 GB/s6150 + 150 GB/s96300 GB/s
NVSwitch
for Volta [27] 		(generic)
(fully connected 18x18 switch)		NVLink 2.025 GT/s8 + 8 Ⓐ200 Gbit/s = 25 GB/s2 * 8 + 2
= 18		450 + 450 GB/s288900 GB/s
Nvidia TU104 GeForce RTX 2080,
Quadro RTX 5000 [28] 		NVLink 2.025 GT/s8 + 8 Ⓐ200 Gbit/s = 25 GB/s125 + 25 GB/s1650 GB/s
Nvidia TU102GeForce RTX 2080 Ti,
Quadro RTX 6000/8000 [28] 		NVLink 2.025 GT/s8 + 8 Ⓐ200 Gbit/s = 25 GB/s250 + 50 GB/s32100 GB/s
Nvidia GA100 [18] [19] Ampere A100
(SXM4 & PCIe [21] )		NVLink 3.050 GT/s4 + 4 Ⓐ200 Gbit/s = 25 GB/s12 [29] 300 + 300 GB/s96600 GB/s
Nvidia GA102 [20] GeForce RTX 3090
Quadro RTX A6000		NVLink 3.028.125 GT/s4 + 4 Ⓐ112.5 Gbit/s = 14.0625 GB/s456.25 + 56.25 GB/s16112.5 GB/s
NVSwitch
for Ampere [30] 		(generic)
(fully connected 18x18 switch)		NVLink 3.050 GT/s8 + 8 Ⓐ400 Gbit/s = 50 GB/s2 * 8 + 2
= 18		900 + 900 GB/s2881800 GB/s
NVSwitch
for Hopper [30] 		(fully connected 64 port switch)NVLink 4.0106.25 GT/s9 + 9 Ⓐ450 Gbit/s18900 GB/s1287200 GB/s
Nvidia Grace CPU [31] Nvidia GH200 SuperchipPCIe-5 (4x, 16x) @ 512 GB/s
Nvidia Grace CPU [32] Nvidia GH200 SuperchipNVLink-C2C @ 900 GB/s
Nvidia Hopper GPU [33] Nvidia GH200 SuperchipNVLink-C2C @ 900 GB/s
Nvidia Hopper GPU [34] Nvidia GH200 SuperchipNVLink 4 (18x) @ 900 GB/s

Note: Data rate columns were rounded by being approximated by transmission rate, see real world performance paragraph

Ⓐ: sample value; NVLink sub-link bundling should be possible
Ⓑ: sample value; other fractions for the PCIe lane usage should be possible
Ⓒ: a single (no! 16) PCIe lane transfers data over a differential pair
Ⓓ: various limitations of finally possible combinations might apply due to chip pin muxing and board design
dual: interface unit can either be configured as a root hub or an end point
generic: bare semiconductor without any board design specific restrictions applied

Real world performance could be determined by applying different encapsulation taxes as well usage rate. Those come from various sources:

Those physical limitations usually reduce the data rate to between 90 and 95% of the transfer rate. NVLink benchmarks show an achievable transfer rate of about 35.3 Gbit/s (host to device) for a 40 Gbit/s (2 sub-lanes uplink) NVLink connection towards a P100 GPU in a system that is driven by a set of IBM Power8 CPUs. [35]

Usage with plug-in boards

For the various versions of plug-in boards (a yet small number of high-end gaming and professional graphics GPU boards with this feature exist) that expose extra connectors for joining them into a NVLink group, a similar number of slightly varying, relatively compact, PCB based interconnection plugs does exist. Typically only boards of the same type will mate together due to their physical and logical design. For some setups two identical plugs need to be applied for achieving the full data rate. As of now the typical plug is U-shaped with a fine grid edge connector on each of the end strokes of the shape facing away from the viewer. The width of the plug determines how far away the plug-in cards need to be seated to the main board of the hosting computer system - a distance for the placement of the card is commonly determined by the matching plug (known available plug widths are 3 to 5 slots and also depend on board type). [36] [37] The interconnect is often referred as Scalable Link Interface (SLI) from 2004 for its structural design and appearance, even if the modern NVLink based design is of a quite different technical nature with different features in its basic levels compared to the former design. Reported real world devices are: [38]

Service software and programming

For the Tesla, Quadro and Grid product lines, the NVML-API (Nvidia Management Library API) offers a set of functions for programmatically controlling some aspects of NVLink interconnects on Windows and Linux systems, such as component evaluation and versions along with status/error querying and performance monitoring. [46] Further, with the provision of the NCCL library (Nvidia Collective Communications Library) developers in the public space shall be enabled for realizing e.g. powerful implementations for artificial intelligence and similar computation hungry topics atop NVLink. [47] The page "3D Settings" » "Configure SLI, Surround, PhysX" in the Nvidia Control panel and the CUDA sample application "simpleP2P" use such APIs to realize their services in respect to their NVLink features. On the Linux platform, the command line application with sub-command "nvidia-smi nvlink" provides a similar set of advanced information and control. [38]

History

On 5 April 2016, Nvidia announced that NVLink would be implemented in the Pascal-microarchitecture-based GP100 GPU, as used in, for example, Nvidia Tesla P100 products. [48] With the introduction of the DGX-1 high performance computer base it was possible to have up to eight P100 modules in a single rack system connected to up to two host CPUs. The carrier board (...) allows for a dedicated board for routing the NVLink connections – each P100 requires 800 pins, 400 for PCIe + power, and another 400 for the NVLinks, adding up to nearly 1600 board traces for NVLinks alone (...). [49] Each CPU has direct connection to 4 units of P100 via PCIe and each P100 has one NVLink each to the 3 other P100s in the same CPU group plus one more NVLink to one P100 in the other CPU group. Each NVLink (link interface) offers a bidirectional 20 GB/sec up 20 GB/sec down, with 4 links per GP100 GPU, for an aggregate bandwidth of 80 GB/sec up and another 80 GB/sec down. [50] NVLink supports routing so that in the DGX-1 design for every P100 a total of 4 of the other 7 P100s are directly reachable and the remaining 3 are reachable with only one hop. According to depictions in Nvidia's blog-based publications, from 2014 NVLink allows bundling of individual links for increased point to point performance so that for example a design with two P100s and all links established between the two units would allow the full NVLink bandwidth of 80 GB/s between them. [51]

At GTC2017, Nvidia presented its Volta generation of GPUs and indicated the integration of a revised version 2.0 of NVLink that would allow total I/O data rates of 300 GB/s for a single chip for this design, and further announced the option for pre-orders with a delivery promise for Q3/2017 of the DGX-1 and DGX-Station high performance computers that will be equipped with GPU modules of type V100 and have NVLink 2.0 realized in either a networked (two groups of four V100 modules with inter-group connectivity) or a fully interconnected fashion of one group of four V100 modules.

In 2017-2018, IBM and Nvidia delivered the Summit and Sierra supercomputers for the US Department of Energy [52] which combine IBM's POWER9 family of CPUs and Nvidia's Volta architecture, using NVLink 2.0 for the CPU-GPU and GPU-GPU interconnects and InfiniBand EDR for the system interconnects. [53]

In 2020, Nvidia announced that they will no longer be adding new SLI driver profiles on RTX 2000 series and older from January 1, 2021. [54]

See also

Related Research Articles

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References

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  43. 1 2 "NVIDIA Quadro RTX 6000 und RTX 5000 Ready für Pre-Order". October 1, 2018.
  44. 1 2 3 "NVLink | pny.com". www.pny.com.
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  49. ↑ Anandtech.com
  50. ↑ NVIDIA Unveils the DGX-1 HPC Server: 8 Teslas, 3U, Q2 2016 by anandtech.com on April, 2016
  51. ↑ How NVLink Will Enable Faster, Easier Multi-GPU Computing by Mark Harris on November 14, 2014
  52. ↑ "Whitepaper: Summit and Sierra Supercomputers" (PDF). 2014-11-01.
  53. ↑ "Nvidia Volta, IBM POWER9 Land Contracts For New US Government Supercomputers". AnandTech. 2014-11-17.
  54. ↑ "RIP: Nvidia slams the final nail in SLI's coffin, no new profiles after 2020". PC World. 2020-09-18.
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