Open Watcom Assembler

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Open Watcom Assembler
Original author(s) Open Watcom Assembler
Operating system DOS for x86-based PCs, Microsoft Windows, Linux for x86-based PCs, OS/2 for x86-based PCs, FreeBSD for x86-based PCs.
Available in English
Type x86 assembler
Website www.openwatcom.com

Open Watcom Assembler or WASM is an x86 assembler produced by Watcom, based on the Watcom Assembler found in Watcom C/C++ compiler and Watcom FORTRAN 77. [1] [2] [3] Further development is being done on the 32- and 64-bit JWASM project, [4] which more closely matches the syntax of Microsoft's assembler. [5]

Contents

There are experimental assemblers for PowerPC, Alpha AXP, and MIPS. [6]

Technical details

Assembler

Disassembler

There is an associated Watcom disassembler, wdis. The assembler does not have listing facilities; instead the use of wdis for generating listings is recommended. [7] wdis can read OMF, COFF and ELF object files and PE and ELF executables. It supports 16-bit and 32-bit x86 instruction set including MMX, 3DNow!, SSE, SSE2, and SSE3. Support for PowerPC, Alpha AXP, MIPS, and SPARC V8 instruction sets is also built in. [8]

WASM forks

JWasm

JWasm is a fork of Wasm originated by Japheth with following features:

Japheth paused development (or rather, was out of contact) of JWASM in January 2014 with version 2.12pre, but currently continues work on project on GitHub [10] , current (June 2024) version is 2.18. Also, others on the Masm32 forum [11] picked up where Japheth once left off.

HJWasm

HJWasm, adding the prefix H in reference to Masm32 forum member Habran who started off this second WASM development continuation. Version 2.13pre was originally announced in 2016. [12] New features include:

  • SIMD:
  • MMX: MOVQ and added in 2.13, to supplement MOVD.
  • AVX2: VGATHERDPD, VGATHERQPD, VGATHERDPS, VGATHERQPS, VPGATHERDD, VPGATHERQD, VPGATHERDQ, VPGATHERQQ, VEX-encoded general purpose instructions added in 2.13. Remaining instructions added in 2.16.
  • AVX-512: VCMPxxPD, VCMPxxPS, VCMPxxSD, VCMPxxPD, VCMPxxSS, AVX-512F set, EVEX-encoded instructions added in 2.13; VMOVQ added 2.13, to supplement MOVD. Remaining instructions added in 2.16.
  • Random Number Generator: RDRAND, RDSEED added in 2.13.
  • half-precision conversions: F16C(VCVTPH2PS, VCVTPS2PH) added in 2.13.
  • Intel MPX: Added in 2.31.

HASM

HASM is a renamed version of HJWASM, starting in version 2.33. The name was used following a MASM Forum discussion thread that originally proposed a replacement name. The name HASM was proposed by forum member habran in Reply #6, [13] and was finalized at the end of discussion thread at Reply #33. [14] No known features are added in HASM's release cycle.

UASM

The name was actually used in version 2.33 (dated 2017-05-20) at Terraspace ltd's product page, [15] but it was only announced in version 2.34. [16] Changes to HJWASM includes: [17]

  • Record types: fully supports registers and up to 32bit record fields in 2.41.
  • Support for 128bit: Added in 2.42, inline declaration with the type added in 2.43.1 / .2.
  • Support of typedef chain on return types added in 2.46.8.
  • m512 built-in types added in 2.47.

Related Research Articles

x86 Family of instruction set architectures

x86 is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel based on the 8086 microprocessor and its 8-bit-external-bus variant, the 8088. The 8086 was introduced in 1978 as a fully 16-bit extension of 8-bit Intel's 8080 microprocessor, with memory segmentation as a solution for addressing more memory than can be covered by a plain 16-bit address. The term "x86" came into being because the names of several successors to Intel's 8086 processor end in "86", including the 80186, 80286, 80386 and 80486. Colloquially, their names were "186", "286", "386" and "486".

<span class="mw-page-title-main">Single instruction, multiple data</span> Type of parallel processing

Single instruction, multiple data (SIMD) is a type of parallel processing in Flynn's taxonomy. SIMD can be internal and it can be directly accessible through an instruction set architecture (ISA), but it should not be confused with an ISA. SIMD describes computers with multiple processing elements that perform the same operation on multiple data points simultaneously.

<span class="mw-page-title-main">MMX (instruction set)</span> Instruction set designed by Intel

MMX is a single instruction, multiple data (SIMD) instruction set architecture designed by Intel, introduced on January 8, 1997 with its Pentium P5 (microarchitecture) based line of microprocessors, named "Pentium with MMX Technology". It developed out of a similar unit introduced on the Intel i860, and earlier the Intel i750 video pixel processor. MMX is a processor supplementary capability that is supported on IA-32 processors by Intel and other vendors as of 1997. AMD also added MMX instruction set in its K6 processor.

In computing, Streaming SIMD Extensions (SSE) is a single instruction, multiple data (SIMD) instruction set extension to the x86 architecture, designed by Intel and introduced in 1999 in their Pentium III series of central processing units (CPUs) shortly after the appearance of Advanced Micro Devices (AMD's) 3DNow!. SSE contains 70 new instructions, most of which work on single precision floating-point data. SIMD instructions can greatly increase performance when exactly the same operations are to be performed on multiple data objects. Typical applications are digital signal processing and graphics processing.

<span class="mw-page-title-main">Netwide Assembler</span> Assembler for the Intel x86 architecture

The Netwide Assembler (NASM) is an assembler and disassembler for the Intel x86 architecture. It can be used to write 16-bit, 32-bit (IA-32) and 64-bit (x86-64) programs. It is considered one of the most popular assemblers for Linux and x86 chips.

<span class="mw-page-title-main">Athlon 64</span> Series of CPUs by AMD

The Athlon 64 is a ninth-generation, AMD64-architecture microprocessor produced by Advanced Micro Devices (AMD), released on September 23, 2003. It is the third processor to bear the name Athlon, and the immediate successor to the Athlon XP. The Athlon 64 was the second processor to implement the AMD64 architecture and the first 64-bit processor targeted at the average consumer. Variants of the Athlon 64 have been produced for Socket 754, Socket 939, Socket 940, and Socket AM2. It was AMD's primary consumer CPU, and primarily competed with Intel's Pentium 4, especially the Prescott and Cedar Mill core revisions.

3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of floating-point vector operations using vector registers. This improvement enhances the performance of many graphics-intensive applications. The first microprocessor to implement 3DNow! was the AMD K6-2, introduced in 1998. In appropriate applications, this enhancement raised the speed by about 2–4 times.

x86 assembly language is the name for the family of assembly languages which provide some level of backward compatibility with CPUs back to the Intel 8008 microprocessor, which was launched in April 1972. It is used to produce object code for the x86 class of processors.

SSE2 is one of the Intel SIMD processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of XMM (SIMD) registers on x86 instruction set architecture processors. These registers can load up to 128 bits of data and perform instructions, such as vector addition and multiplication, simultaneously.

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The x86 instruction set has several times been extended with SIMD instruction set extensions. These extensions, starting from the MMX instruction set extension introduced with Pentium MMX in 1997, typically define sets of wide registers and instructions that subdivide these registers into fixed-size lanes and perform a computation for each lane in parallel.

References

  1. Randall Hyde. "WASM: The Open Watcom Assembler". Archived from the original on 2012-03-02. Retrieved 2017-09-11.{{cite web}}: CS1 maint: bot: original URL status unknown (link)
  2. Leiterman, James (2005). "MASM vs. NASM vs. TASM vs. WASM". 32/64-bit 80x86 assembly language architecture. Wordware Publishing, Inc. p. 481. ISBN   978-1-59822-002-5 . Retrieved 2010-02-01.
  3. Leiterman p482 on Google Books
  4. JWASM, a 32/64 bit assembler based on WASM with syntax similar to MASM. Archived 10 October 2014
  5. Fog, Agner (2009), Optimizing subroutines in assembly language (PDF) (2009-09-26 ed.), p. 13
  6. 1 2 Open Watcom website: Assembler Archived 2006-07-15 at the Wayback Machine
  7. OpenWatcom: "No listing files are generated [by the assembler]. Producing full listings may be a waste of effort because wdis (the Open Watcom disassembler) does a very good job. However, it could be extremely helpful to produce a dump of the internal symbol table the way MASM does, especially for diagnostic purposes."
  8. Open Watcom website: Disassembler Archived 2006-07-15 at the Wayback Machine
  9. The 1996 "WALK32 consists of the following main components:
    • A full-featured PE (Portable Executable) file linker called W32Link.
    • A main include file, containing Win32 constant, type, and structure definitions.
    • Another include file, containing the application and DLL startup source code.
    • Segment and PE section management macros.
    • Macros related to Unicode support.
    • Several demo applications and DLL’s.
    • A collection of programming utilities for various purposes." walk32.doc in walk32_1.zip
  10. GitHub/Baron-von-Riedesel/JWasm
  11. UASM Assembler Development
  12. HJWasm Releases
  13. A New Name? (thread page 1)
  14. A New Name? (thread page 3)
  15. UASM (2.33)
  16. UASM 2.33 Release
  17. UASM ChangeLog