This article possibly contains original research .(September 2016) |
Original author(s) | Open Watcom Assembler |
---|---|
Operating system | DOS for x86-based PCs, Microsoft Windows, Linux for x86-based PCs, OS/2 for x86-based PCs, FreeBSD for x86-based PCs. |
Available in | English |
Type | x86 assembler |
Website | www |
Open Watcom Assembler or WASM is an x86 assembler produced by Watcom, based on the Watcom Assembler found in Watcom C/C++ compiler and Watcom FORTRAN 77. [1] [2] [3] Further development is being done on the 32- and 64-bit JWASM project, [4] which more closely matches the syntax of Microsoft's assembler. [5]
There are experimental assemblers for PowerPC, Alpha AXP, and MIPS. [6]
There is an associated Watcom disassembler, wdis. The assembler does not have listing facilities; instead the use of wdis for generating listings is recommended. [7] wdis can read OMF, COFF and ELF object files and PE and ELF executables. It supports 16-bit and 32-bit x86 instruction set including MMX, 3DNow!, SSE, SSE2, and SSE3. Support for PowerPC, Alpha AXP, MIPS, and SPARC V8 instruction sets is also built in. [8]
JWasm is a fork of Wasm originated by Japheth with following features:
Japheth ceased development (or rather, was out of contact) of JWASM in January 2014 with version 2.12pre, but others on the Masm32 forum [10] picked up where Japheth left off.
HJWasm, adding the prefix H in reference to Masm32 forum member Habran who started off this second WASM development continuation. Version 2.13pre was originally announced in 2016. [11] New features include:
HASM is a renamed version of HJWASM, starting in version 2.33. The name was used following a MASM Forum discussion thread that originally proposed a replacement name. The name HASM was proposed by forum member habran in Reply #6, [12] and was finalized at the end of discussion thread at Reply #33. [13] No known features are added in HASM's release cycle.
The name was actually used in version 2.33 (dated 2017-05-20) at Terraspace ltd's product page, [14] but it was only announced in version 2.34. [15] Changes to HJWASM includes: [16]
x86 is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel based on the Intel 8086 microprocessor and its 8088 variant. The 8086 was introduced in 1978 as a fully 16-bit extension of Intel's 8-bit 8080 microprocessor, with memory segmentation as a solution for addressing more memory than can be covered by a plain 16-bit address. The term "x86" came into being because the names of several successors to Intel's 8086 processor end in "86", including the 80186, 80286, 80386 and 80486 processors. Colloquially, their names were "186", "286", "386" and "486".
Single instruction, multiple data (SIMD) is a type of parallel processing in Flynn's taxonomy. SIMD can be internal and it can be directly accessible through an instruction set architecture (ISA), but it should not be confused with an ISA. SIMD describes computers with multiple processing elements that perform the same operation on multiple data points simultaneously.
MMX is a single instruction, multiple data (SIMD) instruction set architecture designed by Intel, introduced on January 8, 1997 with its Pentium P5 (microarchitecture) based line of microprocessors, named "Pentium with MMX Technology". It developed out of a similar unit introduced on the Intel i860, and earlier the Intel i750 video pixel processor. MMX is a processor supplementary capability that is supported on IA-32 processors by Intel and other vendors as of 1997.
In computing, Streaming SIMD Extensions (SSE) is a single instruction, multiple data (SIMD) instruction set extension to the x86 architecture, designed by Intel and introduced in 1999 in their Pentium III series of central processing units (CPUs) shortly after the appearance of Advanced Micro Devices (AMD's) 3DNow!. SSE contains 70 new instructions, most of which work on single precision floating-point data. SIMD instructions can greatly increase performance when exactly the same operations are to be performed on multiple data objects. Typical applications are digital signal processing and graphics processing.
The Athlon 64 is a ninth-generation, AMD64-architecture microprocessor produced by Advanced Micro Devices (AMD), released on September 23, 2003. It is the third processor to bear the name Athlon, and the immediate successor to the Athlon XP. The second processor to implement the AMD64 architecture and the first 64-bit processor targeted at the average consumer, it was AMD's primary consumer CPU, and primarily competed with Intel's Pentium 4, especially the Prescott and Cedar Mill core revisions. It is AMD's first K8, eighth-generation processor core for desktop and mobile computers. Despite being natively 64-bit, the AMD64 architecture is backward-compatible with 32-bit x86 instructions. Athlon 64s have been produced for Socket 754, Socket 939, Socket 940, and Socket AM2. The line was succeeded by the dual-core Athlon 64 X2 and Athlon X2 lines.
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of floating-point vector operations using vector registers, which improves the performance of many graphics-intensive applications. The first microprocessor to implement 3DNow! was the AMD K6-2, which was introduced in 1998. When the application was appropriate, this raised the speed by about 2–4 times.
x86 assembly language is the name for the family of assembly languages which provide some level of backward compatibility with CPUs back to the Intel 8008 microprocessor, which was launched in April 1972. It is used to produce object code for the x86 class of processors.
SSE2 is one of the Intel SIMD processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier SSE instruction set, and is intended to fully replace MMX. Intel extended SSE2 to create SSE3 in 2004. SSE2 added 144 new instructions to SSE, which has 70 instructions. Competing chip-maker AMD added support for SSE2 with the introduction of their Opteron and Athlon 64 ranges of AMD64 64-bit CPUs in 2003.
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revision of their Pentium 4 CPU. In April 2005, AMD introduced a subset of SSE3 in revision E of their Athlon 64 CPUs. The earlier SIMD instruction sets on the x86 platform, from oldest to newest, are MMX, 3DNow!, SSE, and SSE2.
The x86 instruction set refers to the set of instructions that x86-compatible microprocessors support. The instructions are usually part of an executable program, often stored as a computer file and executed on the processor.
The Microsoft Macro Assembler (MASM) is an x86 assembler that uses the Intel syntax for MS-DOS and Microsoft Windows. Beginning with MASM 8.0, there are two versions of the assembler: One for 16-bit & 32-bit assembly sources, and another (ML64) for 64-bit sources only.
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