X86 instruction listings

The x86 instruction set refers to the set of instructions that x86-compatible microprocessors support. The instructions are usually part of an executable program, often stored as a computer file and executed on the processor.

The x86 instruction set has been extended several times, introducing wider registers and datatypes as well as new functionality. ^[1]

x86 integer instructions

Main article: x86 assembly language

Below is the full 8086/8088 instruction set of Intel (81 instructions total). ^[2] These instructions are also available in 32-bit mode, they operate instead on 32-bit registers (eax, ebx, etc.) and values instead of their 16-bit (ax, bx, etc.) counterparts. The updated instruction set is grouped according to architecture (i186, i286, i386, i486, i586/i686) and is referred to as (32-bit) x86 and (64-bit) x86-64 (also known as AMD64).

Original 8086/8088 instructions

This is the original instruction set. In the 'Notes' column, r means register, m means memory address and imm means immediate (i.e. a value).

Original 8086/8088 instruction set

In- struc- tion	Meaning	Notes	Opcode
AAA	ASCII adjust AL after addition	used with unpacked binary-coded decimal	0x37
AAD	ASCII adjust AX before division	8086/8088 datasheet documents only base 10 version of the AAD instruction (opcode 0xD50x0A), but any other base will work. Later Intel's documentation has the generic form too. NEC V20 and V30 (and possibly other NEC V-series CPUs) always use base 10, and ignore the argument, causing a number of incompatibilities	0xD5
AAM	ASCII adjust AX after multiplication	Only base 10 version (Operand is 0xA) is documented, see notes for AAD	0xD4
AAS	ASCII adjust AL after subtraction		0x3F
ADC	Add with carry	(1) r += (r/m/imm+CF); (2) m += (r/imm+CF);	0x10...0x15, 0x80...0x81/2, 0x83/2
ADD	Add	(1) r += r/m/imm; (2) m += r/imm;	0x00...0x05, 0x80/0...0x81/0, 0x83/0
AND	Logical AND	(1) r &= r/m/imm; (2) m &= r/imm;	0x20...0x25, 0x80...0x81/4, 0x83/4
CALL	Call procedure	pusheip; eip points to the instruction directly after the call	0x9A, 0xE8, 0xFF/2, 0xFF/3
CBW	Convert byte to word	AX = AL ; sign extended	0x98
CLC	Clear carry flag	CF = 0;	0xF8
CLD	Clear direction flag	DF = 0;	0xFC
CLI	Clear interrupt flag	IF = 0;	0xFA
CMC	Complement carry flag	CF = !CF;	0xF5
CMP	Compare operands	(1) r - r/m/imm; (2) m - r/imm;	0x38...0x3D, 0x80...0x81/7, 0x83/7
CMPSB	Compare bytes in memory. May be used with a REPE or REPNE prefix to test and repeat the instruction CX times.	if(DF==0)*(byte*)SI++-*(byte*)ES:DI++;else*(byte*)SI---*(byte*)ES:DI--;	0xA6
CMPSW	Compare words. May be used with a REPE or REPNE prefix to test and repeat the instruction CX times.	if(DF==0)*(word*)SI++-*(word*)ES:DI++;else*(word*)SI---*(word*)ES:DI--;	0xA7
CWD	Convert word to doubleword		0x99
DAA	Decimal adjust AL after addition	(used with packed binary-coded decimal)	0x27
DAS	Decimal adjust AL after subtraction		0x2F
DEC	Decrement by 1		0x48...0x4F, 0xFE/1, 0xFF/1
DIV	Unsigned divide	(1) AX = DX:AX / r/m; resulting DX = remainder (2) AL = AX / r/m; resulting AH = remainder	0xF7/6, 0xF6/6
ESC	Used with floating-point unit		0xD8..0xDF
HLT	Enter halt state		0xF4
IDIV	Signed divide	(1) AX = DX:AX / r/m; resulting DX = remainder (2) AL = AX / r/m; resulting AH = remainder	0xF7/7, 0xF6/7
IMUL	Signed multiply in One-operand form	(1) DX:AX = AX * r/m; (2) AX = AL * r/m	0xF7/5, 0xF6/5
IN	Input from port	(1) AL = port[imm]; (2) AL = port[DX]; (3) AX = port[imm]; (4) AX = port[DX];	0xE4, 0xE5, 0xEC, 0xED
INC	Increment by 1		0x40...0x47, 0xFE/0, 0xFF/0
INT	Call to interrupt		0xCC, 0xCD
INTO	Call to interrupt if overflow		0xCE
IRET	Return from interrupt		0xCF
Jcc	Jump if condition	(JA, JAE, JB, JBE, JC, JE, JG, JGE, JL, JLE, JNA, JNAE, JNB, JNBE, JNC, JNE, JNG, JNGE, JNL, JNLE, JNO, JNP, JNS, JNZ, JO, JP, JPE, JPO, JS, JZ)	0x70...0x7F
JCXZ	Jump if CX is zero		0xE3
JMP	Jump		0xE9...0xEB, 0xFF/4, 0xFF/5
LAHF	Load FLAGS into AH register		0x9F
LDS	Load DS:r with far pointer		0xC5
LEA	Load Effective Address		0x8D
LES	Load ES:r with far pointer		0xC4
LOCK	Assert BUS LOCK# signal	(for multiprocessing)	0xF0
LODSB	Load string byte. May be used with a REP prefix to repeat the instruction CX times.	if(DF==0)AL=*SI++;elseAL=*SI--;	0xAC
LODSW	Load string word. May be used with a REP prefix to repeat the instruction CX times.	if(DF==0)AX=*SI++;elseAX=*SI--;	0xAD
LOOP/ LOOPx	Loop control	(LOOPE, LOOPNE, LOOPNZ, LOOPZ) if(x&&--CX)gotolbl;	0xE0...0xE2
MOV	Move	(1) r = r/m/imm; (2) m = r/imm (3) r/m = sreg; (4) sreg = r/m;	0xA0...0xA3, 0x8C, 0x8E
MOVSB	Move byte from string to string. May be used with a REP prefix to repeat the instruction CX times.	if(DF==0)*(byte*)ES:DI++=*(byte*)SI++;else*(byte*)ES:DI--=*(byte*)SI--; .	0xA4
MOVSW	Move word from string to string. May be used with a REP prefix to repeat the instruction CX times.	if(DF==0)*(word*)ES:DI++=*(word*)SI++;else*(word*)ES:DI--=*(word*)SI--;	0xA5
MUL	Unsigned multiply	(1) DX:AX = AX * r/m; (2) AX = AL * r/m;	0xF7/4, 0xF6/4
NEG	Two's complement negation	r/m=0–r/m;	0xF6/3...0xF7/3
NOP	No operation	opcode equivalent to XCHG EAX, EAX	0x90
NOT	Negate the operand, logical NOT	r/m^=-1;	0xF6/2...0xF7/2
OR	Logical OR	(1) r ∣= r/m/imm; (2) m ∣= r/imm;	0x08...0x0D, 0x80...0x81/1, 0x83/1
OUT	Output to port	(1) port[imm] = AL; (2) port[DX] = AL; (3) port[imm] = AX; (4) port[DX] = AX;	0xE6, 0xE7, 0xEE, 0xEF
POP	Pop data from stack	r/m/sreg = *SP++;	0x07, 0x17, 0x1F, 0x58...0x5F, 0x8F/0
POPF	Pop FLAGS register from stack	FLAGS = *SP++;	0x9D
PUSH	Push data onto stack	*--SP=r/m/sreg;	0x06, 0x0E, 0x16, 0x1E, 0x50...0x57, 0xFF/6
PUSHF	Push FLAGS onto stack	*--SP=FLAGS;	0x9C
RCL	Rotate left (with carry)		0xC0...0xC1/2 (186+), 0xD0...0xD3/2
RCR	Rotate right (with carry)		0xC0...0xC1/3 (186+), 0xD0...0xD3/3
REPxx	Repeat MOVS/STOS/CMPS/LODS/SCAS	(REP, REPE, REPNE, REPNZ, REPZ)	0xF2, 0xF3
RET	Return from procedure	Not a real instruction. The assembler will translate these to a RETN or a RETF depending on the memory model of the target system.
RETN	Return from near procedure		0xC2, 0xC3
RETF	Return from far procedure		0xCA, 0xCB
ROL	Rotate left		0xC0...0xC1/0 (186+), 0xD0...0xD3/0
ROR	Rotate right		0xC0...0xC1/1 (186+), 0xD0...0xD3/1
SAHF	Store AH into FLAGS		0x9E
SAL	Shift Arithmetically left (signed shift left)	(1) r/m <<= 1; (2) r/m <<= CL;	0xC0...0xC1/4 (186+), 0xD0...0xD3/4
SAR	Shift Arithmetically right (signed shift right)	(1) (signed) r/m >>= 1; (2) (signed) r/m >>= CL;	0xC0...0xC1/7 (186+), 0xD0...0xD3/7
SBB	Subtraction with borrow	(1) r -= (r/m/imm+CF); (2) m -= (r/imm+CF); alternative 1-byte encoding of SBB AL, AL is available via undocumented SALC instruction	0x18...0x1D, 0x80...0x81/3, 0x83/3
SCASB	Compare byte string. May be used with a REPE or REPNE prefix to test and repeat the instruction CX times.	if(DF==0)AL-*ES:DI++;elseAL-*ES:DI--;	0xAE
SCASW	Compare word string. May be used with a REPE or REPNE prefix to test and repeat the instruction CX times.	if(DF==0)AX-*ES:DI++;elseAX-*ES:DI--;	0xAF
SHL	Shift left (unsigned shift left)		0xC0...0xC1/4 (186+), 0xD0...0xD3/4
SHR	Shift right (unsigned shift right)		0xC0...0xC1/5 (186+), 0xD0...0xD3/5
STC	Set carry flag	CF = 1;	0xF9
STD	Set direction flag	DF = 1;	0xFD
STI	Set interrupt flag	IF = 1;	0xFB
STOSB	Store byte in string. May be used with a REP prefix to repeat the instruction CX times.	if(DF==0)*ES:DI++=AL;else*ES:DI--=AL;	0xAA
STOSW	Store word in string. May be used with a REP prefix to repeat the instruction CX times.	if(DF==0)*ES:DI++=AX;else*ES:DI--=AX;	0xAB
SUB	Subtraction	(1) r -= r/m/imm; (2) m -= r/imm;	0x28...0x2D, 0x80...0x81/5, 0x83/5
TEST	Logical compare (AND)	(1) r & r/m/imm; (2) m & r/imm;	0x84, 0x85, 0xA8, 0xA9, 0xF6/0, 0xF7/0
WAIT	Wait until not busy	Waits until BUSY# pin is inactive (used with floating-point unit)	0x9B
XCHG	Exchange data	r:=:r/m; A spinlock typically uses xchg as an atomic operation. (coma bug).	0x86, 0x87, 0x91...0x97
XLAT	Table look-up translation	behaves like MOV AL, [BX+AL]	0xD7
XOR	Exclusive OR	(1) r ^+= r/m/imm; (2) m ^= r/imm;	0x30...0x35, 0x80...0x81/6, 0x83/6

Added in specific processors

Added with 80186/80188

Instruction	Opcode	Meaning	Notes
BOUND	62 /r	Check array index against bounds	raises software interrupt 5 if test fails
ENTER	C8 iw ib	Enter stack frame	Modifies stack for entry to procedure for high level language. Takes two operands: the amount of storage to be allocated on the stack and the nesting level of the procedure.
INSB/INSW	6C	Input from port to string. May be used with a REP prefix to repeat the instruction CX times.	equivalent to: INAL,DXMOVES:[DI],ALINCDI; adjust DI according to operand size and DF
	6D
LEAVE	C9	Leave stack frame	Releases the local stack storage created by the previous ENTER instruction.
OUTSB/OUTSW	6E	Output string to port. May be used with a REP prefix to repeat the instruction CX times.	equivalent to: MOVAL,DS:[SI]OUTDX,ALINCSI; adjust SI according to operand size and DF
	6F
POPA	61	Pop all general purpose registers from stack	equivalent to: POPDIPOPSIPOPBPPOPAX; no POP SP here, all it does is ADD SP, 2 (since AX will be overwritten later)POPBXPOPDXPOPCXPOPAX
PUSHA	60	Push all general purpose registers onto stack	equivalent to: PUSHAXPUSHCXPUSHDXPUSHBXPUSHSP; The value stored is the initial SP valuePUSHBPPUSHSIPUSHDI
PUSH immediate	6A ib	Push an immediate byte/word value onto the stack	example: PUSH12hPUSH1200h
	68 iw
IMUL immediate	6B /r ib	Signed and unsigned multiplication of immediate byte/word value	example: IMULBX,12hIMULDX,1200hIMULCX,DX,12hIMULBX,SI,1200hIMULDI,wordptr[BX+SI],12hIMULSI,wordptr[BP-4],1200h Note that since the lower half is the same for unsigned and signed multiplication, this version of the instruction can be used for unsigned multiplication as well.
	69 /r iw
SHL/SHR/SAL/SAR/ROL/ROR/RCL/RCR immediate	C0	Rotate/shift bits with an immediate value greater than 1	example: ROLAX,3SHRBL,3
	C1

Added with 80286

The new instructions added in 80286 add support for x86 protected mode. Some but not all of the instructions are available in real mode as well.

Instruction	Opcode	Instruction description	Real mode	Ring
LGDT m16&32 [lower-alpha 1]	0F 01 /2	Load GDTR (Global Descriptor Table Register) from memory. [lower-alpha 2]	Yes	0
LIDT m16&32 [lower-alpha 1]	0F 01 /3	Load IDTR (Interrupt Descriptor Table Register) from memory. [lower-alpha 2] The IDTR controls not just the address/size of the IDT (interrupt Descriptor Table) in protected mode, but the IVT (Interrupt Vector Table) in real mode as well.
LMSW r/m16	0F 01 /6	Load MSW (Machine Status Word) from 16-bit register or memory. [lower-alpha 3] [lower-alpha 4]
CLTS	0F 06	Clear task-switched flag in the MSW.
LLDT r/m16	0F 00 /2	Load LDTR (Local Descriptor Table Register) from 16-bit register or memory. [lower-alpha 2]	#UD
LTR r/m16	0F 00 /3	Load TR (Task Register) from 16-bit register or memory. [lower-alpha 2] The TSS (Task State Segment) specified by the 16-bit argument is marked busy, but a task switch is not done.
SGDT m16&32 [lower-alpha 1]	0F 01 /0	Store GDTR to memory.	Yes	Usually 3 [lower-alpha 5]
SIDT m16&32 [lower-alpha 1]	0F 01 /1	Store IDTR to memory.
SMSW r/m16	0F 01 /4	Store MSW to register or 16-bit memory. [lower-alpha 6]
SLDT r/m16	0F 00 /0	Store LDTR to register or 16-bit memory. [lower-alpha 6]	#UD
STR r/m16	0F 00 /1	Store TR to register or 16-bit memory. [lower-alpha 6]
ARPL r/m16,r16	63 /r [lower-alpha 7]	Adjust RPL (Requested Privilege Level) field of selector. The operation performed is: if (dst & 3) < (src & 3) then dst = (dst & 0xFFFC) | (src & 3) eflags.zf = 1 else eflags.zf = 0	#UD [lower-alpha 8]	3
LAR r,r/m16	0F 02 /r	Load access rights byte from the specified segment descriptor. Reads bytes 4-7 of segment descriptor, bitwise-ANDs it with 0x00FxFF00, [lower-alpha 9] then stores the bottom 16/32 bits of the result in destination register. Sets EFLAGS.ZF=1 if the descriptor could be loaded, ZF=0 otherwise.	#UD
LSL r,r/m16	0F 03 /r	Load segment limit from the specified segment descriptor. Sets ZF=1 if the descriptor could be loaded, ZF=0 otherwise.
VERR r/m16	0F 00 /4	Verify a segment for reading. Sets ZF=1 if segment can be read, ZF=0 otherwise.
VERW r/m16	0F 00 /5	Verify a segment for writing. Sets ZF=1 if segment can be written, ZF=0 otherwise. [lower-alpha 10]
LOADALL [lower-alpha 11]	0F 05	Load all CPU registers from a 102-byte data structure starting at physical address 800h, including "hidden" part of segment descriptor registers.	Yes	0
STOREALL [lower-alpha 11]	F1 0F 04	Store all CPU registers to a 102-byte data structure starting at physical address 800h, then shut down CPU.

1. The descriptors used by the LGDT, LIDT, SGDT and SIDT instructions consist of a 2-part data structure. The first part is a 16-bit value, specifying table size in bytes minus 1. The second part is a 32-bit value (64-bit value in 64-bit mode), specifying the linear start address of the table.
   For LGDT and LIDT with a 16-bit operand size, the address is ANDed with 00FFFFFFh. On Intel (but not AMD) CPUs, the SGDT and SIDT instructions with a 16-bit operand size is – as of Intel SDM revision 079, March 2023 – documented to write a descriptor to memory with the last byte being set to 0. However, observed behavior is that bits 31:24 of the descriptor table address are written instead. ^[3]
2. The LGDT, LIDT, LLDT and LTR instructions are serializing on Pentium and later processors.
3. The LMSW instruction is serializing on Intel processors from Pentium onwards, but not on AMD processors.
4. On 80386 and later, the "Machine Status Word" is the same as the CR0 control register – however, the LMSW instruction can only modify the bottom 4 bits of this register and cannot clear bit 0. The inability to clear bit 0 means that LMSW can be used to enter but not leave x86 Protected Mode.
   On 80286, it is not possible to leave Protected Mode at all (neither with LMSW nor with LOADALL ^[4] ) without a CPU reset – on 80386 and later, it is possible to leave Protected Mode, but this requires the use of the 80386-and-later MOV to CR0 instruction.
5. If CR4.UMIP=1 is set, then the SGDT, SIDT, SLDT, SMSW and STR instructions can only run in Ring 0.
   These instructions were unprivileged on all x86 CPUs from 80286 onwards until the introduction of UMIP in 2017. ^[5] This has been a significant security problem for software-based virtualization, since it enables these instructions to be used by a VM guest to detect that it is running inside a VM. ^{[6] [7]}
6. The SMSW, SLDT and STR instructions always use an operand size of 16 bits when used with a memory argument. With a register argument on 80386 or later processors, wider destination operand sizes are available and behave as follows:
   • SMSW: Stores full CR0 in x86-64 long mode, undefined otherwise.
   • SLDT: Zero-extends 16-bit argument on Pentium Pro and later processors, undefined on earlier processors.
   • STR: Zero-extends 16-bit argument.
7. In 64-bit long mode, the ARPL instruction is not available – the 63 /r opcode has been reassigned to the 64-bit-mode-only MOVSXD instruction.
8. The ARPL instruction causes #UD in Real mode and Virtual 8086 Mode – Windows 95 and OS/2 2.x are known to make extensive use of this #UD to use the 63 opcode as a one-byte breakpoint to transition from Virtual 8086 Mode to kernel mode. ^{[8] [9]}
9. Bits 19:16 of this mask are documented as "undefined" on Intel CPUs. ^[10] On AMD CPUs, the mask is documented as 0x00FFFF00.
10. On some Intel CPU/microcode combinations from 2019 onwards, the VERW instruction also flushes microarchitectural data buffers. This enables it to be used as part of workarounds for Microarchitectural Data Sampling security vulnerabilities. ^{[11] [12]}
11. Undocumented, 80286 only. ^{[4] [13] [14]} (A different variant of LOADALL with a different opcode and memory layout exists on 80386.)

Added with 80386

The 80386 added support for 32-bit operation to the x86 instruction set. This was done by widening the general-purpose registers to 32 bits and introducing the concepts of OperandSize and AddressSize – most instruction forms that would previously take 16-bit data arguments were given the ability to take 32-bit arguments by setting their OperandSize to 32 bits, and instructions that could take 16-bit address arguments were given the ability to take 32-bit address arguments by setting their AddressSize to 32 bits. (Instruction forms that work on 8-bit data continue to be 8-bit regardless of OperandSize. Using a data size of 16 bits will cause only the bottom 16 bits of the 32-bit general-purpose registers to be modified – the top 16 bits are left unchanged.)

The default OperandSize and AddressSize to use for each instruction is given by the D bit of the segment descriptor of the current code segment - D=0 makes both 16-bit, D=1 makes both 32-bit. Additionally, they can be overridden on a per-instruction basis with two new instruction prefixes that were introduced in the 80386:

• 66h: OperandSize override. Will change OperandSize from 16-bit to 32-bit if CS.D=0, or from 32-bit to 16-bit if CS.D=1.
• 67h: AddressSize override. Will change AddressSize from 16-bit to 32-bit if CS.D=0, or from 32-bit to 16-bit if CS.D=1.

The 80386 also introduced the two new segment registers FS and GS as well as the x86 control, debug and test registers.

The new instructions introduced in the 80386 can broadly be subdivided into two classes:

• Pre-existing opcodes that needed new mnemonics for their 32-bit OperandSize variants (e.g. CWDE, LODSD)
• New opcodes that introduced new functionality (e.g. SHLD, SETcc)

For instruction forms where the operand size can be inferred from the instruction's arguments (e.g. ADD EAX,EBX can be inferred to have a 32-bit OperandSize due to its use of EAX as an argument), new instruction mnemonics are not needed and not provided.

80386: new instruction mnemonics for 32-bit variants of older opcodes

Type	Instruction mnemonic	Opcode	Description	Mnemonic for older 16-bit variant	Ring
String instructions [lower-alpha 1] [lower-alpha 2]	LODSD	AD	Load string doubleword: EAX := DS:[rSI±±]	LODSW	3
	STOSD	AB	Store string doubleword: ES:[rDI±±] := EAX	STOSW
	MOVSD	A5	Move string doubleword: ES:[rDI±±] := DS:[rSI±±]	MOVSW
	CMPSD	A7	Compare string doubleword: temp1 := DS:[rSI±±] temp2 := ES:[rDI±±] CMP temp1, temp2 /* 32-bit compare and set EFLAGS */	CMPSW
	SCASD	AF	Scan string doubleword: temp1 := ES:[rDI±±] CMP EAX, temp1 /* 32-bit compare and set EFLAGS */	SCASW
	INSD	6D	Input string from doubleword I/O port:ES:[rDI±±] := port[DX] [lower-alpha 3]	INSW	Usually 0 [lower-alpha 4]
	OUTSD	6F	Output string to doubleword I/O port:port[DX] := DS:[rSI±±]	OUTSW
Other	CWDE	98	Sign-extend 16-bit value in AX to 32-bit value in EAX [lower-alpha 5]	CBW	3
	CDQ	99	Sign-extend 32-bit value in EAX to 64-bit value in EDX:EAX. Mainly used to prepare a dividend for the 32-bit IDIV (signed divide) instruction.	CWD
	JECXZ rel8	E3 cb [lower-alpha 6]	Jump if ECX is zero	JCXZ
	PUSHAD	60	Push all 32-bit registers onto stack [lower-alpha 7]	PUSHA
	POPAD	61	Pop all 32-bit general-purpose registers off stack [lower-alpha 8]	POPA
	PUSHFD	9C	Push 32-bit EFLAGS register onto stack	PUSHF	Usually 3 [lower-alpha 9]
	POPFD	9D	Pop 32-bit EFLAGS register off stack	POPF
	IRETD	CF	32-bit interrupt return. Differs from the older 16-bit IRET instruction in that it will pop interrupt return items (EIP,CS,EFLAGS; also ESP [lower-alpha 10] and SS if there is a CPL change; and also ES,DS,FS,GS if returning to virtual 8086 mode) off the stack as 32-bit items instead of 16-bit items. Should be used to return from interrupts when the interrupt handler was entered through a 32-bit IDT interrupt/trap gate. Instruction is serializing.	IRET

1. For the 32-bit string instructions, the ±± notation is used to indicate that the indicated register is post-decremented by 4 if EFLAGS.DF=1 and post-incremented by 4 otherwise.
   For the operands where the DS segment is indicated, the DS segment can be overridden by a segment-override prefix – where the ES segment is indicated, the segment is always ES and cannot be overridden.
   The choice of whether to use the 16-bit SI/DI registers or the 32-bit ESI/EDI registers as the address registers to use is made by AddressSize, overridable with the 67 prefix.
2. The 32-bit string instructions accept repeat-prefixes in the same way as older 8/16-bit string instructions.
   For LODSD, STOSD, MOVSD, INSD and OUTSD, the REP prefix (F3) will repeat the instruction the number of times specified in rCX (CX or ECX, decided by AddressSize), decrementing rCX for each iteration (with rCX=0 resulting in no-op and proceeding to the next instruction).
   For CMPSD and SCASD, the REPE (F3) and REPNE (F2) prefixes are available, which will repeat the instruction but only as long as the flag condition (ZF=1 for REPE, ZF=0 for REPNE) holds true.
3. For the INSB/W/D instructions, the memory access rights for the ES:[rDI] memory address might not be checked until after the port access has been performed – if this check fails (e.g. page fault or other memory exception), then the data item read from the port is lost. As such, it is not recommended to use this instruction to access an I/O port that performs any kind of side effect upon read.
4. I/O port access is only allowed when CPL≤IOPL or the I/O port permission bitmap bits for the port to access are all set to 0.
5. The CWDE instruction differs from the older CWD instruction in that CWD would sign-extend the 16-bit value in AX into a 32-bit value in the DX:AX register pair.
6. For the E3 opcode (JCXZ/JECXZ), the choice of whether the instruction will use CX or ECX for its comparison (and consequently which mnemonic to use) is based on the AddressSize, not OperandSize. (OperandSize instead controls whether the jump destination should be truncated to 16 bits or not).
   This also applies to the loop instructions LOOP,LOOPE,LOOPNE (opcodes E0,E1,E2), however, unlike JCXZ/JECXZ, these instructions have not been given new mnemonics for their ECX-using variants.
7. For PUSHA(D), the value of SP/ESP pushed onto the stack is the value it had just before the PUSHA(D) instruction started executing.
8. For POPA/POPAD, the stack item corresponding to SP/ESP is popped off the stack (performing a memory read), but not placed into SP/ESP.
9. The PUSHFD and POPFD instructions will cause a #GP exception if executed in virtual 8086 mode if IOPL is not 3.
   The PUSHF, POPF, IRET and IRETD instructions will cause a #GP exception if executed in Virtual-8086 mode if IOPL is not 3 and VME is not enabled.
10. If IRETD is used to return from kernel mode to user mode (which will entail a CPL change) and the user-mode stack segment indicated by SS is a 16-bit segment, then the IRETD instruction will only restore the low 16 bits of the stack pointer (ESP/RSP), with the remaining bits keeping whatever value they had in kernel code before the IRETD. This has necessitated complex workarounds on both Linux ("ESPFIX") ^[15] and Windows. ^[16] This issue also affects the later 64-bit IRETQ instruction.

80386: new opcodes introduced

Instruction mnemonics	Opcode	Description	Ring
BT r/m, r	0F A3 /r	Bit Test. [lower-alpha 1] Second operand specifies which bit of the first operand to test. The bit to test is copied to EFLAGS.CF.	3
BT r/m, imm8	0F BA /4 ib
BTS r/m, r	0F AB /r	Bit Test-and-set. [lower-alpha 1] [lower-alpha 2] Second operand specifies which bit of the first operand to test and set.
BTS r/m, imm8	0F BA /5 ib
BTR r/m, r	0F B3 /r	Bit Test and Reset. [lower-alpha 1] [lower-alpha 2] Second operand specifies which bit of the first operand to test and clear.
BTR r/m, imm8	0F BA /6 ib
BTC r/m, r	0F BB /r	Bit Test and Complement. [lower-alpha 1] [lower-alpha 2] Second operand specifies which bit of the first operand to test and toggle.
BTC r/m, imm8	0F BA /7 ib
BSF r, r/m	NFx 0F BC /r [lower-alpha 3]	Bit scan forward. Returns bit index of lowest set bit in input. [lower-alpha 4]	3
BSR r, r/m	NFx 0F BD /r [lower-alpha 5]	Bit scan reverse. Returns bit index of highest set bit in input. [lower-alpha 4]
SHLD r/m, r, imm8	0F A4 /r ib	Shift Left Double. The operation of SHLD arg1,arg2,shamt is: arg1 := (arg1<<shamt) | (arg2>>(operand_size - shamt)) [lower-alpha 6]
SHLD r/m, r, CL	0F A5 /r
SHRD r/m, r, imm8	0F AC /r ib	Shift Right Double. The operation of SHRD arg1,arg2,shamt is: arg1 := (arg1>>shamt) | (arg2<<(operand_size - shamt)) [lower-alpha 6]
SHRD r/m, r, CL	0F AD /r
MOVZX reg, r/m8	0F B6 /r	Move from 8/16-bit source to 16/32-bit register with zero-extension.	3
MOVZX reg, r/m16	0F B7 /r
MOVSX reg, r/m8	0F BE /r	Move from 8/16-bit source to 16/32/64-bit register with sign-extension.
MOVSX reg, r/m16	0F BF /r
SETcc r/m8	0F 9x /0 [lower-alpha 7] [lower-alpha 8]	Set byte to 1 if condition is satisfied, 0 otherwise.
Jcc rel16 Jcc rel32	0F 8x cw 0F 8x cd [lower-alpha 7]	Conditional jump near. Differs from older variants of conditional jumps in that they accept a 16/32-bit offset rather than just an 8-bit offset.
IMUL r, r/m	0F AF /r	Two-operand non-widening integer multiply.
FS:	64	Segment-override prefixes for FS and GS segment registers.	3
GS:	65
PUSH FS	0F A0	Push/pop FS and GS segment registers.
POP FS	0F A1
PUSH GS	0F A8
POP GS	0F A9
LFS r16, m16&16 LFS r32, m32&16	0F B4 /r	Load far pointer from memory. Offset part is stored in destination register argument, segment part in FS/GS/SS segment register as indicated by the instruction mnemonic. [lower-alpha 9]
LGS r16, m16&16 LGS r32, m32&16	0F B5 /r
LSS r16, m16&16 LSS r32, m32&16	0F B2 /r
MOV reg,CRx	0F 20 /r [lower-alpha 10]	Move from control register to general register. [lower-alpha 11]	0
MOV CRx,reg	0F 22 /r [lower-alpha 10]	Move from general register to control register. [lower-alpha 11] Moves to the CR3 control register are serializing and will flush the TLB. [lower-alpha 12] On Pentium and later processors, moves to the CR0 and CR4 control registers are also serializing. [lower-alpha 13]
MOV reg,DRx	0F 21 /r [lower-alpha 10]	Move from x86 debug register to general register. [lower-alpha 11]
MOV DRx,reg	0F 23 /r [lower-alpha 10]	Move from general register to x86 debug register. [lower-alpha 11] On Pentium and later processors, moves to the DR0-DR7 debug registers are serializing.
MOV reg,TRx	0F 24 /r [lower-alpha 10]	Move from x86 test register to general register. [lower-alpha 14]
MOV TRx,reg	0F 26 /r [lower-alpha 10]	Move from general register to x86 test register. [lower-alpha 14]
ICEBP,  INT01,  INT1 [lower-alpha 15]	F1	In-circuit emulation breakpoint. Performs software interrupt #1 if executed when not using in-circuit emulation. [lower-alpha 16]	3
UMOV r/m, r8	0F 10 /r	User Move – perform data moves that can access user memory while in In-circuit emulation HALT mode. Performs same operation as MOV if executed when not doing in-circuit emulation. [lower-alpha 17]
UMOV r/m, r16/32	0F 11 /r
UMOV r8, r/m	0F 12 /r
UMOV r16/32, r/m	0F 13 /r
XBTS reg,r/m	0F A6 /r	Bitfield extract (early 386 only). [lower-alpha 18] [lower-alpha 19]
IBTS r/m,reg	0F A7 /r	Bitfield insert (early 386 only). [lower-alpha 18] [lower-alpha 19]
LOADALLD,  LOADALL386 [lower-alpha 20]	0F 07	Load all CPU registers from a 296-byte data structure starting at ES:EDI, including "hidden" part of segment descriptor registers.	0

1. For the BT, BTS, BTR and BTC instructions:
   • If the first argument to the instruction is a register operand and/or the second argument is an immediate, then the bit-index in the second argument is taken modulo operand size (16/32/64, in effect using only the bottom 4, 5 or 6 bits of the index.)
   • If the first argument is a memory operand and the second argument is a register operand, then the bit-index in the second argument is used in full – it is interpreted as a signed bit-index that is used to offset the memory address to use for the bit test.
2. The BTS, BTC and BTR instructions accept the LOCK (F0) prefix when used with a memory argument – this results in the instruction executing atomically.
3. If the F3 prefix is used with the 0F BC /r opcode, then the instruction will execute as TZCNT on systems that support the BMI1 extension. TZCNT differs from BSF in that TZCNT but not BSR is defined to return operand size if the source operand is zero – for other source operand values, they produce the same result (except for flags).
4. BSF and BSR set the EFLAGS.ZF flag to 1 if the source argument was all-0s and 0 otherwise.
   If the source argument was all-0s, then the destination register is documented as being left unchanged on AMD processors, but set to an undefined value on Intel processors.
5. If the F3 prefix is used with the 0F BD /r opcode, then the instruction will execute as LZCNT on systems that support the ABM or LZCNT extensions. LZCNT produces a different result from BSR for most input values.
6. For SHLD and SHRD, the shift-amount is masked – the bottom 5 bits are used for 16/32-bit operand size and 6 bits for 64-bit operand size.
   SHLD and SHRD with 16-bit arguments and a shift-amount greater than 16 produce undefined results. (Actual results differ between different Intel CPUs, with at least three different behaviors known. ^[17] )
7. The condition codes supported for the SETcc and Jcc near instructions (opcodes 0F 9x /0 and 0F 8x respectively, with the x nibble specifying the condition) are:

   x	cc	Condition (EFLAGS)
   0	O	OF=1: "Overflow"
   1	NO	OF=0: "Not Overflow"
   2	C,B,NAE	CF=1: "Carry", "Below", "Not Above or Equal"
   3	NC,NB,AE	CF=0: "Not Carry", "Not Below", "Above or Equal"
   4	Z,E	ZF=1: "Zero", "Equal"
   5	NZ,NE	ZF=0: "Not Zero", "Not Equal"
   6	NA,BE	(CF=1 or ZF=1): "Not Above", "Below or Equal"
   7	A,NBE	(CF=0 and ZF=0): "Above", "Not Below or Equal"
   8	S	SF=1: "Sign"
   9	NS	SF=0: "Not Sign"
   A	P,PE	PF=1: "Parity", "Parity Even"
   B	NP,PO	PF=0: "Not Parity", "Parity Odd"
   C	L,NGE	SF≠OF: "Less", "Not Greater Or Equal"
   D	NL,GE	SF=OF: "Not Less", "Greater Or Equal"
   E	LE,NG	(ZF=1 or SF≠OF): "Less or Equal", "Not Greater"
   F	NLE,G	(ZF=0 and SF=OF): "Not Less or Equal", "Greater"

8. For SETcc, while the opcode is commonly specified as /0 – implying that bits 5:3 of the instruction's ModR/M byte should be 000 – modern x86 processors (Pentium and later) ignore bits 5:3 and will execute the instruction as SETcc regardless of the contents of these bits.
9. For LFS, LGS and LSS, the size of the offset part of the far pointer is given by operand size – the size of the segment part is always 16 bits. In 64-bit mode, using the REX.W prefix with these instructions will cause them to load a far pointer with a 64-bit offset on Intel but not AMD processors.
10. For MOV to/from the CRx, DRx and TRx registers, the reg part of the ModR/M byte is used to indicate CRx/DRx/TRx register and r/m part the general-register. Uniquely for the MOV CRx/DRx/TRx opcodes, the top two bits of the ModR/M byte is ignored – these opcodes are decoded and executed as if the top two bits of the ModR/M byte are 11b.
11. For moves to/from the CRx and DRx registers, the operand size is always 64 bits in 64-bit mode and 32 bits otherwise.
12. On processors that support global pages (Pentium and later), global page table entries will not be flushed by a MOV to CR3 − instead, these entries can be flushed by toggling the CR4.PGE bit.
    On processors that support PCIDs, writing to CR3 while PCIDs are enabled will only flush TLB entries belonging to the PCID specified in bits 11:0 of the value written to CR3 (this flush can be suppressed by setting bit 63 of the written value to 1). Flushing pages belonging to other PCIDs can instead be done by toggling the CR4.PGE bit, clearing the CR4.PCIDE bit, or using the INVPCID instruction.
13. On processors prior to Pentium, moves to CR0 would not serialize the instruction stream – in part for this reason, it is usually required to perform a far jump ^[18] immediately after a MOV to CR0 if such a MOV is used to enable/disable protected mode and/or memory paging.
    MOV to CR2 is architecturally listed as serializing, but has been reported to be non-serializing on at least some Intel Core-i7 processors. ^[19]
    MOV to CR8 (introduced with x86-64) is serializing on AMD but not Intel processors.
14. The MOV TRx instructions were discontinued from Pentium onwards.
15. The INT1/ICEBP (F1) instruction is present on all known Intel x86 processors from the 80386 onwards, ^[20] but only fully documented for Intel processors from the May 2018 release of the Intel SDM (rev 067) onwards. ^[21] Before this release, mention of the instruction in Intel material was sporadic, e.g. AP-526 rev 001. ^[22]
    For AMD processors, the instruction has been documented since 2002. ^[23]
16. The operation of the F1(ICEBP) opcode differs from the operation of the regular software interrupt opcode CD 01 in several ways:
    In protected mode, CD 01 will check CPL against the interrupt descriptor's DPL field as an access-rights check, while F1 will not.
    • In virtual-8086 mode, CD 01 will also check CPL against IOPL as an access-rights check, while F1 will not.
    • In virtual-8086 mode with VME enabled, interrupt redirection is supported for CD 01 but not F1.
17. The UMOV instruction is present on 386 and 486 processors only. ^[20]
18. The XBTS and IBTS instructions were discontinued with the B1 stepping of 80386.
    They have been used by software mainly for detection of the buggy ^[24] B0 stepping of the 80386. Microsoft Windows (v2.01 and later) will attempt to run the XBTS instruction as part of its CPU detection if CPUID is not present, and will refuse to boot if XBTS is found to be working. ^[25]
19. For XBTS and IBTS, the r/m argument represents the data to extract/insert a bitfield from/to, the reg argument the bitfield to be inserted/extracted, AX/EAX a bit-offset and CL a bitfield length. ^[26]
20. Undocumented, 80386 only. ^[27]

Added with 80486

Instruction	Opcode	Description	Ring
BSWAP r32	0F C8+r	Byte Order Swap. Usually used to convert between big-endian and little-endian data representations. For 32-bit registers, the operation performed is: r = (r << 24) | ((r << 8) & 0x00FF0000) | ((r >> 8) & 0x0000FF00) | (r >> 24); Using BSWAP with a 16-bit register argument produces an undefined result. [lower-alpha 1]	3
CMPXCHG r/m8,r8	0F B0 /r [lower-alpha 2]	Compare and Exchange. If accumulator (AL/AX/EAX/RAX) compares equal to first operand, [lower-alpha 3] then EFLAGS.ZF is set to 1 and the first operand is overwritten with the second operand. Otherwise, EFLAGS.ZF is set to 0, and first operand is copied into the accumulator. Instruction atomic only if used with LOCK prefix.
CMPXCHG r/m,r16 CMPXCHG r/m,r32	0F B1 /r [lower-alpha 2]
XADD r/m,r8	0F C0 /r	eXchange and ADD. Exchanges the first operand with the second operand, then stores the sum of the two values into the destination operand. Instruction atomic only if used with LOCK prefix.
XADD r/m,r16 XADD r/m,r32	0F C1 /r
INVLPG m8	0F 01 /7	Invalidate the TLB entries that would be used for the 1-byte memory operand. [lower-alpha 4] Instruction is serializing.	0
INVD	0F 08	Invalidate Internal Caches. [lower-alpha 5] Modified data in the cache are not written back to memory, potentially causing data loss. [lower-alpha 6]
WBINVD	NFx 0F 09 [lower-alpha 7]	Write Back and Invalidate Cache. [lower-alpha 5] Writes back all modified cache lines in the processor's internal cache to main memory and invalidates the internal caches.

1. Using BSWAP with 16-bit registers is not disallowed per se (it will execute without producing an #UD or other exceptions) but is documented to produce undefined results – it is reported to produce various different results on 486, ^[28] 586, and Bochs/QEMU. ^[29]
2. On Intel 80486 stepping A, ^[30] the CMPXCHG instruction uses a different encoding - 0F A6 /r for 8-bit variant, 0F A7 /r for 16/32-bit variant. The 0F B0/B1 encodings are used on 80486 stepping B and later. ^{[31] [32]}
3. The CMPXCHG instruction sets EFLAGS in the same way as a CMP instruction that uses the accumulator (AL/AX/EAX/RAX) as its first argument would do.
4. INVLPG executes as no-operation if the m8 argument is invalid (e.g. unmapped page or non-canonical address).
   INVLPG can be used to invalidate TLB entries for individual global pages.
5. The INVD and WBINVD instructions will invalidate all cache lines in the CPU's L1 caches. It is implementation-defined whether they will invalidate L2/L3 caches as well.
   These instructions are serializing – on some processors, they may block interrupts until completion as well.
6. Under Intel VT-x virtualization, the INVD instruction will cause a mandatory #VMEXIT. Also, on processors that support Intel SGX, if the PRM (Processor Reserved Memory) has been set up by using the PRMRRs (PRM range registers), then the INVD instruction is not permitted and will cause a #GP(0) exception. ^[33]
7. If the F3 prefix is used with the 0F 09 opcode, then the instruction will execute as WBNOINVD on processors that support the WBNOINVD extension – this will not invalidate the cache.

Added in P5/P6-class processors

Integer/system instructions that were not present in the basic 80486 instruction set, but were added in various x86 processors prior to the introduction of SSE. (Discontinued instructions are not included.)

Instruction	Opcode	Description	Ring	Added in
RDMSR	0F 32	Read Model-specific register. The MSR to read is specified in ECX. The value of the MSR is then returned as a 64-bit value in EDX:EAX.	0	IBM 386SLC, [34] Intel Pentium, AMD K5, Cyrix 6x86MX,MediaGXm, IDT WinChip C6, Transmeta Crusoe
WRMSR	0F 30	Write Model-specific register. The MSR to write is specified in ECX, and the data to write is given in EDX:EAX. [lower-alpha 1] Instruction is, with some exceptions, serializing. [lower-alpha 2]
RSM [38]	0F AA	Resume from System Management Mode. Instruction is serializing.	-2 (SMM)	Intel 386SL, [39] [40] 486SL, [lower-alpha 3] Intel Pentium, AMD 5x86, Cyrix 486SLC/e, [41] IDT WinChip C6, Transmeta Crusoe, Rise mP6
CPUID	0F A2	CPU Identification and feature information. Takes as input a CPUID leaf index in EAX and, depending on leaf, a sub-index in ECX. Result is returned in EAX,EBX,ECX,EDX. [lower-alpha 4] Instruction is serializing, and causes a mandatory #VMEXIT under virtualization. Support for CPUID can be checked by toggling bit 21 of EFLAGS (EFLAGS.ID) – if this bit can be toggled, CPUID is present.	Usually 3 [lower-alpha 5]	Intel Pentium, [lower-alpha 6] AMD 5x86, [lower-alpha 6] Cyrix 5x86, [lower-alpha 7] IDT WinChip C6, Transmeta Crusoe, Rise mP6, NexGen Nx586, [lower-alpha 8] UMC Green CPU
CMPXCHG8B m64	0F C7 /1	Compare and Exchange 8 bytes. Compares EDX:EAX with m64. If equal, set ZF [lower-alpha 9] and store ECX:EBX into m64. Else, clear ZF and load m64 into EDX:EAX. Instruction atomic only if used with LOCK prefix. [lower-alpha 10]	3	Intel Pentium, AMD K5, Cyrix 6x86L,MediaGXm, IDT WinChip C6, [lower-alpha 11] Transmeta Crusoe, [lower-alpha 11] Rise mP6 [lower-alpha 11]
RDTSC	0F 31	Read 64-bit Time Stamp Counter (TSC) into EDX:EAX. [lower-alpha 12] In early processors, the TSC was a cycle counter, incrementing by 1 for each clock cycle (which could cause its rate to vary on processors that could change clock speed at runtime) – in later processors, it increments at a fixed rate that doesn't necessarily match the CPU clock speed. [lower-alpha 13]	Usually 3 [lower-alpha 14]	Intel Pentium, AMD K5, Cyrix 6x86MX,MediaGXm, IDT WinChip C6, Transmeta Crusoe, Rise mP6
RDPMC	0F 33	Read Performance Monitoring Counter. The counter to read is specified by ECX and its value is returned in EDX:EAX. [lower-alpha 12]	Usually 3 [lower-alpha 15]	Intel Pentium MMX, Intel Pentium Pro, AMD K7, Cyrix 6x86MX, IDT WinChip C6, VIA Nano [lower-alpha 16]
CMOVcc reg,r/m	0F 4x /r [lower-alpha 17]	Conditional move to register. The source operand may be either register or memory. [lower-alpha 18]	3	Intel Pentium Pro, AMD K7, Cyrix 6x86MX,MediaGXm, Transmeta Crusoe, VIA C3 "Nehemiah" [lower-alpha 19]
NOP r/m, NOPL r/m	NFx 0F 1F /0 [lower-alpha 20]	Official long NOP. Other than AMD K7/K8, broadly unsupported in non-Intel processors released before 2005. [lower-alpha 21] [56]	3	Intel Pentium Pro, [lower-alpha 22] AMD K7, x86-64, [lower-alpha 23] VIA C7 [60]
UD2, [lower-alpha 24] UD2A [lower-alpha 25]	0F 0B	Undefined Instructions – will generate an invalid opcode (#UD) exception in all operating modes. [lower-alpha 26] These instructions are provided for software testing to explicitly generate invalid opcodes. The opcodes for these instructions are reserved for this purpose.	(3)	(80186), [lower-alpha 27] Intel Pentium [65]
UD1 reg,r/m, [lower-alpha 28] UD2B reg,r/m [lower-alpha 25]	0F B9 /r [lower-alpha 29]
OIO, UD0, UD0 reg,r/m [lower-alpha 30]	0F FF, 0F FF /r [lower-alpha 29]			(80186), [lower-alpha 27] Cyrix 6x86, [70] AMD K5 [72]
SYSCALL	0F 05	Fast System call.	3	AMD K6, [lower-alpha 31] x86-64 [lower-alpha 32] [lower-alpha 33]
SYSRET	0F 07 [lower-alpha 34]	Fast Return from System Call. Designed to be used together with SYSCALL.	0 [lower-alpha 35]
SYSENTER	0F 34	Fast System call.	3 [lower-alpha 35]	Intel Pentium II, [lower-alpha 36] AMD K7, [77] [lower-alpha 37] Transmeta Crusoe, [lower-alpha 38] NatSemi Geode GX2, VIA C3 "Nehemiah" [lower-alpha 39]
SYSEXIT	0F 35 [lower-alpha 34]	Fast Return from System Call. Designed to be used together with SYSENTER.	0 [lower-alpha 35]

1. On Intel and AMD CPUs, the WRMSR instruction is also used to update the CPU microcode. This is done by writing the virtual address of the new microcode to upload to MSR 79h on Intel CPUs and MSR C001_0020h ^[35] on AMD CPUs.
2. Writes to the following MSRs are not serializing: ^{[36] [37]}

   Number	Name
   48h	SPEC_CTRL
   49h	PRED_CMD
   10Bh	FLUSH_CMD
   122h	TSX_CTRL
   6E0h	TSC_DEADLINE
   6E1h	PKRS
   774h	HWP_REQUEST (non-serializing only if the FAST_IA32_­HWP_REQUEST bit it set)
   802h to 83Fh	(x2APIC MSRs)
   1B01h	UARCH_MISC_CTL
   C001_011Bh	Doorbell Register (AMD)

3. System Management Mode and the RSM instruction were made available on non-SL variants of the Intel 486 only after the initial release of the Intel Pentium in 1993.
4. On some older 32-bit processors, executing CPUID with a leaf index (EAX) greater than 0 may leave EBX and ECX unmodified, keeping their old values. For this reason, it is recommended to zero out EBX and ECX before executing CPUID.
   Processors noted to exhibit this behavior include Cyrix MII ^[42] and IDT WinChip 2. ^[43]
   
   In 64-bit mode, CPUID will set the top 32 bits of RAX, RBX, RCX and RDX to zero.
5. On some Intel processors starting from Ivy Bridge, there exists MSRs that can be used to restrict CPUID to ring 0. Such MSRs are documented for at least Ivy Bridge ^[44] and Denverton. ^[45]
   The ability to restrict CPUID to ring 0 also exists on AMD processors supporting the "CpuidUserDis" feature (Zen 4 "Raphael" and later). ^[46]
6. CPUID is also available on some Intel and AMD 486 processor variants that were released after the initial release of the Intel Pentium.
7. On the Cyrix 5x86 and 6x86 CPUs, CPUID is not enabled by default and must be enabled through a Cyrix configuration register.
8. On NexGen CPUs, CPUID is only supported with some system BIOSes. On some NexGen CPUs that do support CPUID, EFLAGS.ID is not supported but EFLAGS.AC is, complicating CPU detection. ^[47]
9. Unlike the older CMPXCHG instruction, the CMPXCHG8B instruction does not modify any EFLAGS bits other than ZF.
10. LOCK CMPXCHG8B with a register operand (which is an invalid encoding) can cause hangs on some Intel Pentium CPUs (Pentium F00F bug).
11. On IDT WinChip, Transmeta Crusoe and Rise mP6 processors, the CMPXCHG8B instruction is always supported, however its CPUID bit may be missing. This is a workaround for a bug in Windows NT. ^[48]
12. The RDTSC and RDPMC instructions are not ordered with respect to other instructions, and may sample their respective counters before earlier instructions are executed or after later instructions have executed. Invocations of RDPMC (but not RDTSC) may be reordered relative to each other even for reads of the same counter.
    In order to impose ordering with respect to other instructions, LFENCE or serializing instructions (e.g. CPUID) are needed. ^[49]
13. Fixed-rate TSC was introduced in two stages:

    Constant TSC

    TSC running at a fixed rate as long as the processor core is not in a deep-sleep (C2 or deeper) mode, but not synchronized between CPU cores. Introduced in Intel Prescott, Yonah and Bonnell. Also present in all Transmeta and VIA Nano ^[50] CPUs. Does not have a CPUID bit.

    Invariant TSC

    TSC running at a fixed rate, and remaining synchronized between CPU cores in all P-,C- and T-states (but not necessarily S-states).
    Present in AMD K10 and later; Intel Nehalem/Saltwell ^[51] and later; Zhaoxin WuDaoKou ^[52] and later. Indicated with a CPUID bit (leaf 8000_0007:EDX[8]).

14. RDTSC can be run outside Ring 0 only if CR4.TSD=0.
    On Intel Pentium and AMD K5, RDTSC cannot be run in Virtual-8086 mode. ^[53] Later processors removed this restriction.
15. RDPMC can be run outside Ring 0 only if CR4.PCE=1.
16. The RDPMC instruction is not present in VIA processors prior to the Nano.
17. The condition codes supported for CMOVcc instruction (opcode 0F 4x /r, with the x nibble specifying the condition) are:

    x	cc	Condition (EFLAGS)
    0	O	OF=1: "Overflow"
    1	NO	OF=0: "Not Overflow"
    2	C,B,NAE	CF=1: "Carry", "Below", "Not Above or Equal"
    3	NC,NB,AE	CF=0: "Not Carry", "Not Below", "Above or Equal"
    4	Z,E	ZF=1: "Zero", "Equal"
    5	NZ,NE	ZF=0: "Not Zero", "Not Equal"
    6	NA,BE	(CF=1 or ZF=1): "Not Above", "Below or Equal"
    7	A,NBE	(CF=0 and ZF=0): "Above", "Not Below or Equal"
    8	S	SF=1: "Sign"
    9	NS	SF=0: "Not Sign"
    A	P,PE	PF=1: "Parity", "Parity Even"
    B	NP,PO	PF=0: "Not Parity", "Parity Odd"
    C	L,NGE	SF≠OF: "Less", "Not Greater Or Equal"
    D	NL,GE	SF=OF: "Not Less", "Greater Or Equal"
    E	LE,NG	(ZF=1 or SF≠OF): "Less or Equal", "Not Greater"
    F	NLE,G	(ZF=0 and SF=OF): "Not Less or Equal", "Greater"

18. In 64-bit mode, CMOVcc with a 32-bit operand size will clear the upper 32 bits of the destination register even if the condition is false.
    For CMOVcc with a memory source operand, the CPU will always read the operand from memory – potentially causing memory exceptions and cache line-fills – even if the condition for the move is not satisfied. (The Intel APX extension defines a set of new EVEX-encoded variants of CMOVcc that will suppress memory exceptions if the condition is false.)
19. On pre-Nehemiah VIA C3 variants ("Samuel"/"Ezra"), the reg,reg but not reg,[mem] forms of the CMOVcc instructions have been reported to be present as undocumented instructions. ^[54]
20. Intel's recommended byte encodings for multi-byte NOPs of lengths 2 to 9 bytes in 32/64-bit mode are (in hex): ^[55]

    Length	Byte Sequence
    2	66 90
    3	0F 1F 00
    4	0F 1F 40 00
    5	0F 1F 44 00 00
    6	66 0F 1F 44 00 00
    7	0F 1F 80 00 00 00 00
    8	0F 1F 84 00 00 00 00 00
    9	66 0F 1F 84 00 00 00 00 00

    For cases where there is a need to use more than 9 bytes of NOP padding, it is recommended to use multiple NOPs.
21. Unlike other instructions added in Pentium Pro, long NOP does not have a CPUID feature bit.
22. 0F 1F /0 as long-NOP was introduced in the Pentium Pro, but remained undocumented until 2006. ^[57] The whole 0F 18..1F opcode range was NOP in Pentium Pro. However, except for 0F 1F /0, Intel does not guarantee that these opcodes will remain NOP in future processors, and have indeed assigned some of these opcodes to other instructions in at least some processors. ^[58]
23. Documented for AMD x86-64 since 2002. ^[59]
24. While the 0F 0B opcode was officially reserved as an invalid opcode from Pentium onwards, it only got assigned the mnemonic UD2 from Pentium Pro onwards. ^[61]
25. GNU Binutils have used the UD2A and UD2B mnemonics for the 0F 0B and 0F B9 opcodes since version 2.7. ^[62]
    Neither UD2A nor UD2B originally took any arguments - UD2B was later modified to accept a ModR/M byte, in Binutils version 2.30. ^[63]
26. The UD2 (0F 0B) instruction will additionally stop subsequent bytes from being decoded as instructions, even speculatively. For this reason, if an indirect branch instruction is followed by something that is not code, it is recommended to place an UD2 instruction after the indirect branch. ^[64]
27. The UD0/1/2 opcodes - 0F 0B, 0F B9 and 0F FF - will cause an #UD exception on all x86 processors from the 80186 onwards (except NEC V-series processors), but did not get explicitly reserved for this purpose until P5-class processors.
28. While the 0F B9 opcode was officially reserved as an invalid opcode from Pentium onwards, it only got assigned its mnemonic UD1 much later – AMD APM started listing UD1 in its opcode maps from rev 3.17 onwards, ^[66] while Intel SDM started listing it from rev 061 onwards. ^[67]
29. For both the 0F B9 and 0F FF opcodes, different x86 implementations are known to differ regarding whether the opcodes accept a ModR/M byte. ^{[68] [69]}
30. For the 0F FF opcode, the OIO mnemonic was introduced by Cyrix, ^[70] while the UD0 menmonic (without arguments) was introduced by AMD and Intel at the same time as the UD1 mnemonic for 0F B9. ^{[66] [67]} Later Intel (but not AMD) documentation modified its description of UD0 to add a ModR/M byte and take two arguments. ^[71]
31. On K6, the SYSCALL/SYSRET instructions were available on Model 7 (250nm "Little Foot") and later, not on the earlier Model 6. ^[73]
32. SYSCALL and SYSRET were made an integral part of x86-64 – as a result, the instructions are available in 64-bit mode on all x86-64 processors from AMD, Intel, VIA and Zhaoxin.
    Outside 64-bit mode, the instructions are available on AMD processors only.
33. The exact semantics of SYSRET differs slightly between AMD and Intel processors: non-canonical return addresses cause a #GP exception to be thrown in Ring 3 on AMD CPUs but Ring 0 on Intel CPUs. This has been known to cause security issues. ^[74]
34. For the SYSRET and SYSEXIT instructions under x86-64, it is necessary to add the REX.W prefix for variants that will return to 64-bit user-mode code.
    Encodings of these instructions without the REX.W prefix are used to return to 32-bit user-mode code. (Neither of these instructions can be used to return to 16-bit user-mode code.)
35. The SYSRET, SYSENTER and SYSEXIT instructions are unavailable in Real mode. (SYSENTER is, however, available in Virtual 8086 mode.)
36. The CPUID flags that indicate support for SYSENTER/SYSEXIT are set on the Pentium Pro, even though the processor does not officially support these instructions. ^[75]
    Third party testing indicates that the opcodes are present on the Pentium Pro but too buggy to be usable. ^[76]
37. On AMD CPUs, the SYSENTER and SYSEXIT instructions are not available in x86-64 long mode (#UD).
38. On Transmeta CPUs, the SYSENTER and SYSEXIT instructions are only available with version 4.2 or higher of the Transmeta Code Morphing software. ^[78]
39. On Nehemiah, SYSENTER and SYSEXIT are available only on stepping 8 and later. ^[79]

Added as instruction set extensions

Added with x86-64

These instructions can only be encoded in 64 bit mode. They fall in four groups:

• original instructions that reuse existing opcodes for a different purpose (MOVSXD replacing ARPL)
• original instructions with new opcodes (SWAPGS)
• existing instructions extended to a 64 bit address size (JRCXZ)
• existing instructions extended to a 64 bit operand size (remaining instructions)

Most instructions with a 64 bit operand size encode this using a REX.W prefix; in the absence of the REX.W prefix, the corresponding instruction with 32 bit operand size is encoded. This mechanism also applies to most other instructions with 32 bit operand size. These are not listed here as they do not gain a new mnemonic in Intel syntax when used with a 64 bit operand size.

Instruction	Encoding	Meaning	Ring
CDQE	REX.W 98	Sign extend EAX into RAX	3
CQO	REX.W 99	Sign extend RAX into RDX:RAX
CMPSQ	REX.W A7	CoMPare String Quadword
CMPXCHG16B m128 [lower-alpha 1] [lower-alpha 2]	REX.W 0F C7 /1	CoMPare and eXCHanGe 16 Bytes. Atomic only if used with LOCK prefix.
IRETQ	REX.W CF	64-bit Return from Interrupt
JRCXZ rel8	E3 cb	Jump if RCX is zero
LODSQ	REX.W AD	LoaD String Quadword
MOVSXD r64,r/m32	REX.W 63 /r [lower-alpha 3]	MOV with Sign Extend 32-bit to 64-bit
MOVSQ	REX.W A5	Move String Quadword
POPFQ	9D	POP RFLAGS Register
PUSHFQ	9C	PUSH RFLAGS Register
SCASQ	REX.W AF	SCAn String Quadword
STOSQ	REX.W AB	STOre String Quadword
SWAPGS	0F 01 F8	Exchange GS base with KernelGSBase MSR	0

1. The memory operand to CMPXCHG16B must be 16-byte aligned.
2. The CMPXCHG16B instruction was absent from a few of the earliest Intel/AMD x86-64 processors. On Intel processors, the instruction was missing from Xeon "Nocona" stepping D, ^[80] but added in stepping E. ^[81] On AMD K8 family processors, it was added in stepping F, at the same time as DDR2 support was introduced. ^[82]
   For this reason, CMPXCHG16B has its own CPUID flag, separate from the rest of x86-64.
3. Encodings of MOVSXD without REX.W prefix are permitted but discouraged ^[83] – such encodings behave identically to 16/32-bit MOV (8B /r).

Bit manipulation extensions

Main article: X86 Bit manipulation instruction set

Bit manipulation instructions. For all of the VEX-encoded instructions defined by BMI1 and BMI2, the operand size may be 32 or 64 bits, controlled by the VEX.W bit – none of these instructions are available in 16-bit variants.

Bit Manipulation Extension	Instruction mnemonics	Opcode	Instruction description	Added in
ABM (LZCNT) [lower-alpha 1] Advanced Bit Manipulation	POPCNT r16,r/m16 POPCNT r32,r/m32	F3 0F B8 /r	Population Count. Counts the number of bits that are set to 1 in its source argument.	K10, Bobcat, Haswell, ZhangJiang, Gracemont
	POPCNT r64,r/m64	F3 REX.W 0F B8 /r
	LZCNT r16,r/m16 LZCNT r32,r/m32	F3 0F BD /r	Count Leading zeroes. [lower-alpha 2] If source operand is all-0s, then LZCNT will return operand size in bits (16/32/64) and set CF=1.
	LZCNT r64,r/m64	F3 REX.W 0F BD /r
BMI1 Bit Manipulation Instruction Set 1	TZCNT r16,r/m16 TZCNT r32,r/m32	F3 0F BC /r	Count Trailing zeroes. [lower-alpha 3] If source operand is all-0s, then TZCNT will return operand size in bits (16/32/64) and set CF=1.	Haswell, Piledriver, Jaguar, ZhangJiang, Gracemont
	TZCNT r64,r/m64	F3 REX.W 0F BC /r
	ANDN ra,rb,r/m	VEX.LZ.0F38 F2 /r	Bitwise AND-NOT: ra = r/m AND NOT(rb)
	BEXTR ra,r/m,rb	VEX.LZ.0F38 F7 /r	Bitfield extract. Bitfield start position is specified in bits [7:0] of rb, length in bits[15:8] of rb. The bitfield is then extracted from the r/m value with zero-extension, then stored in ra. Equivalent to [lower-alpha 4] mask = (1 << rb[15:8]) - 1 ra = (r/m >> rb[7:0]) AND mask
	BLSI reg,r/m	VEX.LZ.0F38 F3 /3	Extract lowest set bit in source argument. Returns 0 if source argument is 0. Equivalent to dst = (-src) AND src
	BLSMSK reg,r/m	VEX.LZ.0F38 F3 /2	Generate a bitmask of all-1s bits up to the lowest bit position with a 1 in the source argument. Returns all-1s if source argument is 0. Equivalent to dst = (src-1) XOR src
	BLSR reg,r/m	VEX.LZ.0F38 F3 /1	Copy all bits of the source argument, then clear the lowest set bit. Equivalent to dst = (src-1) AND src
BMI2 Bit Manipulation Instruction Set 2	BZHI ra,r/m,rb	VEX.LZ.0F38 F5 /r	Zero out high-order bits in r/m starting from the bit position specified in rb, then write result to rd. Equivalent to ra = r/m AND NOT(-1 << rb[7:0])	Haswell, Excavator, [lower-alpha 5] ZhangJiang, Gracemont
	MULX ra,rb,r/m	VEX.LZ.F2.0F38 F6 /r	Widening unsigned integer multiply without setting flags. Multiplies EDX/RDX with r/m, then stores the low half of the multiplication result in ra and the high half in rb. If ra and rb specify the same register, only the high half of the result is stored.
	PDEP ra,rb,r/m	VEX.LZ.F2.0F38 F5 /r	Parallel Bit Deposit. Scatters contiguous bits from rb to the bit positions set in r/m, then stores result to ra. Operation performed is: ra=0; k=0; mask=r/m for i=0 to opsize-1 do if (mask[i] == 1) then ra[i]=rb[k]; k=k+1
	PEXT ra,rb,r/m	VEX.LZ.F3.0F38 F5 /r	Parallel Bit Extract. Uses r/m argument as a bit mask to select bits in rb, then compacts the selected bits into a contiguous bit-vector. Operation performed is: ra=0; k=0; mask=r/m for i=0 to opsize-1 do if (mask[i] == 1) then ra[k]=rb[i]; k=k+1
	RORX reg,r/m,imm8	VEX.LZ.F2.0F3A F0 /r ib	Rotate right by immediate without affecting flags.
	SARX ra,r/m,rb	VEX.LZ.F3.0F38 F7 /r	Arithmetic shift right without updating flags. For SARX, SHRX and SHLX, the shift-amount specified in rb is masked to 5 bits for 32-bit operand size and 6 bits for 64-bit operand size.
	SHRX ra,r/m,rb	VEX.LZ.F2.0F38 F7 /r	Logical shift right without updating flags.
	SHLX ra,r/m,rb	VEX.LZ.66.0F38 F7 /r	Shift left without updating flags.

1. On AMD CPUs, the "ABM" extension provides both POPCNT and LZCNT. On Intel CPUs, however, the CPUID bit for "ABM" is only documented to indicate the presence of the LZCNT instruction and is listed as "LZCNT", while POPCNT has its own separate CPUID feature bit.
   However, all known processors that implement the "ABM"/"LZCNT" extensions also implement POPCNT and set the CPUID feature bit for POPCNT, so the distinction is theoretical only.
   (The converse is not true – there exist processors that support POPCNT but not ABM, such as Intel Nehalem and VIA Nano 3000.)
2. The LZCNT instruction will execute as BSR on systems that do not support the LZCNT or ABM extensions. BSR computes the index of the highest set bit in the source operand, producing a different result from LZCNT for most input values.
3. The TZCNT instruction will execute as BSF on systems that do not support the BMI1 extension. BSF produces the same result as TZCNT for all input operand values except zero – for which TZCNT returns input operand size, but BSF produces undefined behavior (leaves destination unmodified on most modern CPUs).
4. For BEXTR, the start position and length are not masked and can take values from 0 to 255. If the selected bits extend beyond the end of the r/m argument (which has the usual 32/64-bit operand size), then the excess bits are read out as 0.
5. On AMD processors before Zen 3, the PEXT and PDEP instructions are quite slow ^[84] and exhibit data-dependent timing due to the use of a microcoded implementation (about 18 to 300 cycles, depending on the number of bits set in the mask argument). As a result, it is often faster to use other instruction sequences on these processors. ^{[85] [86]}

Added with Intel TSX

Main article: Transactional Synchronization Extensions

TSX Subset	Instruction	Opcode	Description	Added in
RTM Restricted Transactional memory	XBEGIN rel16 XBEGIN rel32	C7 F8 cw C7 F8 cd	Start transaction. If transaction fails, perform a branch to the given relative offset.	Haswell (Deprecated on desktop/laptop CPUs from 10th generation (Ice Lake, Comet Lake) onwards, but continues to be available on Xeon-branded server parts (e.g. Ice Lake-SP, Sapphire Rapids))
	XABORT imm8	C6 F8 ib	Abort transaction with 8-bit immediate as error code.
	XEND	NP 0F 01 D5	End transaction.
	XTEST	NP 0F 01 D6	Test if in transactional execution. Sets EFLAGS.ZF to 0 if executed inside a transaction (RTM or HLE), 1 otherwise.
HLE Hardware Lock Elision	XACQUIRE	F2	Instruction prefix to indicate start of hardware lock elision, used with memory atomic instructions only (for other instructions, the F2 prefix may have other meanings). When used with such instructions, may start a transaction instead of performing the memory atomic operation.	Haswell (Discontinued – the last processors to support HLE were Coffee Lake and Cascade Lake)
	XRELEASE	F3	Instruction prefix to indicate end of hardware lock elision, used with memory atomic/store instructions only (for other instructions, the F3 prefix may have other meanings). When used with such instructions during hardware lock elision, will end the associated transaction instead of performing the store/atomic.
TSXLDTRK Load Address Tracking suspend/resume	XSUSLDTRK	F2 0F 01 E8	Suspend Tracking Load Addresses	Sapphire Rapids
	XRESLDTRK	F2 0F 01 E9	Resume Tracking Load Addresses

Added with Intel CET

Intel CET (Control-Flow Enforcement Technology) adds two distinct features to help protect against security exploits such as return-oriented programming: a shadow stack (CET_SS), and indirect branch tracking (CET_IBT).

CET Subset	Instruction	Opcode	Description	Ring	Added in
CET_SS Shadow stack. When shadow stacks are enabled, return addresses are pushed on both the regular stack and the shadow stack when a function call is made. They are then both popped on return from the function call – if they do not match, then the stack is assumed to be corrupted, and a #CP exception is issued. The shadow stack is additionally required to be stored in specially marked memory pages which cannot be modified by normal memory store instructions.	INCSSPD r32	F3 0F AE /5	Increment shadow stack pointer	3	Tiger Lake, Zen 3
	INCSSPQ r64	F3 REX.W 0F AE /5
	RDSSPD r32	F3 0F 1E /1	Read shadow stack pointer into register (low 32 bits) [lower-alpha 1]
	RDSSPQ r64	F3 REX.W 0F 1E /1	Read shadow stack pointer into register (full 64 bits) [lower-alpha 1]
	SAVEPREVSSP	F3 0F 01 EA	Save previous shadow stack pointer
	RSTORSSP m64	F3 0F 01 /5	Restore saved shadow stack pointer
	WRSSD m32,r32	NP 0F 38 F6 /r	Write 4 bytes to shadow stack
	WRSSQ m64,r64	NP REX.W 0F 38 F6 /r	Write 8 bytes to shadow stack
	WRUSSD m32,r32	66 0F 38 F5 /r	Write 4 bytes to user shadow stack	0
	WRUSSQ m64,r64	66 REX.W 0F 38 F5 /r	Write 8 bytes to user shadow stack
	SETSSBSY	F3 0F 01 E8	Mark shadow stack busy
	CLRSSBSY m64	F3 0F AE /6	Clear shadow stack busy flag
CET_IBT Indirect Branch Tracking. When IBT is enabled, an indirect branch (jump, call, return) to any instruction that is not an ENDBR32/64 instruction will cause a #CP exception.	ENDBR32	F3 0F 1E FB	Terminate indirect branch in 32-bit mode [lower-alpha 2]	3	Tiger Lake
	ENDBR64	F3 0F 1E FA	Terminate indirect branch in 64-bit mode [lower-alpha 2]
	NOTRACK	3E [lower-alpha 3]	Prefix used with indirect CALL/JMP near instructions (opcodes FF /2 and FF /4) to indicate that the branch target is not required to start with an ENDBR32/64 instruction. Prefix only honored when NO_TRACK_EN flag is set.

1. The RDSSPD and RDSSPQ instructions act as NOPs on processors where shadow stacks are disabled or CET is not supported.
2. ENDBR32 and ENDBR64 act as NOPs on processors that don't support CET_IBT or where IBT is disabled.
3. This prefix has the same encoding as the DS: segment override prefix – as of April 2022, Intel documentation does not appear to specify whether this prefix also retains its old segment-override function when used as a no-track prefix, nor does it provide an official mnemonic for this prefix. ^{[87] [88]} (GNU binutils use "notrack" ^[89] )

Added with XSAVE

The XSAVE instruction set extensions are designed to save/restore CPU extended state (typically for the purpose of context switching) in a manner that can be extended to cover new instruction set extensions without the OS context-switching code needing to understand the specifics of the new extensions. This is done by defining a series of state-components, each with a size and offset within a given save area, and each corresponding to a subset of the state needed for one CPU extension or another. The EAX=0Dh CPUID leaf is used to provide information about which state-components the CPU supports and what their sizes/offsets are, so that the OS can reserve the proper amount of space and set the associated enable-bits.

XSAVE Extension	Instruction mnemonics	Opcode [lower-alpha 1]	Instruction description	Ring	Added in
XSAVE Processor Extended State Save/Restore.	XSAVE mem XSAVE64 mem	NP 0F AE /4 NP REX.W 0F AE /4	Save state components specified by bitmap in EDX:EAX to memory.	3	Penryn, [lower-alpha 2] Bulldozer, Jaguar, Goldmont, ZhangJiang
	XRSTOR mem XRSTOR64 mem	NP 0F AE /5 NP REX.W 0F AE /5	Restore state components specified by EDX:EAX from memory.
	XGETBV	NP 0F 01 D0	Get value of Extended Control Register. Reads an XCR specified by ECX into EDX:EAX. [lower-alpha 3]
	XSETBV	NP 0F 01 D1	Set Extended Control Register. [lower-alpha 4] Write the value in EDX:EAX to the XCR specified by ECX.	0
XSAVEOPT Processor Extended State Save/Restore Optimized	XSAVEOPT mem XSAVEOPT64 mem	NP 0F AE /6 NP REX.W 0F AE /6	Save state components specified by EDX:EAX to memory. Unlike the older XSAVE instruction, XSAVEOPT may abstain from writing processor state items to memory when the CPU can determine that they haven't been modified since the most recent corresponding XRSTOR.	3	Sandy Bridge, Steamroller, Puma, Goldmont, ZhangJiang
XSAVEC Processor Extended State save/restore with compaction.	XSAVEC mem XSAVEC64 mem	NP 0F C7 /4 NP REX.W 0F C7 /4	Save processor extended state components specified by EDX:EAX to memory with compaction.	3	Skylake, Goldmont, Zen 1
XSS Processor Extended State save/restore, including supervisor state.	XSAVES mem XSAVES64 mem	NP 0F C7 /5 NP REX.W 0F C7 /5	Save processor extended state components specified by EDX:EAX to memory with compaction and optimization if possible.	0	Skylake, Goldmont, Zen 1
	XRSTORS mem XRSTORS64 mem	NP 0F C7 /3 NP REX.W 0F C7 /3	Restore state components specified by EDX:EAX from memory.

1. Under Intel APX, the XSAVE* and XRSTOR* instructions cannot be encoded with the REX2 prefix.
2. XSAVE was added in steppings E0/R0 of Penryn and is not available in earlier steppings.
3. On some processors (starting with Skylake, Goldmont and Zen 1), executing XGETBV with ECX=1 is permitted – this will not return XCR1 (no such register exists) but instead return XCR0 bitwise-ANDed with the current value of the "XINUSE" state-component bitmap (a bitmap of XSAVE state-components that are not known to be in their initial state).
   The presence of this functionality of XGETBV is indicated by CPUID.(EAX=0Dh,ECX=1):EAX[bit 2].
4. The XSETBV instruction will cause a mandatory #VMEXIT if executed under Intel VT-x virtualization.

Added with other cross-vendor extensions

Instruction Set Extension	Instruction mnemonics	Opcode	Instruction description	Ring	Added in
SSE [lower-alpha 1] (non-SIMD)	PREFETCHNTA m8	0F 18 /0	Prefetch with Non-Temporal Access. Prefetch data under the assumption that the data will be used only once, and attempt to minimize cache pollution from said data. The methods used to minimize cache pollution are implementation-dependent. [lower-alpha 2]	3	Pentium III, (K7), [lower-alpha 1] (Geode GX2), [lower-alpha 1] Nehemiah, Efficeon
	PREFETCHT0 m8	0F 18 /1	Prefetch data to all levels of the cache hierarchy. [lower-alpha 2]
	PREFETCHT1 m8	0F 18 /2	Prefetch data to all levels of the cache hierarchy except L1 cache. [lower-alpha 2]
	PREFETCHT2 m8	0F 18 /3	Prefetch data to all levels of the cache hierarchy except L1 and L2 caches. [lower-alpha 2]
	SFENCE	NP 0F AE F8+x [lower-alpha 3]	Store Fence. [lower-alpha 4]
SSE2 (non-SIMD)	LFENCE	NP 0F AE E8+x [lower-alpha 3]	Load Fence and Dispatch Serialization. [lower-alpha 5]	3	Pentium 4, K8, Efficeon, C7 Esther
	MFENCE	NP 0F AE F0+x [lower-alpha 3]	Memory Fence. [lower-alpha 6]
	MOVNTI m32,r32 MOVNTI m64,r64	NP 0F C3 /r NP REX.W 0F C3 /r	Non-Temporal Memory Store.
	PAUSE	F3 90 [lower-alpha 7]	Pauses CPU thread for a short time period. [lower-alpha 8] Intended for use in spinlocks. [lower-alpha 9]
CLFSH [lower-alpha 10] Cache Line Flush.	CLFLUSH m8	NP 0F AE /7	Flush one cache line to memory. In a system with multiple cache hierarchy levels and/or multiple processors each with their own caches, the line is flushed from all of them.	3	(SSE2), Geode LX
MONITOR [lower-alpha 11] Monitor a memory location for memory writes.	MONITOR [lower-alpha 12] MONITOR EAX,ECX,EDX	NP 0F 01 C8	Start monitoring a memory location for memory writes. The memory address to monitor is given by DS:AX/EAX/RAX. [lower-alpha 13] ECX and EDX are reserved for extra extension and hint flags, respectively. [lower-alpha 14]	Usually 0 [lower-alpha 15]	Prescott, Yonah, Bonnell, K10, Nano
	MWAIT [lower-alpha 12] MWAIT EAX,ECX	NP 0F 01 C9	Wait for a write to a monitored memory location previously specified with MONITOR. [lower-alpha 16] ECX and EAX are used to provide extra extension [lower-alpha 17] and hint [lower-alpha 18] flags, respectively. MWAIT hints are commonly used for CPU power management.
SMX Safer Mode Extensions. Load, authenticate and execute a digitally signed "Authenticated Code Module" as part of Intel Trusted Execution Technology.	GETSEC	NP 0F 37 [lower-alpha 19]	Perform an SMX function. The leaf function to perform is given in EAX. [lower-alpha 20] Depending on leaf function, the instruction may take additional arguments in RBX, ECX and EDX.	Usually 0 [lower-alpha 21]	Conroe/Merom, WuDaoKou, [102] Tremont
RDTSCP Read Time Stamp Counter and Processor ID.	RDTSCP	0F 01 F9	Read Time Stamp Counter and processor core ID. [lower-alpha 22] The TSC value is placed in EDX:EAX and the core ID in ECX. [lower-alpha 23]	Usually 3 [lower-alpha 24]	K8, [lower-alpha 25] Nehalem, Silvermont, Nano
POPCNT [lower-alpha 26] Population Count.	POPCNT r16,r/m16 POPCNT r32,r/m32	F3 0F B8 /r	Count the number of bits that are set to 1 in its source argument.	3	K10, Nehalem, Nano 3000
	POPCNT r64,r/m64	F3 REX.W 0F B8 /r
SSE4.2 (non-SIMD)	CRC32 r32,r/m8	F2 0F 38 F0 /r	Accumulate CRC value using the CRC-32C (Castagnoli) polynomial 0x11EDC6F41 (normal form 0x1EDC6F41). This is the polynomial used in iSCSI. In contrast to the more popular one used in Ethernet, its parity is even, and it can thus detect any error with an odd number of changed bits.	3	Nehalem, Bulldozer, ZhangJiang
	CRC32 r32,r/m16 CRC32 r32,r/m32	F2 0F 38 F1 /r
	CRC32 r64,r/m64	F2 REX.W 0F 38 F1 /r
FSGSBASE Read/write base address of FS and GS segments from user-mode. Available in 64-bit mode only.	RDFSBASE r32 RDFSBASE r64	F3 0F AE /0 F3 REX.W 0F AE /0	Read base address of FS: segment.	3	Ivy Bridge, Steamroller, Goldmont, ZhangJiang
	RDGSBASE r32 RDGSBASE r64	F3 0F AE /1 F3 REX.W 0F AE /1	Read base address of GS: segment.
	WRFSBASE r32 WRFSBASE r64	F3 0F AE /2 F3 REX.W 0F AE /2	Write base address of FS: segment.
	WRGSBASE r32 WRGSBASE r64	F3 0F AE /3 F3 REX.W 0F AE /3	Write base address of GS: segment.
MOVBE Move to/from memory with byte order swap.	MOVBE r16,m16 MOVBE r32,m32	NFx 0F 38 F0 /r	Load from memory to register with byte-order swap.	3	Bonnell, Haswell, Jaguar, Steamroller, ZhangJiang
	MOVBE r64,m64	NFx REX.W 0F 38 F0 /r
	MOVBE m16,r16 MOVBE m32,r32	NFx 0F 38 F1 /r	Store to memory from register with byte-order swap.
	MOVBE m64,r64	NFx REX.W 0F 38 F1 /r
INVPCID Invalidate TLB entries by Process-context identifier.	INVPCID reg,m128	66 0F 38 82 /r	Invalidate entries in TLB and paging-structure caches based on invalidation type in register [lower-alpha 27] and descriptor in m128. The descriptor contains a memory address and a PCID. [lower-alpha 28] Instruction is serializing on AMD but not Intel CPUs.	0	Haswell, ZhangJiang, Zen 3, Gracemont
PREFETCHW [lower-alpha 29] Cache-line prefetch with intent to write.	PREFETCHW m8	0F 0D /1	Prefetch cache line with intent to write. [lower-alpha 2]	3	K6-2, (Cedar Mill), [lower-alpha 30] Silvermont, Broadwell, ZhangJiang
	PREFETCH m8 [lower-alpha 31]	0F 0D /0	Prefetch cache line. [lower-alpha 2]
ADX Enhanced variants of add-with-carry.	ADCX r32,r/m32 ADCX r64,r/m64	66 0F 38 F6 /r 66 REX.W 0F 38 F6 /r	Add-with-carry. Differs from the older ADC instruction in that it leaves flags other than EFLAGS.CF unchanged.	3	Broadwell, Zen 1, ZhangJiang, Gracemont
	ADOX r32,r/m32 ADOX r64,r/m64	F3 0F 38 F6 /r F3 REX.W 0F 38 F6 /r	Add-with-carry, with the overflow-flag EFLAGS.OF serving as carry input and output, with other flags left unchanged.
SMAP Supervisor Mode Access Prevention. Repurposes the EFLAGS.AC (alignment check) flag to a flag that prevents access to user-mode memory while in ring 0, 1 or 2.	CLAC	NP 0F 01 CA	Clear EFLAGS.AC.	0	Broadwell, Goldmont, Zen 1, LuJiaZui [lower-alpha 32]
	STAC	NP 0F 01 CB	Set EFLAGS.AC.
CLFLUSHOPT Optimized Cache Line Flush.	CLFLUSHOPT m8	NFx 66 0F AE /7	Flush cache line. Differs from the older CLFLUSH instruction in that it has more relaxed ordering rules with respect to memory stores and other cache line flushes, enabling improved performance.	3	Skylake, Goldmont, Zen 1
PREFETCHWT1 Cache-line prefetch into L2 cache with intent to write.	PREFETCHWT1 m8	0F 0D /2	Prefetch data with T1 locality hint (fetch into L2 cache, but not L1 cache) and intent-to-write hint. [lower-alpha 2]	3	Knights Landing, YongFeng
PKU Protection Keys for user pages.	RDPKRU	NP 0F 01 EE	Read User Page Key register into EAX.	3	Skylake-X, Comet Lake, Gracemont, Zen 3, LuJiaZui [lower-alpha 32]
	WRPKRU	NP 0F 01 EF	Write data from EAX into User Page Key Register, and perform a Memory Fence.
CLWB Cache Line Writeback to memory.	CLWB m8	NFx 66 0F AE /6	Write one cache line back to memory without invalidating the cache line.	3	Skylake-X, Zen 2, Tiger Lake, Tremont
RDPID Read processor core ID.	RDPID r32	F3 0F C7 /7	Read processor core ID into register. [lower-alpha 22]	3 [lower-alpha 33]	Goldmont Plus, Zen 2, Ice Lake, LuJiaZui [lower-alpha 32]
MOVDIRI Move to memory as Direct Store.	MOVDIRI m32,r32 MOVDIRI m64,r64	NP 0F 38 F9 /r NP REX.W 0F 38 F9 /r	Store to memory using Direct Store (memory store that is not cached or write-combined with other stores).	3	Tiger Lake, Tremont, Zen 5
MOVDIR64B Move 64 bytes as Direct Store.	MOVDIR64B reg,m512	66 0F 38 F8 /r	Move 64 bytes of data from m512 to address given by ES:reg. The 64-byte write is done atomically with Direct Store. [lower-alpha 34]	3	Tiger Lake, Tremont, Zen 5
WBNOINVD Whole Cache Writeback without invalidate.	WBNOINVD	F3 0F 09	Write back all dirty cache lines to memory without invalidation. [lower-alpha 35] Instruction is serializing.	0	Zen 2, Ice Lake-SP
PREFETCHI Instruction prefetch.	PREFETCHIT0 m8	0F 18 /7	Prefetch code to all levels of the cache hierarchy. [lower-alpha 36]	3	Zen 5, Granite Rapids
	PREFETCHIT1 m8	0F 18 /6	Prefetch code to all levels of the cache hierarchy except first-level cache. [lower-alpha 36]

1. AMD Athlon processors prior to the Athlon XP did not support full SSE, but did introduce the non-SIMD instructions of SSE as part of "MMX Extensions". ^[90] These extensions (without full SSE) are also present on Geode GX2 and later Geode processors.
2. All of the PREFETCH* instructions are hint instructions with effects only on performance, not program semantics. Providing an invalid address (e.g. address of an unmapped page or a non-canonical address) will cause the instruction to act as a NOP without any exceptions generated.
3. For the SFENCE, LFENCE and MFENCE instructions, the bottom 3 bits of the ModR/M byte are ignored, and any value of x in the range 0..7 will result in a valid instruction.
4. The SFENCE instruction ensures that all memory stores after the SFENCE instruction are made globally observable after all memory stores before the SFENCE. This imposes ordering on stores that can otherwise be reordered, such as non-temporal stores and stores to WC (Write-Combining) memory regions. ^[91]
   On Intel CPUs, as well as AMD CPUs from Zen1 onwards (but not older AMD CPUs), SFENCE also acts as a reordering barrier on cache flushes/writebacks performed with the CLFLUSH, CLFLUSHOPT and CLWB instructions. (Older AMD CPUs require MFENCE to order CLFLUSH.)
   SFENCE is not ordered with respect to LFENCE, and an SFENCE+LFENCE sequence is not sufficient to prevent a load from being reordered past a previous store. ^[92] To prevent such reordering, it is necessary to execute an MFENCE, LOCK or a serializing instruction.
5. The LFENCE instruction ensures that all memory loads after the LFENCE instruction are made globally observable after all memory loads before the LFENCE.
   On all Intel CPUs that support SSE2, the LFENCE instruction provides a stronger ordering guarantee: ^[93] it is dispatch-serializing, meaning that instructions after the LFENCE instruction are allowed to start executing only after all instructions before it have retired (which will ensure that all preceding loads but not necessarily stores have completed). The effect of dispatch-serialization is that LFENCE also acts as a speculation barrier and a reordering barrier for accesses to non-memory resources such as performance counters (accessed through e.g. RDTSC or RDPMC) and x2apic MSRs.
   On AMD CPUs, LFENCE is not necessarily dispatch-serializing by default – however, on all AMD CPUs that support any form of non-dispatch-serializing LFENCE, it can be made dispatch-serializing by setting bit 1 of MSR C001_1029. ^[94]
6. The MFENCE instruction ensures that all memory loads, stores and cacheline-flushes after the MFENCE instruction are made globally observable after all memory loads, stores and cacheline-flushes before the MFENCE.
   On Intel CPUs, MFENCE is not dispatch-serializing, and therefore cannot be used on its own to enforce ordering on accesses to non-memory resources such as performance counters and x2apic MSRs. MFENCE is still ordered with respect to LFENCE, so if there is a need to enforce ordering between memory stores and subsequent non-memory accesses, then such an ordering can be obtained by issuing an MFENCE followed by an LFENCE. ^{[49] [95]}
   On AMD CPUs, MFENCE is serializing.
7. The operation of the PAUSE instruction in 64-bit mode is, unlike NOP, unaffected by the presence of the REX.R prefix. Neither NOP nor PAUSE are affected by the other bits of the REX prefix. A few examples of how opcode 90 interacts with various prefixes in 64-bit mode are:
   • 90 is NOP
   • 41 90 is XCHG R8D,EAX
   • 4E 90 is NOP
   • 49 90 is XCHG R8,RAX
   • F3 90 is PAUSE
   • F3 41 90 is PAUSE
   • F3 4F 90 is PAUSE
8. The actual length of the pause performed by the PAUSE instruction is implementation-dependent.
   On systems without SSE2, PAUSE will execute as NOP.
9. Under VT-x or AMD-V virtualization, executing PAUSE many times in a short time interval may cause a #VMEXIT. The number of PAUSE executions and interval length that can trigger #VMEXIT are platform-specific.
10. While the CLFLUSH instruction was introduced together with SSE2, it has its own CPUID flag and may be present on processors not otherwise implementing SSE2 and/or absent from processors that otherwise implement SSE2. (E.g. AMD Geode LX supports CLFLUSH but not SSE2.)
11. While the MONITOR and MWAIT instructions were introduced at the same time as SSE3, they have their own CPUID flag that needs to be checked separately from the SSE3 CPUID flag (e.g. Athlon 64 X2 and VIA C7 supported SSE3 but not MONITOR.)
12. For the MONITOR and MWAIT instructions, older Intel documentation ^[96] lists instruction mnemonics with explicit operands (MONITOR EAX,ECX,EDX and MWAIT EAX,ECX), while newer documentation omits these operands. Assemblers/disassemblers may support one or both of these variants. ^[97]
13. For MONITOR, the DS: segment can be overridden with a segment prefix.
    The memory area that will be monitored will be not just the single byte specified by DS:rAX, but a linear memory region containing the byte – the size and alignment of this memory region is implementation-dependent and can be queried through CPUID.
    The memory location to monitor should have memory type WB (write-back cacheable), or else monitoring may fail.
14. As of April 2024, no extensions or hints have been defined for the MONITOR instruction. As such, the instruction requires ECX=0 and ignores EDX.
15. On some processors, such as Intel Xeon Phi x200 ^[98] and AMD K10 ^[99] and later, there exist documented MSRs that can be used to enable MONITOR and MWAIT to run in Ring 3.
16. The wait performed by MWAITmay be ended by system events other than a memory write (e.g. cacheline evictions, interrupts) – the exact set of events that can cause the wait to end is implementation-specific.
    Regardless of whether the wait was ended by a memory write or some other event, monitoring will have ended and it will be necessary to set up monitoring again with MONITOR before using MWAIT to wait for memory writes again.
17. The extension flags available for MWAIT in the ECX register are:

    Bits	MWAIT Extension
    0	Treat interrupts as break events, even when masked (EFLAGS.IF=0). (Available on all non-NetBurst implementations of MWAIT.)
    1	Timed MWAIT: end the wait when the TSC reaches or exceeds the value in EDX:EBX. (Undocumented, reportedly present in Intel Skylake and later Intel processors) [100]
    2	Monitorless MWAIT [101]
    31:3	Not used, must be set to zero.

18. The hint flags available for MWAIT in the EAX register are:

    Bits	MWAIT Hint
    3:0	Sub-state within a C-state (see bits 7:4) (Intel processors only)
    7:4	Target CPU power C-state during wait, minus 1. (E.g. 0000b for C1, 0001b for C2, 1111b for C0)
    31:8	Not used.

    The C-states are processor-specific power states, which do not necessarily correspond 1:1 to ACPI C-states.
19. For the GETSEC instruction, the REX.W prefix enables 64-bit addresses for the EXITAC leaf function only - REX prefixes are otherwise permitted but ignored for the instruction.
20. The leaf functions defined for GETSEC (selected by EAX) are:

    EAX	Function
    0 (CAPABILITIES)	Report SMX capabilities
    2 (ENTERACCES)	Enter execution of authenticated code module
    3 (EXITAC)	Exit execution of authenticated code module
    4 (SENTER)	Enter measured environment
    5 (SEXIT)	Exit measured environment
    6 (PARAMETERS)	Report SMX parameters
    7 (SMCTRL)	SMX Mode Control
    8 (WAKEUP)	Wake up sleeping processors in measured environment

    Any unsupported value in EAX causes an #UD exception.
21. For GETSEC, most leaf functions are restricted to Ring 0, but the CAPABILITIES (EAX=0) and PARAMETERS (EAX=6) leaf functions are available in Ring 3.
22. The "core ID" value read by RDTSCP and RDPID is actually the TSC_AUX MSR (MSR C000_0103h). Whether this value actually corresponds to a processor ID is a matter of operating system convention.
23. Unlike the older RDTSC instruction, RDTSCP will delay the TSC read until all previous instructions have retired, guaranteeing ordering with respect to preceding memory loads (but not stores). RDTSCP is not ordered with respect to subsequent instructions, though.
24. RDTSCP can be run outside Ring 0 only if CR4.TSD=0.
25. Support for RDTSCP was added in stepping F of the AMD K8, and is not available on earlier steppings.
26. While the POPCNT instruction was introduced at the same time as SSE4.2, it is not considered to be a part of SSE4.2, but instead a separate extension with its own CPUID flag.
    On AMD processors, it is considered to be a part of the ABM extension, but still has its own CPUID flag.
27. The invalidation types defined for INVPCID (selected by register argument) are:

    Value	Function
    0	Invalidate TLB entries matching PCID and virtual memory address in descriptor, excluding global entries
    1	Invalidate TLB entries matching PCID in descriptor, excluding global entries
    2	Invalidate all TLB entries, including global entries
    3	Invalidate all TLB entries, excluding global entries

    Any unsupported value in the register argument causes a #GP exception.
28. Unlike the older INVLPG instruction, INVPCID will cause a #GP exception if the provided memory address is non-canonical. This discrepancy has been known to cause security issues. ^[103]
29. The PREFETCH and PREFETCHW instructions are mandatory parts of the 3DNow! instruction set extension, but are also available as a standalone extension on systems that do not support 3DNow!
30. The opcodes for PREFETCH and PREFETCHW (0F 0D /r) execute as NOPs on Intel CPUs from Cedar Mill (65nm Pentium 4) onwards, with PREFETCHW gaining prefetch functionality from Broadwell onwards.
31. The PREFETCH (0F 0D /0) instruction is a 3DNow! instruction, present on all processors with 3DNow! but not necessarily on processors with the PREFETCHW extension.
    On AMD CPUs with PREFETCHW, opcode 0F 0D /0 as well as opcodes 0F 0D /2../7 are all documented to be performing prefetch.
    On Intel processors with PREFETCHW, these opcodes are documented as performing reserved-NOPs ^[104] (except 0F 0D /2 being PREFETCHWT1 m8 on Xeon Phi only) – third party testing ^[105] indicates that some or all of these opcodes may be performing prefetch on at least some Intel Core CPUs.
32. The SMAP, PKU and RDPID instruction set extensions are supported on stepping 2 ^[106] and later of Zhaoxin LuJiaZui, but not on earlier steppings.
33. Unlike the older RDTSCP instruction which can also be used to read the processor ID, user-mode RDPID is not disabled by CR4.TSD=1.
34. For MOVDIR64, the destination address given by ES:reg must be 64-byte aligned.
    The operand size for the register argument is given by the address size, which may be overridden by the 67h prefix.
    The 64-byte memory source argument does not need to be 64-byte aligned, and is not guaranteed to be read atomically.
35. The WBNOINVD instruction will execute as WBINVD if run on a system that doesn't support the WBNOINVD extension.
    WBINVD differs from WBNOINVD in that WBINVD will invalidate all cache lines after writeback.
36. In initial implementations, the PREFETCHIT0 and PREFETCHIT1 instructions will perform code prefetch only when using the RIP-relative addressing mode and act as NOPs otherwise.
    The PREFETCHI instructions are hint instructions only - if an attempt is made to prefetch an invalid address, the instructions will act as NOPs with no exceptions generated. On processors that support Long-NOP but do not support the PREFETCHI instructions, these instructions will always act as NOPs.

Added with other Intel-specific extensions

Instruction Set Extension	Instruction mnemonics	Opcode	Instruction description	Ring	Added in
SSE2 branch hints Instruction prefixes that can be used with the Jcc instructions to provide branch taken/not-taken hints.	(HWNT) [lower-alpha 1]	2E [lower-alpha 2]	Instruction prefix: branch hint weakly not taken.	3	Pentium 4, [lower-alpha 3] Meteor Lake [109]
	(HST) [lower-alpha 1]	3E [lower-alpha 2]	Instruction prefix: branch hint strongly taken.
SGX Software Guard Extensions. Set up an encrypted enclave in which a guest can execute code that a compromised or malicious host cannot inspect or tamper with.	ENCLS	NP 0F 01 CF	Perform an SGX Supervisor function. The function to perform is given in EAX [lower-alpha 4] - depending on function, the instruction may take additional input operands in RBX, RCX and RDX. Depending on function, the instruction may return data in RBX and/or an error code in EAX.	0	SGX1 Skylake, [lower-alpha 5] Goldmont Plus SGX2 Goldmont Plus, Ice Lake-SP [113] OVERSUB [110] Ice Lake-SP, Tremont
	ENCLU	NP 0F 01 D7	Perform an SGX User function. The function to perform is given in EAX [lower-alpha 6] - depending on function, the instruction may take additional input operands in RBX, RCX and RDX. Depending on function, the instruction may return data/status information in EAX and/or RCX.	3 [lower-alpha 7]
	ENCLV	NP 0F 01 C0	Perform an SGX Virtualization function. The function to perform is given in EAX [lower-alpha 8] - depending on function, the instruction may take additional input operands in RBX, RCX and RDX. Instruction returns status information in EAX.	0 [lower-alpha 9]
PTWRITE Write data to a Processor Trace Packet.	PTWRITE r/m32 PTWRITE r/m64	F3 0F AE /4 F3 REX.W 0F AE /4	Read data from register or memory to encode into a PTW packet. [lower-alpha 10]	3	Kaby Lake, Goldmont Plus
PCONFIG Platform Configuration, including TME-MK ("Total Memory Encryption – Multi-Key") and TSE ("Total Storage Encryption").	PCONFIG	NP 0F 01 C5	Perform a platform feature configuration function. The function to perform is specified in EAX [lower-alpha 11] - depending on function, the instruction may take additional input operands in RBX, RCX and RDX. If the instruction fails, it will set EFLAGS.ZF=1 and return an error code in EAX. If it is successful, it sets EFLAGS.ZF=0 and EAX=0.	0	Ice Lake-SP
CLDEMOTE Cache Line Demotion Hint.	CLDEMOTE m8	NP 0F 1C /0	Move cache line containing m8 from CPU L1 cache to a more distant level of the cache hierarchy. [lower-alpha 12]	3	(Tremont), (Alder Lake), Sapphire Rapids [lower-alpha 13]
WAITPKG User-mode memory monitoring and waiting.	UMONITOR r16/32/64	F3 0F AE /6	Start monitoring a memory location for memory writes. The memory address to monitor is given by the register argument. [lower-alpha 14]	3	Tremont, Alder Lake
	UMWAIT r32 UMWAIT r32,EDX,EAX	F2 0F AE /6	Timed wait for a write to a monitored memory location previously specified with UMONITOR. In the absence of a memory write, the wait will end when either the TSC reaches the value specified by EDX:EAX or the wait has been going on for an OS-controlled maximum amount of time. [lower-alpha 15]	Usually 3 [lower-alpha 16]
	TPAUSE r32 TPAUSE r32,EDX,EAX	66 0F AE /6	Wait until the Time Stamp Counter reaches the value specified in EDX:EAX. [lower-alpha 15] The register argument to the UMWAIT and TPAUSE instructions specifies extra flags to control the operation of the instruction. [lower-alpha 17]
SERIALIZE Instruction Execution Serialization.	SERIALIZE	NP 0F 01 E8	Serialize instruction fetch and execution. [lower-alpha 18]	3	Alder Lake
HRESET Processor History Reset.	HRESET imm8	F3 0F 3A F0 C0 ib	Request that the processor reset selected components of hardware-maintained prediction history. A bitmap of which components of the CPU's prediction history to reset is given in EAX (the imm8 argument is ignored). [lower-alpha 19]	0	Alder Lake
UINTR User Interprocessor interrupt. Available in 64-bit mode only.	SENDUIPI reg	F3 0F C7 /6	Send Interprocessor User Interrupt. [lower-alpha 20]	3	Sapphire Rapids
	UIRET	F3 0F 01 EC	User Interrupt Return. Pops RIP, RFLAGS and RSP off the stack, in that order. [lower-alpha 21]
	TESTUI	F3 0F 01 ED	Test User Interrupt Flag. Copies UIF to EFLAGS.CF .
	CLUI	F3 0F 01 EE	Clear User Interrupt Flag.
	STUI	F3 0F 01 EF	Set User Interrupt Flag.
ENQCMD Enqueue Store. Part of Intel DSA (Data Streaming Accelerator Architecture). [117]	ENQCMD r32/64,m512	F2 0F 38 F8 /r	Enqueue Command. Reads a 64-byte "command data" structure from memory (m512 argument) and writes atomically to a memory-mapped Enqueue Store device (register argument provides the memory address of this device, using ES segment and requiring 64-byte alignment.) Sets ZF=0 to indicate that device accepted the command, or ZF=1 to indicate that command was not accepted (e.g. queue full or the memory location was not an Enqueue Store device.)	3	Sapphire Rapids
	ENQCMDS r32/64,m512	F3 0F 38 F8 /r	Enqueue Command Supervisor. Differs from ENQCMD in that it can place an arbitrary PASID (process address-space identifier) and a privilege-bit in the "command data" to enqueue.	0
WRMSRNS Non-serializing Write to Model-specific register.	WRMSRNS	NP 0F 01 C6	Write Model-specific register. The MSR to write is specified in ECX, and the data to write is given in EDX:EAX. The instruction differs from the older WRMSR instruction in that it is not serializing.	0	Sierra Forest
MSRLIST Read/write multiple Model-specific registers. Available in 64-bit mode only.	RDMSRLIST	F2 0F 01 C6	Read multiple MSRs. RSI points to a table of up to 64 MSR indexes to read (64 bits each), RDI points to a table of up to 64 data items that the MSR read-results will be written to (also 64 bits each), and RCX provides a 64-entry bitmap of which of the table entries to actually perform an MSR read for. [lower-alpha 22]	0	Sierra Forest
	WRMSRLIST	F3 0F 01 C6	Write multiple MSRs. RSI points to a table of up to 64 MSR indexes to write (64 bits each), RDI points to a table of up to 64 data items to write into the MSRs (also 64 bits each), and RCX provides a 64-entry bitmap of which of the table entries to actually perform an MSR write for. [lower-alpha 22] The instruction is not serializing.
CMPCCXADD Atomically perform a compare - and a fetch-and-add if the condition is met. Available in 64-bit mode only.	CMPccXADD m32,r32,r32 CMPccXADD m64,r64,r64	VEX.128.66.0F38.W0 Ex /r VEX.128.66.0F38.W1 Ex /r [lower-alpha 23] [lower-alpha 24]	Read value from memory, then compare to first register operand. If the comparison passes, then add the second register operand to the memory value. The instruction as a whole is performed atomically. The operation of CMPccXADD [mem],reg1,reg2 is: temp1 := [mem] EFLAGS := CMP temp1, reg1 // sets EFLAGS like regular compare reg1 := temp1 if( condition ) [mem] := temp1 + reg2	3	Sierra Forest, Lunar Lake
PBNDKB Platform Bind Key to Binary Large Object. Part of Intel TSE (Total Storage Encryption), and available in 64-bit mode only.	PBNDKB	NP 0F 01 C7	Bind information to a platform by encrypting it with a platform-specific wrapping key. The instruction takes as input the addresses to two 256-byte-aligned "bind structures" in RBX and RCX, reads the structure pointed to by RBX and writes a modified structure to the address given in RCX. If the instruction fails, it will set EFLAGS.ZF=1 and return an error code in EAX. If it is successful, it sets EFLAGS.ZF=0 and EAX=0.	0	Lunar Lake

1. The branch hint mnemonics HWNT and HST are listed in early Willamette documentation only ^[107] - later Intel documentation lists the branch hint prefixes without assigning them a mnemonic. ^[108]
2. The 2E and 3E prefixes are interpreted as branch hints only when used with the Jcc conditional branch instructions (opcodes 70..7F and 0F 80..8F) - when used with other opcodes, they may take other meanings (e.g. for instructions with memory operands outside 64-bit mode, they will work as segment-override prefixes CS: and DS:, respectively). On processors that don't support branch hints, these prefixes are accepted but ignored when used with Jcc.
3. Branch hints are supported on all NetBurst (Pentium 4 family) processors - but not supported on any other known processor prior to their re-introduction in "Redwood Cove" CPUs, starting with "Meteor Lake" in 2023.
4. The leaf functions defined for ENCLS (selected by EAX) are:

   EAX	Function
   0 (ECREATE)	Create an enclave
   1 (EADD)	Add a page
   2 (EINIT)	Initialize an enclave
   3 (EREMOVE)	Remove a page from EPC (Enclave Page Cache)
   4 (EDBGRD)	Read data by debugger
   5 (EDBGWR)	Write data by debugger
   6 (EEXTEND)	Extend EPC page measurement
   7 (ELDB)	Load an EPC page as blocked
   8 (ELDU)	Load an EPC page as unblocked
   9 (EBLOCK)	Block an EPC page
   A (EPA)	Add version array
   B (EWB)	Writeback/invalidate EPC page
   C (ETRACK)	Activate EBLOCK checks
   Added with SGX2
   D (EAUG)	Add page to initialized enclave
   E (EMODPTR)	Restrict permissions of EPC page
   F (EMODT)	Change type of EPC page
   Added with OVERSUB [110]
   10 (ERDINFO)	Read EPC page type/status info
   11 (ETRACKC)	Activate EBLOCK checks
   12 (ELDBC)	Load EPC page as blocked with enhanced error reporting
   13 (ELDUC)	Load EPC page as unblocked with enhanced error reporting
   Other
   18 (EUPDATESVN)	Update SVN (Security Version Number) after live microcode update [111]

   Any unsupported value in EAX causes a #GP exception.
5. SGX is deprecated on desktop/laptop processors from 11th generation (Rocket Lake, Tiger Lake) onwards, but continues to be available on Xeon-branded server parts. ^[112]
6. The leaf functions defined for ENCLU (selected by EAX) are:

   EAX	Function
   0 (EREPORT)	Create a cryptographic report
   1 (EGETKEY)	Create a cryptographic key
   2 (EENTER)	Enter an Enclave
   3 (ERESUME)	Re-enter an Enclave
   4 (EEXIT)	Exit an Enclave
   Added with SGX2
   5 (EACCEPT)	Accept changes to EPC page
   6 (EMODPE)	Extend EPC page permissions
   7 (EACCEPTCOPY)	Initialize pending page
   Added with TDX [114]
   8 (EVERIFYREPORT2)	Verify a cryptographic report of a trust domain
   Added with AEX-Notify
   9 (EDECCSSA)	Decrement TCS.CSSA

   Any unsupported value in EAX causes a #GP exception.
   The EENTER and ERESUME functions cannot be executed inside an SGX enclave – the other functions can only be executed inside an enclave.
7. ENCLU can only be executed in ring 3, not rings 0/1/2.
8. The leaf functions defined for ENCLV (selected by EAX) are:

   EAX	Function
   Added with OVERSUB [110]
   0 (EDECVIRTCHILD)	Decrement VIRTCHILDCNT in SECS
   1 (EINCVIRTCHILD)	Increment VIRTCHILDCNT in SECS
   2 (ESETCONTEXT)	Set ENCLAVECONTEXT field in SECS

   Any unsupported value in EAX causes a #GP exception.
   The ENCLV instruction is only present on systems that support the EPC Oversubscription Extensions to SGX ("OVERSUB").
9. ENCLV is only available if Intel VMX operation is enabled with VMXON, and will produce #UD otherwise.
10. For PTWRITE, the write to the Processor Trace Packet will only happen if a set of enable-bits (the "TriggerEn", "ContextEn", "FilterEn" bits of the RTIT_STATUS MSR and the "PTWEn" bit of the RTIT_CTL MSR) are all set to 1.
    The PTWRITE instruction is indicated in the SDM to cause an #UD exception if the 66h instruction prefix is used, regardless of other prefixes.
11. The leaf functions defined for PCONFIG (selected by EAX) are:

    EAX	Function
    0	MKTME_KEY_PROGRAM: Program key and encryption mode to use with an TME-MK Key ID.
    Added with TSE
    1	TSE_KEY_PROGRAM: Direct key programming for TSE.
    2	TSE_KEY_PROGRAM_WRAPPED: Wrapped key programming for TSE.

    Any unsupported value in EAX causes a #GP(0) exception.
12. For CLDEMOTE, the cache level that it will demote a cache line to is implementation-dependent.
    Since the instruction is considered a hint, it will execute as a NOP without any exceptions if the provided memory address is invalid or not in the L1 cache. It may also execute as a NOP under other implementation-dependent circumstances as well.
    On systems that do not support the CLDEMOTE extension, it executes as a NOP.
13. Intel documentation lists Tremont and Alder Lake as the processors in which CLDEMOTE was introduced. However, as of May 2022, no Tremont or Alder Lake models have been observed to have the CPUID feature bit for CLDEMOTE set, while several of them have the CPUID bit cleared. ^[115]
    As of April 2023, the CPUID feature bit for CLDEMOTE has been observed to be set for Sapphire Rapids. ^[116]
14. For UMONITOR, the operand size of the address argument is given by the address size, which may be overridden by the 67h prefix. The default segment used is DS:, which can be overridden with a segment prefix.
15. For the UMWAIT and TPAUSE instructions, the operating system can use the IA32_UMWAIT_CONTROL MSR to limit the maximum amount of time that a single UMWAIT/TPAUSE invocation is permitted to wait. The UMWAIT and TPAUSE instructions will set RFLAGS.CF to 1 if they reached the IA32_UMWAIT_CONTROL-defined time limit and 0 otherwise.
16. TPAUSE and UMWAIT can be run outside Ring 0 only if CR4.TSD=0.
17. For the register argument to the UMWAIT and TPAUSE instructions, the following flag bits are supported:

    Bits	Usage
    0	Preferred optimization state. 0 = C0.2 (slower wakeup, improves performance of other SMT threads on same core) 1 = C0.1 (faster wakeup)
    31:1	(Reserved)

18. While serialization can be performed with older instructions such as e.g. CPUID and IRET, these instructions perform additional functions, causing side-effects and reduced performance when stand-alone instruction serialization is needed. (CPUID additionally has the issue that it causes a mandatory #VMEXIT when executed under virtualization, which causes a very large overhead.) The SERIALIZE instruction performs serialization only, avoiding these added costs.
19. A bitmap of CPU history components that can be reset through HRESET is provided by CPUID.(EAX=20h,ECX=0):EBX.
    As of July 2023, the following bits are defined:

    Bit	Usage
    0	Intel Thread Director history
    31:1	(Reserved)

20. The register argument to SENDUIPI is an index to pick an entry from the UITT (User-Interrupt Target Table, a table specified by the new UINTR_TT and UINT_MISC MSRs.)
21. On Sapphire Rapids processors, the UIRET instruction always sets UIF (User Interrupt Flag) to 1. On Sierra Forest and later processors, UIRET will set UIF to the value of bit 1 of the value popped off the stack for RFLAGS - this functionality is indicated by CPUID.(EAX=7,ECX=1):EDX[17].
22. For the RDMSRLIST and WRMSRLIST instructions, the addresses specified in the RSI and RDI registers must be 8-byte aligned.
23. The condition codes supported for the CMPccXADD instructions (opcode VEX.128.66.0F38 Ex /r with the x nibble specifying the condition) are:

    x	cc	Condition (EFLAGS)
    0	O	OF=1: "Overflow"
    1	NO	OF=0: "Not Overflow"
    2	B	CF=1: "Below"
    3	NB	CF=0: "Not Below"
    4	Z	ZF=1: "Zero"
    5	NZ	ZF=0: "Not Zero"
    6	BE	(CF=1 or ZF=1): "Below or Equal"
    7	NBE	(CF=0 and ZF=0): "Not Below or Equal"
    8	S	SF=1: "Sign"
    9	NS	SF=0: "Not Sign"
    A	P	PF=1: "Parity"
    B	NP	PF=0: "Not Parity"
    C	L	SF≠OF: "Less"
    D	NL	SF=OF: "Not Less"
    E	LE	(ZF=1 or SF≠OF): "Less or Equal"
    F	NLE	(ZF=0 and SF=OF): "Not Less or Equal"

24. Even though the CMPccXADD instructions perform a locked memory operation, they do not require or accept the LOCK (F0h) prefix - attempting to use this prefix results in #UD.

Added with other AMD-specific extensions

Instruction Set Extension	Instruction mnemonics	Opcode	Instruction description	Ring	Added in
AltMovCr8 Alternative mechanism to access the CR8 control register. [lower-alpha 1]	MOV reg,CR8	F0 0F 20 /0 [lower-alpha 2]	Read the CR8 register.	0	K8 [lower-alpha 3]
	MOV CR8,reg	F0 0F 22 /0 [lower-alpha 2]	Write to the CR8 register.
MONITORX Monitor a memory location for writes in user mode.	MONITORX	NP 0F 01 FA	Start monitoring a memory location for memory writes. Similar to older MONITOR, except available in user mode.	3	Excavator
	MWAITX	NP 0F 01 FB	Wait for a write to a monitored memory location previously specified with MONITORX. MWAITX differs from the older MWAIT instruction mainly in that it runs in user mode and that it can accept an optional timeout argument (given in TSC time units) in EBX (enabled by setting bit[1] of ECX to 1.)
CLZERO Zero out full cache line.	CLZERO rAX	NP 0F 01 FC	Write zeroes to all bytes in a memory region that has the size and alignment of a CPU cache line and contains the byte addressed by DS:rAX. [lower-alpha 4]	3	Zen 1
RDPRU Read processor register in user mode.	RDPRU	NP 0F 01 FD	Read selected MSRs (mainly performance counters) in user mode. ECX specifies which register to read. [lower-alpha 5] The value of the MSR is returned in EDX:EAX.	Usually 3 [lower-alpha 6]	Zen 2
MCOMMIT Commit Stores To Memory.	MCOMMIT	F3 0F 01 FA	Ensure that all preceding stores in thread have been committed to memory, and that any errors encountered by these stores have been signalled to any associated error logging resources. The set of errors that can be reported and the logging mechanism are platform-specific. Sets EFLAGS.CF to 0 if any errors occurred, 1 otherwise.	3	Zen 2
INVLPGB Invalidate TLB Entries with broadcast.	INVLPGB	NP 0F 01 FE	Invalidate TLB Entries for a range of pages, with broadcast. The invalidation is performed on the processor executing the instruction, and also broadcast to all other processors in the system. rAX takes the virtual address to invalidate and some additional flags, ECX takes the number of pages to invalidate, and EDX specifies ASID and PCID to perform TLB invalidation for.	0	Zen 3
	TLBSYNC	NP 0F 01 FF	Synchronize TLB invalidations. Wait until all TLB invalidations signalled by preceding invocations of the INVLPGB instruction on the same logical processor have been responded to by all processors in the system. Instruction is serializing.

1. The standard way to access the CR8 register is to use an encoding that makes use of the REX.R prefix, e.g. 44 0F 20 07 (MOV RDI,CR8). However, the REX.R prefix is only available in 64-bit mode.
   The AltMovCr8 extension adds an additional method to access CR8, using the F0 (LOCK) prefix instead of REX.R – this provides access to CR8 outside 64-bit mode.
2. Like other variants of MOV to/from the CRx registers, the AltMovCr8 encodings ignore the top 2 bits of the instruction's ModR/M byte, and always execute as if these two bits are set to 11b.
   The AltMovCr8 encodings are available in 64-bit mode. However, combining the LOCK prefix with the REX.R prefix is not permitted and will cause an #UD exception.
3. Support for AltMovCR8 was added in stepping F of the AMD K8, and is not available on earlier steppings.
4. For CLZERO, the address size and 67h prefix control whether to use AX, EAX or RAX as address. The default segment DS: can be overridden by a segment-override prefix. The provided address does not need to be aligned – hardware will align it as necessary.
   The CLZERO instruction is intended for recovery from otherwise-fatal Machine Check errors. It is non-cacheable, cannot be used to allocate a cache line without a memory access, and should not be used for fast memory clears. ^[118]
5. The register numbering used by RDPRU does not necessarily match that of RDMSR/WRMSR.
   The registers supported by RDPRU as of December 2022 are:

   ECX	Register
   0	MPERF (MSR 0E7h: Maximum Performance Frequency Clock Count)
   1	APERF (MSR 0E8h: Actual Performance Frequency Clock Count)

   Unsupported values in ECX return 0.
6. If CR4.TSD=1, then the RDPRU instruction can only run in ring 0.

x87 floating-point instructions

The x87 coprocessor, if present, provides support for floating-point arithmetic. The coprocessor provides eight data registers, each holding one 80-bit floating-point value (1 sign bit, 15 exponent bits, 64 mantissa bits) – these registers are organized as a stack, with the top-of-stack register referred to as "st" or "st(0)", and the other registers referred to as st(1),st(2),...st(7). It additionally provides a number of control and status registers, including "PC" (precision control, to control whether floating-point operations should be rounded to 24, 53 or 64 mantissa bits) and "RC" (rounding control, to pick rounding-mode: round-to-zero, round-to-positive-infinity, round-to-negative-infinity, round-to-nearest-even) and a 4-bit condition code register "CC", whose four bits are individually referred to as C0,C1,C2 and C3). Not all of the arithmetic instructions provided by x87 obey PC and RC.

Original 8087 instructions

Instruction description	Mnemonic	Opcode	Additional items
x87 Non-Waiting [lower-alpha 1] FPU Control Instructions			Waiting mnemonic [lower-alpha 2]
Initialize x87 FPU	FNINIT	DB E3	FINIT
Load x87 Control Word	FLDCW m16	D9 /5	(none)
Store x87 Control Word	FNSTCW m16	D9 /7	FSTCW
Store x87 Status Word	FNSTSW m16	DD /7	FSTSW
Clear x87 Exception Flags	FNCLEX	DB E2	FCLEX
Load x87 FPU Environment	FLDENV m112/m224 [lower-alpha 3]	D9 /4	(none)
Store x87 FPU Environment	FNSTENV m112/m224 [lower-alpha 3]	D9 /6	FSTENV
Save x87 FPU State, then initialize x87 FPU	FNSAVE m752/m864 [lower-alpha 3]	DD /6	FSAVE
Restore x87 FPU State	FRSTOR m752/m864 [lower-alpha 3]	DD /4	(none)
Enable Interrupts (8087 only) [lower-alpha 4]	FNENI	DB E0	FENI
Disable Interrupts (8087 only) [lower-alpha 4]	FNDISI	DB E1	FDISI
x87 Floating-point Load/Store/Move Instructions			precision control	rounding control
Load floating-point value onto stack	FLD m32	D9 /0	No	—
	FLD m64	DD /0
	FLD m80	DB /5
	FLD st(i)	D9 C0+i
Store top-of-stack floating-point value to memory or stack register	FST m32	D9 /2	No	Yes
	FST m64	DD /2
	FST st(i) [lower-alpha 5]	DD D0+i	No	—
Store top-of-stack floating-point value to memory or stack register, then pop	FSTP m32	D9 /3	No	Yes
	FSTP m64	DD /3
	FSTP m80 [lower-alpha 5]	DB /7	No	—
	FSTP st(i) [lower-alpha 5] [lower-alpha 6]	DD D8+i
		DF D0+i [lower-alpha 7]
		DF D8+i [lower-alpha 7]
Push +0.0 onto stack	FLDZ	D9 EE	No	—
Push +1.0 onto stack	FLD1	D9 E8
Push π (approximately 3.14159) onto stack	FLDPI	D9 EB	No	387 [lower-alpha 8]
Push ${\displaystyle \log _{2}\left(10\right)}$ (approximately 3.32193) onto stack	FLDL2T	D9 E9
Push ${\displaystyle \log _{2}\left(e\right)}$ (approximately 1.44269) onto stack	FLDL2E	D9 EA
Push ${\displaystyle \log _{10}\left(2\right)}$ (approximately 0.30103) onto stack	FLDLG2	D9 EC
Push ${\displaystyle \ln \left(2\right)}$ (approximately 0.69315) onto stack	FLDLN2	D9 ED
Exchange top-of-stack register with other stack register	FXCH st(i) [lower-alpha 9] [lower-alpha 10]	D9 C8+i	No	—
		DD C8+i [lower-alpha 7]
		DF C8+i [lower-alpha 7]
x87 Integer Load/Store Instructions			precision control	rounding control
Load signed integer value onto stack from memory, with conversion to floating-point	FILD m16	DF /0	No	—
	FILD m32	DB /0
	FILD m64	DF /5
Store top-of-stack value to memory, with conversion to signed integer	FIST m16	DF /2	No	Yes
	FIST m32	DB /2
Store top-of-stack value to memory, with conversion to signed integer, then pop stack	FISTP m16	DF /3	No	Yes
	FISTP m32	DB /3
	FISTP m64	DF /7
Load 18-digit Binary-Coded-Decimal integer value onto stack from memory, with conversion to floating-point	FBLD m80 [lower-alpha 11]	DF /4	No	—
Store top-of-stack value to memory, with conversion to 18-digit Binary-Coded-Decimal integer, then pop stack	FBSTP m80	DF /6	No	387 [lower-alpha 8]
x87 Basic Arithmetic Instructions			precision control	rounding control
Floating-point add dst <- dst + src	FADD m32	D8 /0	Yes	Yes
	FADD m64	DC /0
	FADD st,st(i)	D8 C0+i
	FADD st(i),st	DC C0+i
Floating-point multiply dst <- dst * src	FMUL m32	D8 /1	Yes	Yes
	FMUL m64	DC /1
	FMUL st,st(i)	D8 C8+i
	FMUL st(i),st	DC C8+i
Floating-point subtract dst <- dst – src	FSUB m32	D8 /4	Yes	Yes
	FSUB m64	DC /4
	FSUB st,st(i)	D8 E0+i
	FSUB st(i),st	DC E8+i
Floating-point reverse subtract dst <- src – dst	FSUBR m32	D8 /5	Yes	Yes
	FSUBR m64	DC /5
	FSUBR st,st(i)	D8 E8+i
	FSUBR st(i),st	DC E0+i
Floating-point divide [lower-alpha 12] dst <- dst / src	FDIV m32	D8 /6	Yes	Yes
	FDIV m64	DC /6
	FDIV st,st(i)	D8 F0+i
	FDIV st(i),st	DC F8+i
Floating-point reverse divide dst <- src / dst	FDIVR m32	D8 /7	Yes	Yes
	FDIVR m64	DC /7
	FDIVR st,st(i)	D8 F8+i
	FDIVR st(i),st	DC F0+i
Floating-point compare CC <- result_of( st(0) – src ) Same operation as subtract, except that it updates the x87 CC status register instead of any of the FPU stack registers	FCOM m32	D8 /2	No	—
	FCOM m64	DC /2
	FCOM st(i) [lower-alpha 9]	D8 D0+i
		DC D0+i [lower-alpha 7]
x87 Basic Arithmetic Instructions with Stack Pop			precision control	rounding control
Floating-point add and pop	FADDP st(i),st [lower-alpha 9]	DE C0+i	Yes	Yes
Floating-point multiply and pop	FMULP st(i),st [lower-alpha 9]	DE C8+i	Yes	Yes
Floating-point subtract and pop	FSUBP st(i),st [lower-alpha 9]	DE E8+i	Yes	Yes
Floating-point reverse-subtract and pop	FSUBRP st(i),st [lower-alpha 9]	DE E0+i	Yes	Yes
Floating-point divide and pop	FDIVP st(i),st [lower-alpha 9]	DE F8+i	Yes	Yes
Floating-point reverse-divide and pop	FDIVRP st(i),st [lower-alpha 9]	DE F0+i	Yes	Yes
Floating-point compare and pop	FCOMP m32	D8 /3	No	—
	FCOMP m64	DC /3
	FCOMP st(i) [lower-alpha 9]	D8 D8+i
		DC D8+i [lower-alpha 7]
		DE D0+i [lower-alpha 7]
Floating-point compare to st(1), then pop twice	FCOMPP	DE D9	No	—
x87 Basic Arithmetic Instructions with Integer Source Argument			precision control	rounding control
Floating-point add by integer	FIADD m16	DA /0	Yes	Yes
	FIADD m32	DE /0
Floating-point multiply by integer	FIMUL m16	DA /1	Yes	Yes
	FIMUL m32	DE /1
Floating-point subtract by integer	FISUB m16	DA /4	Yes	Yes
	FISUB m32	DE /4
Floating-point reverse-subtract by integer	FISUBR m16	DA /5	Yes	Yes
	FISUBR m32	DE /5
Floating-point divide by integer	FIDIV m16	DA /6	Yes	Yes
	FIDIV m32	DE /6
Floating-point reverse-divide by integer	FIDIVR m16	DA /7	Yes	Yes
	FIDIVR m32	DE /7
Floating-point compare to integer	FICOM m16	DA /2	No	—
	FICOM m32	DE /2
Floating-point compare to integer, and stack pop	FICOMP m16	DA /3	No	—
	FICOMP m32	DE /3
x87 Additional Arithmetic Instructions			precision control	rounding control
Floating-point change sign	FCHS	D9 E0	No	—
Floating-point absolute value	FABS	D9 E1	No	—
Floating-point compare top-of-stack value to 0	FTST	D9 E4	No	—
Classify top-of-stack st(0) register value. The classification result is stored in the x87 CC register. [lower-alpha 13]	FXAM	D9 E5	No	—
Split the st(0) value into two values E and M representing the exponent and mantissa of st(0). The split is done such that ${\displaystyle M*2^{E}=st(0)}$, where E is an integer and M is a number whose absolute value is within the range ${\displaystyle 1\leq \left|M\right|<2}$.   [lower-alpha 14] st(0) is then replaced with E, after which M is pushed onto the stack.	FXTRACT	D9 F4	No	—
Floating-point partial [lower-alpha 15] remainder (not IEEE 754 compliant):$${\displaystyle Q\leftarrow {\mathtt {IntegerRoundToZero}}\left({\frac {st(0)}{st(1)}}\right)}$$$${\displaystyle st(0)\leftarrow st(0)-st(1)*Q}$$	FPREM	D9 F8	No	— [lower-alpha 16]
Floating-point square root	FSQRT	D9 FA	Yes	Yes
Floating-point round to integer	FRNDINT	D9 FC	No	Yes
Floating-point power-of-2 scaling. Rounds the value of st(1) to integer with round-to-zero, then uses it as a scale factor for st(0): [lower-alpha 17] $${\displaystyle st(0)\leftarrow st(0)*2^{{\mathtt {IntegerRoundToZero}}\left(st(1)\right)}}$$	FSCALE	D9 FD	No	Yes [lower-alpha 18]
x87 Transcendental Instructions [lower-alpha 19]			Source operand range restriction
Base-2 exponential minus 1, with extra precision for st(0) close to 0:$${\displaystyle st(0)\leftarrow 2^{st(0)}-1}$$	F2XM1	D9 F0	8087: ${\displaystyle 0\leq st(0)\leq {\frac {1}{2}}}$ 80387: ${\displaystyle -1\leq st(0)\leq 1}$
Base-2 Logarithm:$${\displaystyle st(1)\leftarrow st(1)*\log _{2}\left(st(0)\right)}$$followed by stack pop	FYL2X [lower-alpha 20]	D9 F1	no restrictions
Partial Tangent: Computes from st(0) a pair of values X and Y, such that$${\displaystyle \tan \left(st(0)\right)={\frac {Y}{X}}}$$The Y value replaces the top-of-stack value, and then X is pushed onto the stack. On 80387 and later x87, but not original 8087, X is always 1.0	FPTAN	D9 F2	8087: ${\displaystyle 0\leq \left|st(0)\right|\leq {\frac {\pi }{4}}}$ 80387: ${\displaystyle 0\leq \left|st(0)\right|<2^{63}}$
Two-argument arctangent with quadrant adjustment: [lower-alpha 21] $${\displaystyle st(1)\leftarrow \arctan \left({\frac {st(1)}{st(0)}}\right)}$$ followed by stack pop	FPATAN	D9 F3	8087: ${\displaystyle \left|st(1)\right|\leq \left|st(0)\right|<\infty }$ 80387: no restrictions
Base-2 Logarithm plus 1, with extra precision for st(0) close to 0:$${\displaystyle st(1)\leftarrow st(1)*\log _{2}\left(st(0)+1\right)}$$followed by stack pop	FYL2XP1 [lower-alpha 20]	D9 F9	Intel: ${\displaystyle \left|st(0)\right|<\left(1-{\sqrt {\frac {1}{2}}}\right)}$ AMD: ${\displaystyle \left({\sqrt {\frac {1}{2}}}-1\right)<st(0)<\left({\sqrt {2}}-1\right)}$
Other x87 Instructions
No operation [lower-alpha 22]	FNOP	D9 D0
Decrement x87 FPU Register Stack Pointer	FDECSTP	D9 F6
Increment x87 FPU Register Stack Pointer	FINCSTP	D9 F7
Free x87 FPU Register	FFREE st(i)	DD C0+i
Check and handle pending unmasked x87 FPU exceptions	WAIT, FWAIT	9B
Floating-point store and pop, without stack underflow exception	FSTPNCE st(i)	D9 D8+i [lower-alpha 7]
Free x87 register, then stack pop	FFREEP st(i)	DF C0+i [lower-alpha 7]

1. x87 coprocessors (other than the 8087) handle exceptions in a fairly unusual way. When an x87 instruction generates an unmasked arithmetic exception, it will still complete without causing a CPU fault – instead of causing a fault, it will record within the coprocessor information needed to handle the exception (instruction pointer, opcode, data pointer if the instruction had a memory operand) and set FPU status-word flag to indicate that a pending exception is present. This pending exception will then cause a CPU fault when the next x87, MMX or WAIT instruction is executed.
   The exception to this is x87's "Non-Waiting" instructions, which will execute without causing such a fault even if a pending exception is present (with some caveats, see application note AP-578 ^[119] ). These instructions are mostly control instructions that can inspect and/or modify the pending-exception state of the x87 FPU.
2. For each non-waiting x87 instruction whose mnemonic begins with FN, there exists a pseudo-instruction that has the same mnemonic except without the N. These pseudo-instructions consist of a WAIT instruction (opcode 9B) followed by the corresponding non-waiting x87 instruction. For example:
   • FNCLEX is an instruction with the opcode DB E2. The corresponding pseudo-instruction FCLEX is then encoded as 9B DB E2.
   • FNSAVE ES:[BX+6] is an instruction with the opcode 26 DD 77 06. The corresponding pseudo-instruction FSAVE ES:[BX+6] is then encoded as 9B 26 DD 77 06
   These pseudo-instructions are commonly recognized by x86 assemblers and disassemblers and treated as single instructions, even though all x86 CPUs with x87 coprocessors execute them as a sequence of two instructions.
3. On 80387 and later x87 FPUs, FLDENV, F(N)STENV, FRSTOR and F(N)SAVE exist in 16-bit and 32-bit variants. The 16-bit variants will load/store a 14-byte floating-point environment data structure to/from memory – the 32-bit variants will load/store a 28-byte data structure instead. (F(N)SAVE/FRSTOR will additionally load/store an additional 80 bytes of FPU data register content after the FPU environment, for a total of 94 or 108 bytes). The choice between the 16-bit and 32-bit variants is based on the CS.D bit and the presence of the 66h instruction prefix. On 8087 and 80287, only the 16-bit variants are available.
   64-bit variants of these instructions do not exist – using REX.W under x86-64 will cause the 32-bit variants to be used. Since these can only load/store the bottom 32 bits of FIP and FDP, it is recommended to use FXSAVE64/FXRSTOR64 instead if 64-bit operation is desired.
4. In the case of an x87 instruction producing an unmasked FPU exception, the 8087 FPU will signal an IRQ some indeterminate time after the instruction was issued. This may not always be possible to handle, ^[120] and so the FPU offers the F(N)DISI and F(N)ENI instructions to set/clear the Interrupt Mask bit (bit 7) of the x87 Control Word, ^[121] to control the interrupt.
   Later x87 FPUs, from 80287 onwards, changed the FPU exception mechanism to instead produce a CPU exception on the next x87 instruction. This made the Interrupt Mask bit unnecessary, so it was removed. ^[122] In later Intel x87 FPUs, the F(N)ENI and F(N)DISI instructions were kept for backwards compatibility, executing as NOPs that do not modify any x87 state.
5. FST/FSTP with an 80-bit destination (m80 or st(i)) and an sNaN source value will produce exceptions on AMD but not Intel FPUs.
6. FSTP ST(0) is a commonly used idiom for popping a single register off the x87 register stack.
7. Intel x87 alias opcode. Use of this opcode is not recommended.
   On the Intel 8087 coprocessor, several reserved opcodes would perform operations behaving similarly to existing defined x87 instructions. These opcodes were documented for the 8087 ^[123] and 80287, ^[124] but then omitted from later manuals until the October 2017 update of the Intel SDM. ^[125]
   They are present on all known Intel x87 FPUs but unavailable on some older non-Intel FPUs, such as AMD Geode GX/LX, DM&P Vortex86 ^[126] and NexGen 586PF. ^[127]
8. On the 8087 and 80287, FBSTP and the load-constant instructions always use the round-to-nearest rounding mode. On the 80387 and later x87 FPUs, these instructions will use the rounding mode specified in the x87 RC register.
9. For the FADDP, FSUBP, FSUBRP, FMULP, FDIVP, FDIVRP, FCOM, FCOMP and FXCH instructions, x86 assemblers/disassemblers may recognize variants of the instructions with no arguments. Such variants are equivalent to variants using st(1) as their first argument.
10. On Intel Pentium and later processors, FXCH is implemented as a register renaming rather than a true data move. This has no semantic effect, but enables zero-cycle-latency operation. It also allows the instruction to break data dependencies for the x87 top-of-stack value, improving attainable performance for code optimized for these processors.
11. The result of executing the FBLD instruction on non-BCD data is undefined.
12. On early Intel Pentium processors, floating-point divide was subject to the Pentium FDIV bug. This also affected instructions that perform divide as part of their operations, such as FPREM and FPATAN. ^[128]
13. The FXAM instruction will set C0, C2 and C3 based on value type in st(0) as follows:

    C3	C2	C0	Classification
    0	0	0	Unsupported (unnormal or pseudo-NaN)
    0	0	1	NaN
    0	1	0	Normal finite number
    0	1	1	Infinity
    1	0	0	Zero
    1	0	1	Empty
    1	1	0	Denormal number
    1	1	1	Empty (may occur on 8087/80287 only)

    C1 is set to the sign-bit of st(0), regardless of whether st(0) is Empty or not.
14. For FXTRACT, if st(0) is zero or ±∞, then M is set equal to st(0). If st(0) is zero, E is set to 0 on 8087/80287 but -∞ on 80387 and later. If st(0) is ±∞, then E is set to +∞.
15. For FPREM, if the quotient Q is larger than ${\displaystyle 2^{63}}$, then the remainder calculation may have been done only partially – in this case, the FPREM instruction will need to be run again in order to complete the remainder calculation. This is indicated by the instruction setting C2 to 1.
    If the instruction did complete the remainder calculation, it will set C2 to 0 and set the three bits {C0,C3,C1} to the bottom three bits of the quotient Q.
    On 80387 and later, if the instruction didn't complete the remainder calculation, then the computed remainder Q used for argument reduction will have been rounded to a multiple of 8 (or larger power-of-2), so that the bottom 3 bits of the quotient can still be correctly retrieved in a later pass that does complete the remainder calculation.
16. The remainder computation done by the FPREM instruction is always exact with no roundoff errors.
17. For the FSCALE instruction on 8087 and 80287, st(1) is required to be in the range ${\displaystyle -2^{15}\leq st(1)<2^{15}}$. Also, its absolute value must be either 0 or at least 1. If these requirements are not satisfied, the result is undefined.
    These restrictions were removed in the 80387.
18. For FSCALE, rounding is only applied in the case of overflow, underflow or subnormal result.
19. The x87 transcendental instructions do not obey PC or RC, but instead compute full 80-bit results. These results are not necessarily correctly rounded (see Table-maker's dilemma) – they may have an error of up to ±1 ulp on Pentium or later, or up to ±1.5 ulps on earlier x87 coprocessors.
20. For the FYL2X and FYL2XP1 instructions, the maximum error bound of ±1 ulp only holds for st(1)=1.0 – for other values of st(1), the error bound is increased to ±1.35 ulps.
21. For FPATAN, the following adjustments are done as compared to just computing a one-argument arctangent of the ratio ${\displaystyle {\frac {st(1)}{st(0)}}}$:
    • If both st(0) and st(1) are ±∞, then the arctangent is computed as if each of st(0) and st(1) had been replaced with ±1 of the same sign. This produces a result that is an odd multiple of ${\displaystyle {\frac {\pi }{4}}}$.
    • If both st(0) and st(1) are ±0, then the arctangent is computed as if st(0) but not st(1) had been replaced with ±1 of the same sign, producing a result of ±0 or ${\displaystyle \pm \pi }$.
    • If st(0) is negative (has sign bit set), then an addend of ${\displaystyle \pm \pi }$ with the same sign as st(1) is added to the result.
22. While FNOP is a no-op in the sense that will leave the x87 FPU register stack unmodified, it may still modify FIP and CC, and it may fault if a pending x87 FPU exception is present.

x87 instructions added in later processors

Instruction description	Mnemonic	Opcode	Additional items
x87 Non-Waiting Control Instructions added in 80287			Waiting mnemonic
Notify FPU of entry into Protected Mode [lower-alpha 1]	FNSETPM	DB E4	FSETPM
Store x87 Status Word to AX	FNSTSW AX	DF E0	FSTSW AX
x87 Instructions added in 80387 [lower-alpha 2]			Source operand range restriction
Floating-point unordered compare. Similar to the regular floating-point compare instruction FCOM, except will not produce an exception in response to any qNaN operands.	FUCOM st(i) [lower-alpha 3]	DD E0+i	no restrictions
Floating-point unordered compare and pop	FUCOMP st(i) [lower-alpha 3]	DD E8+i
Floating-point unordered compare to st(1), then pop twice	FUCOMPP	DA E9
IEEE 754 compliant floating-point partial remainder. [lower-alpha 4]	FPREM1	D9 F5
Floating-point sine and cosine. Computes two values ${\displaystyle S=\sin \left(k*st(0)\right)}$ and ${\displaystyle C=\cos \left(k*st(0)\right)}$  [lower-alpha 5] Top-of-stack st(0) is replaced with S, after which C is pushed onto the stack.	FSINCOS	D9 FB	${\displaystyle \left|st(0)\right|<2^{63}}$
Floating-point sine. [lower-alpha 5] $${\displaystyle st(0)\leftarrow \sin \left(k*st(0)\right)}$$	FSIN	D9 FE
Floating-point cosine. [lower-alpha 5] $${\displaystyle st(0)\leftarrow \cos \left(k*st(0)\right)}$$	FCOS	D9 FF
x87 Instructions added in Pentium Pro			Condition for conditional moves
Floating-point conditional move to st(0) based on EFLAGS	FCMOVB st(0),st(i)	DA C0+i	below (CF=1)
	FCMOVE st(0),st(i)	DA C8+i	equal (ZF=1)
	FCMOVBE st(0),st(i)	DA D0+i	below or equal (CF=1 or ZF=1)
	FCMOVU st(0),st(i)	DA D8+i	unordered (PF=1)
	FCMOVNB st(0),st(i)	DB C0+i	not below (CF=0)
	FCMOVNE st(0),st(i)	DB C8+i	not equal (ZF=0)
	FCMOVNBE st(0),st(i)	DB D0+i	not below or equal (CF=0 and ZF=0)
	FCMOVNU st(0),st(i)	DB D8+i	not unordered (PF=0)
Floating-point compare and set EFLAGS. Differs from the older FCOM floating-point compare instruction in that it puts its result in the integer EFLAGS register rather than the x87 CC register. [lower-alpha 6]	FCOMI st(0),st(i)	DB F0+i
Floating-point compare and set EFLAGS, then pop	FCOMIP st(0),st(i)	DF F0+i
Floating-point unordered compare and set EFLAGS	FUCOMI st(0),st(i)	DB E8+i
Floating-point unordered compare and set EFLAGS, then pop	FUCOMIP st(0),st(i)	DF E8+i
x87 Non-Waiting Instructions added in Pentium II, AMD K7 and SSE [lower-alpha 7]			64-bit mnemonic (REX.W prefix)
Save x87, MMX and SSE state to 512-byte data structure [lower-alpha 8] [lower-alpha 9] [lower-alpha 10]	FXSAVE m512byte	NP 0F AE /0	FXSAVE64 m512byte
Restore x87, MMX and SSE state from 512-byte data structure [lower-alpha 8] [lower-alpha 9]	FXRSTOR m512byte	NP 0F AE /1	FXRSTOR64 m512byte
x87 Instructions added as part of SSE3
Floating-point store integer and pop, with round-to-zero	FISTTP m16	DF /1
	FISTTP m32	DB /1
	FISTTP m64	DD /1

1. The x87 FPU needs to know whether it is operating in Real Mode or Protected Mode because the floating-point environment accessed by the F(N)SAVE, FRSTOR, FLDENV and F(N)STENV instructions has different formats in Real Mode and Protected Mode. On 80287, the F(N)SETPM instruction is required to communicate the real-to-protected mode transition to the FPU. On 80387 and later x87 FPUs, real↔protected mode transitions are communicated automatically to the FPU without the need for any dedicated instructions – therefore, on these FPUs, FNSETPM executes as a NOP that does not modify any FPU state.
2. Not including discontinued instructions specific to particular 80387-compatible FPU models.
3. For the FUCOM and FUCOMP instructions, x86 assemblers/disassemblers may recognize variants of the instructions with no arguments. Such variants are equivalent to variants using st(1) as their first argument.
4. The 80387 FPREM1 instruction differs from the older FPREM (D9 F8) instruction in that the quotient Q is rounded to integer with round-to-nearest-even rounding rather than the round-to-zero rounding used by FPREM. Like FPREM, FPREM1 always computes an exact result with no roundoff errors. Like FPREM, it may also perform a partial computation if the quotient is too large, in which case it must be run again.
5. Due to the x87 FPU performing argument reduction for sin/cos with only about 68 bits of precision, the value of k used in the calculation of FSIN, FCOS and FSINCOS is not precisely 1.0, but instead given by ^{[129] [130]} $${\displaystyle k{=}{\frac {2^{66}*\pi }{\lfloor 2^{66}*\pi \rfloor }}\approx 1.0000000000000000000012874}$$This argument reduction inaccuracy also affects the FPTAN instruction.
6. The FCOMI, FCOMIP, FUCOMI and FUCOMIP instructions write their results to the ZF, CF and PF bits of the EFLAGS register. On Intel but not AMD processors, the SF, AF and OF bits of EFLAGS are also zeroed out by these instructions.
7. The FXSAVE and FXRSTOR instructions were added in the "Deschutes" revision of Pentium II, and are not present in earlier "Klamath" revision.
   They are also present in AMD K7.
   They are also considered an integral part of SSE and are therefore present in all processors with SSE.
8. The FXSAVE and FXRSTOR instructions will save/restore SSE state only on processors that support SSE. Otherwise, they will only save/restore x87 and MMX state.
   The x87 section of the state saved/restored by FXSAVE/FXRSTOR has a completely different layout than the data structure of the older F(N)SAVE/FRSTOR instructions, enabling faster save/restore by avoiding misaligned loads and stores.
9. When floating-point emulation is enabled with CR0.EM=1, FXSAVE(64) and FXRSTOR(64) are considered to be x87 instructions and will accordingly produce an #NM (device-not-available) exception. Other than WAIT, these are the only opcodes outside the D8..DF ESC opcode space that exhibit this behavior. (All opcodes in D8..DF will produce #NM if CR0.EM=1, even for undefined opcodes that would produce #UD otherwise.)
10. Unlike the older F(N)SAVE instruction, FXSAVE will not initialize the FPU after saving its state to memory, but instead leave the x87 coprocessor state unmodified.

SIMD instructions

Main article: x86 SIMD instruction listings

Cryptographic instructions

Main article: List of x86 cryptographic instructions

Virtualization instructions

Main article: List of x86 virtualization instructions

Other instructions

See also: List of discontinued x86 instructions

x86 also includes discontinued instruction sets which are no longer supported by Intel and AMD, and undocumented instructions which execute but are not officially documented.

Undocumented x86 instructions

The x86 CPUs contain undocumented instructions which are implemented on the chips but not listed in some official documents. They can be found in various sources across the Internet, such as Ralf Brown's Interrupt List and at sandpile.org

Some of these instructions are widely available across many/most x86 CPUs, while others are specific to a narrow range of CPUs.

Undocumented instructions that are widely available across many x86 CPUs include

Mnemonics	Opcodes	Description	Status
AAM imm8	D4 ib	ASCII-Adjust-after-Multiply. On the 8086, documented for imm8=0Ah only, which is used to convert a binary multiplication result to BCD. The actual operation is AH ← AL/imm8; AL ← AL mod imm8 for any imm8 value (except zero, which produces a divide-by-zero exception). [131]	Available beginning with 8086, documented for imm8 values other than 0Ah since Pentium (earlier documentation lists no arguments).
AAD imm8	D5 ib	ASCII-Adjust-Before-Division. On the 8086, documented for imm8=0Ah only, which is used to convert a BCD value to binary for a following division instruction. The actual operation is AL ← (AL+(AH*imm8)) & 0FFh; AH ← 0 for any imm8 value.
SALC, SETALC	D6	Set AL depending on the value of the Carry Flag (a 1-byte alternative of SBB AL, AL)	Available beginning with 8086, but only documented since Pentium Pro.
ICEBP, INT1	F1	Single byte single-step exception / Invoke ICE	Available beginning with 80386, documented (as INT1) since Pentium Pro. Executes as undocumented instruction prefix on 8086 and 80286. [132]
TEST r/m8,imm8	F6 /1 ib	Undocumented variants of the TEST instruction. [133] Performs the same operation as the documented F6 /0 and F7 /0 variants, respectively.	Available since the 8086. Unavailable on some 80486 steppings. [134] [135]
TEST r/m16,imm16, TEST r/m32,imm32	F7 /1 iw, F7 /1 id
SHL, SAL	(D0..D3) /6, (C0..C1) /6 ib	Undocumented variants of the SHL instruction. [133] Performs the same operation as the documented (D0..D3) /4 and (C0..C1) /4 ib variants, respectively.	Available since the 80186 (performs different operation on the 8086) [136]
(multiple)	82 /(0..7) ib	Alias of opcode 80h, which provides variants of 8-bit integer instructions (ADD, OR, ADC, SBB, AND, SUB, XOR, CMP) with an 8-bit immediate argument. [137]	Available since the 8086. [137] Explicitly unavailable in 64-bit mode but kept and reserved for compatibility. [138]
OR/AND/XOR r/m16,imm8	83 /(1,4,6) ib	16-bit OR/AND/XOR with a sign-extended 8-bit immediate.	Available on 8086, but only documented from 80386 onwards. [139] [140]
REPNZ MOVS	F2 (A4..A5)	The behavior of the F2 prefix (REPNZ, REPNE) when used with string instructions other than CMPS/SCAS is officially undefined, but there exists commercial software (e.g. the version of FDISK distributed with MS-DOS versions 3.30 to 6.22 [141] ) that rely on it to behave in the same way as the documented F3 (REP) prefix.	Available since the 8086.
REPNZ STOS	F2 (AA..AB)
REP RET	F3 C3	The use of the REP prefix with the RET instruction is not listed as supported in either the Intel SDM or the AMD APM. However, AMD's optimization guide for the AMD-K8 describes the F3 C3 encoding as a way to encode a two-byte RET instruction – this is the recommended workaround for an issue in the AMD-K8's branch predictor that can cause branch prediction to fail for some 1-byte RET instructions. [142] At least some versions of gcc are known to use this encoding. [143]	Executes as RET on all known x86 CPUs.
NOP	67 90	NOP with address-size override prefix. The use of the 67h prefix for instructions without memory operands is listed by the Intel SDM (vol 2, section 2.1.1) as "reserved", but it is used in Microsoft Windows 95 as a workaround for a bug in the B1 stepping of Intel 80386. [144] [145]	Executes as NOP on 80386 and later.
NOP r/m	0F 1F /0	Official long NOP. Introduced in the Pentium Pro in 1995, but remained undocumented until March 2006. [57] [146] [147]	Available on Pentium Pro and AMD K7 [148] and later. Unavailable on AMD K6, AMD Geode LX, VIA Nehemiah. [149]
NOP r/m	0F 0D /r	Reserved-NOP. Introduced in 65 nm Pentium 4. Intel documentation lists this opcode as NOP in opcode tables but not instruction listings since June 2005. [150] [151] From Broadwell onwards, 0F 0D /1 has been documented as PREFETCHW, while 0F 0D /0 and /2../7 have been reported to exhibit undocumented prefetch functionality. [105] On AMD CPUs, 0F 0D /r with a memory argument is documented as PREFETCH/PREFETCHW since K6-2 – originally as part of 3Dnow!, but has been kept in later AMD CPUs even after the rest of 3Dnow! was dropped.	Available on Intel CPUs since 65 nmPentium 4.
UD1	0F B9 /r	Intentionally undefined instructions, but unlike UD2 (0F 0B) these instructions were left unpublished until December 2016. [152] [67] Microsoft Windows 95 Setup is known to depend on 0F FF being invalid [153] [154] – it is used as a self check to test that its #UD exception handler is working properly. Other invalid opcodes that are being relied on by commercial software to produce #UD exceptions include FF FF (DIF-2, [155] LaserLok [156] ) and C4 C4 ("BOP" [157] [158] ), however as of January 2022 they are not published as intentionally invalid opcodes.	All of these opcodes produce #UD exceptions on 80186 and later (except on NEC V20/V30, which assign at least 0F FF to the NEC-specific BRKEM instruction.)
UD0	0F FF

Undocumented instructions that appear only in a limited subset of x86 CPUs include

Mnemonics	Opcodes	Description	Status
REP MUL	F3 F6 /4, F3 F7 /4	On 8086/8088, a REP or REPNZ prefix on a MUL or IMUL instruction causes the result to be negated. This is due to the microcode using the “REP prefix present” bit to store the sign of the result.	8086/8088 only. [159]
REP IMUL	F3 F6 /5, F3 F7 /5
REP IDIV	F3 F6 /7, F3 F7 /7	On 8086/8088, a REP or REPNZ prefix on an IDIV (but not DIV) instruction causes the quotient to be negated. This is due to the microcode using the “REP prefix present” bit to store the sign of the quotient.	8086/8088 only. [159]
SAVEALL, STOREALL	(F1) 0F 04	Exact purpose unknown, causes CPU hang (HCF). The only way out is CPU reset. [160] In some implementations, emulated through BIOS as a halting sequence. [161] In a forum post at the Vintage Computing Federation, this instruction (with F1 prefix) is explained as SAVEALL. It interacts with ICE mode.	Only available on 80286.
LOADALL	0F 05	Loads All Registers from Memory Address 0x000800H	Only available on 80286. Opcode reused for SYSCALL in AMD K6 and later CPUs.
LOADALLD	0F 07	Loads All Registers from Memory Address ES:EDI	Only available on 80386. Opcode reused for SYSRET in AMD K6 and later CPUs.
CL1INVMB	0F 0A [162]	On the Intel SCC (Single-chip Cloud Computer), invalidate all message buffers. The mnemonic and operation of the instruction, but not its opcode, are described in Intel's SCC architecture specification. [163]	Available on the SCC only.
PATCH2	0F 0E	On AMD K6 and later maps to FEMMS operation (fast clear of MMX state) but on Intel identified as uarch data read on Intel [164]	Only available in Red unlock state (0F 0F too)
PATCH3	0F 0F	Write uarch	Can change RAM part of microcode on Intel
UMOV r,r/m, UMOV r/m,r	0F (10..13) /r	Moves data to/from user memory when operating in ICE HALT mode. [165] Acts as regular MOV otherwise.	Available on some 386 and 486 processors only. Opcodes reused for SSE instructions in later CPUs.
NXOP	0F 55	NexGen hypercode interface. [166]	Available on NexGen Nx586 only.
(multiple)	0F (E0..FB) [167]	NexGen Nx586 "hyper mode" instructions. The NexGen Nx586 CPU uses "hyper code" [168] (x86 code sequences unpacked at boot time and only accessible in a special "hyper mode" operation mode, similar to DEC Alpha's PALcode and Intel's XuCode [169] ) for many complicated operations that are implemented with microcode in most other x86 CPUs. The Nx586 provides a large number of undocumented instructions to assist hyper mode operation.	Available in Nx586 hyper mode only.
PSWAPW mm,mm/m64	0F 0F /r BB	Undocumented AMD 3DNow! instruction on K6-2 and K6-3. Swaps 16-bit words within 64-bit MMX register. [170] [171] Instruction known to be recognized by MASM 6.13 and 6.14.	Available on K6-2 and K6-3 only. Opcode reused for documented PSWAPD instruction from AMD K7 onwards.
Un­known mnemonic	64 D6	Using the 64 (FS: segment) prefix with the undocumented D6 (SALC/SETALC) instruction will, on UMC CPUs only, cause EAX to be set to 0xAB6B1B07. [172] [173]	Available on the UMC Green CPU only. Executes as SALC on non-UMC CPUs.
FS: Jcc	64 (70..7F) rel8, 64 0F (80..8F) rel16/32	On Intel NetBurst (Pentium 4) CPUs, the 64h (FS: segment) instruction prefix will, when used with conditional branch instructions, act as a branch hint to indicate that the branch will be alternating between taken and not-taken. [174] Unlike other NetBurst branch hints (CS: and DS: segment prefixes), this hint is not documented.	Available on NetBurst CPUs only. Segment prefixes on conditional branches are accepted but ignored by non-NetBurst CPUs.
JMPAI	0F 3F	Jump and execute instructions in the undocumented Alternate Instruction Set.	Only available on some x86 processors made by VIA Technologies.
(FMA4)	VEX.66.0F38 (5C..5F,68..6F,78..7F) /r imm8	On AMD Zen1, FMA4 instructions are present but undocumented (missing CPUID flag). The reason for leaving the feature undocumented may or may not have been due to a buggy implementation. [175]	Removed from Zen2 onwards.
(unknown, multiple)	0F 0F /r ??	The whitepapers for SandSifter [176] and UISFuzz [177] report the detection of large numbers of undocumented instructions in the 3DNow! opcode range on several different AMD CPUs (at least Geode NX and C-50). Their operation is not known. On at least AMD K6-2, all of the unassigned 3DNow! opcodes (other than the undocumented PF2IW, PI2FW and PSWAPW instructions) are reported to execute as equivalents of POR (MMX bitwise-OR instruction). [171]	Present on some AMD CPUs with 3DNow!.
MOVDB, GP2MEM	Un­known	Microprocessor Report's article "MediaGX Targets Low-Cost PCs" from 1997, covering the introduction of the Cyrix MediaGX processor, lists several new instructions that are said to have been added to this processor in order to support its new "Virtual System Architecture" features, including MOVDB and GP2MEM – and also mentions that Cyrix did not intend to publish specifications for these instructions. [178]	Unknown. No specification known to have been published.
REP XSHA512	F3 0F A6 E0	Perform SHA-512 hashing. Supported by OpenSSL [179] as part of its VIA PadLock support, and listed in a Zhaoxin-supplied Linux kernel patch, [180] but not documented by the VIA PadLock Programming Guide.	Only available on some x86 processors made by VIA Technologies and Zhaoxin.
REP XMODEXP	F3 0F A6 F8	Instructions to perform modular exponentiation and random number generation, respectively. Listed in a VIA-supplied patch to add support for VIA Nano-specific PadLock instructions to OpenSSL, [181] but not documented by the VIA PadLock Programming Guide.
XRNG2	F3 0F A7 F8
Un­known mnemonic	0F A7 (C1..C7)	Detected by CPU fuzzing tools such as SandSifter [176] and UISFuzz [177] as executing without causing #UD on several different VIA and Zhaoxin CPUs. Unknown operation, may be related to the documented XSTORE (0F A7 C0) instruction.
Un­known mnemonic	F2 0F A6 C0	Zhaoxin SM2 instruction. CPUID flags listed in a Linux kernel patch for OpenEuler, [182] description and opcode (but no instruction mnemonic) provided in a Zhaoxin patent application [183] and a Zhaoxin-provided Linux kernel patch. [184]	Present in Zhaoxin KX-6000G. [185]
ZXPAUSE	F2 0F A6 D0	Pause the processor until the Time Stamp Counter reaches or exceeds the value specified in EDX:EAX. Low-power processor C-state can be requested in ECX. Listed in OpenEuler kernel patch. [186]	Present in Zhaoxin KX-7000.
MONTMUL2	Un­known	Zhaoxin RSA/"xmodx" instructions. Mnemonics and CPUID flags are listed in a Linux kernel patch for OpenEuler, [182] but opcodes and instruction descriptions are not available.	Unknown. Some Zhaoxin CPUs [185] have the CPUID flags for these instructions set.

Undocumented x87 instructions

Mnemonics	Opcodes	Description	Status
FENI, FENI8087_NOP	DB E0	FPU Enable Interrupts (8087)	Documented for the Intel 80287. [124] Present on all Intel x87 FPUs from 80287 onwards. For FPUs other than the ones where they were introduced on (8087 for FENI/FDISI and 80287 for FSETPM), they act as NOPs. These instructions and their operation on modern CPUs are commonly mentioned in later Intel documentation, but with opcodes omitted and opcode table entries left blank (e.g. Intel SDM 325462-077, April 2022 mentions them twice without opcodes). The opcodes are, however, recognized by Intel XED. [187]
FDISI, FDISI8087_NOP	DB E1	FPU Disable Interrupts (8087)
FSETPM, FSETPM287_NOP	DB E4	FPU Set Protected Mode (80287)
(no mnemonic)	D9 D7,  D9 E2, D9 E7,  DD FC, DE D8,  DE DA, DE DC,  DE DD, DE DE,  DF FC	"Reserved by Cyrix" opcodes	These opcodes are listed as reserved opcodes that will produce "unpredictable results" without generating exceptions on at least Cyrix 6x86, [188] 6x86MX, MII, MediaGX, and AMD Geode GX/LX. [189] (The documentation for these CPUs all list the same ten opcodes.) Their actual operation is not known, nor is it known whether their operation is the same on all of these CPUs.

See also

• CLMUL
• RDRAND
• Advanced Vector Extensions 2
• AVX-512
• x86 Bit manipulation instruction set
• CPUID
• List of discontinued x86 instructions

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• Intel Corporation (April 2022). "Intel 64 and IA-32 Architectures Software Developer's Manual, Combined Volumes: 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D and 4". Intel. Retrieved 21 June 2022.

External links

• Free IA-32 and x86-64 documentation, provided by Intel
• AMD64 Architecture Programmer's Manual, Volumes 1-5, provided by AMD
• x86 Opcode and Instruction Reference
• x86 and amd64 instruction reference
• Instruction tables: Lists of instruction latencies, throughputs and micro-operation breakdowns for Intel, AMD and VIA CPUs
• Netwide Assembler Instruction List (from Netwide Assembler)