Fabrication process
Zen 5 was designed with both 4nm and 3nm processes in mind. This acted as an insurance policy for AMD in the event that TSMC's mass production of its N3 nodes were to face delays, significant wafer defect issues or capacity issues. One industry analyst estimated early N3 wafer yields to be at 55% while others estimated yields to be similar to those of N5 at between 60-80%. [13] [14] Additionally, Apple, as TSMC's largest customer, is given priority access to the latest process nodes. In 2022, Apple was responsible for 23% of TSMC's $72 billion in total revenue. [15] After N3 began ramping at the end of 2022, Apple bought up the entirety of TSMC's early N3B wafer production capacity to fabricate their A17 and M3 SoCs. [16] Zen 5 desktop and server processors continue to use the N6 node for the I/O die fabrication. [17]
Zen 5 Core Complex Dies (CCDs) are fabricated on TSMC's N4X node which is intended to accommodate higher frequencies for high-performance computing (HPC) applications. [18] Zen 4-based mobile processors were fabricated on the N4P node which is targeted more towards power efficiency. N4X maintains IP compatibility with N4P and offers a 6% frequency gain over N4P at the same power but comes with the trade-off of moderate leakage. [19] Compared to the N5 node used to produce Zen 4 CCDs, N4X can enable up to 15% higher frequencies while running at 1.2V. [20]
The Zen 5 CCD, codenamed "Eldora", [1] has a die size of 70.6mm2, a 0.5% reduction in area from Zen 4's 71mm2 CCD while achieving a 28% increase in transistor density due to the N4X process node. [21] Zen 5's CCD contains 8.315 billion transistors compared to the Zen 4 CCD's 6.5 billion transistors. [22] The size of an individual Zen 5 core is actually larger than a Zen 4 core but the CCD has been reduced via shrinking the L3 cache. The monolithic die used by "Strix Point" mobile processors, fabricated on TSMC's lower power N4P node, measures 232.5mm2 in area. [21]
Cache
L1
The wider front end in the Zen 5 architecture necessitates larger caches and higher memory bandwidth in order to keep the cores fed with data. The L1 cache per core is increased from 64 KB to 80 KB per core. The L1 instruction cache remains the same at 32 KB but the L1 data cache is increased from 32 KB to 48 KB per core. Furthermore, the bandwidth of the L1 data cache for 512-bit floating point unit pipes has also been doubled. The L1 data cache's associativity has increased from 8-way to 12-way in order to accommodate its larger size.
L2
The L2 cache remains at 1 MB but its associativity has increased from 8-way to 16-way. Zen 5 also has a doubled L2 cache bandwidth of 64 bytes per clock.
L3
The L3 cache is filled from L2 cache victims and in-flight misses. Latency for accessing the L3 cache has been reduced by 3.5 cycles. [26] A Zen 5 Core Complex Die (CCD) contains 32 MB of L3 cache shared between the 8 cores. In Zen 5 3D V-Cache CCDs, a piece of silicon containing 64 MB of extra L3 cache is placed under the cores rather than on top like in prior generations for a total of 96 MB. [27] This allows for increased core frequency compared to previous generation 3D V-Cache implementations which were sensitive to higher voltages. The Zen 5-based Ryzen 7 9800X3D has a 500 MHz increased base frequency over the Zen 4-based Ryzen 7 7800X3D and allows overclocking for the first time. [28]
Ryzen AI 300 APUs, codenamed "Strix Point", features 24 MB of total L3 cache which is split into two separate cache arrays. 16 MB of dedicated L3 cache is shared by the 4 Zen 5 cores and 8 MB is shared by the 8 Zen 5c cores. [29] Zen 5c cores are not able to access the 16 MB L3 cache array and vice versa. [30]
| Cache | Zen 4 | Zen 5 |
|---|
L1
Data | Size | 32 KB | 48 KB |
|---|
| Associativity | 8-way | 12-way |
|---|
| Bandwidth | 32B/clk | 64B/clk |
|---|
|
|---|
L1
Instructions | Size | 32 KB | 32 KB |
|---|
| Associativity | 8-way | 8-way |
|---|
| Bandwidth | 64B/clk | 64B/clk |
|---|
|
|---|
| L2 | Size | 1 MB | 1 MB |
|---|
| Associativity | 8-way | 16-way |
|---|
| Bandwidth | 32B/clk | 64B/clk |
|---|
|
|---|
| L3 | Size | 32 MB | 32 MB |
|---|
| Associativity | 16-way | 16-way |
|---|
| Bandwidth | 32B/clk Read
16B/clk Write | 32B/clk Read
16B/clk Write |
|---|
|
