90 nm process

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The 90 nm process refers to the technology used in semiconductor manufacturing to create integrated circuits with a minimum feature size of 90 nanometers. It was an advancement over the previous 130 nm process. Eventually, it was succeeded by smaller process nodes, such as the 65 nm, 45 nm, and 32 nm processes.

Contents

It was commercialized by the 2003–2005 timeframe, by semiconductor companies including Toshiba, Sony, Samsung, IBM, Intel, Fujitsu, TSMC, Elpida, AMD, Infineon, Texas Instruments and Micron Technology.

The origin of the 90 nm value is historical; it reflects a trend of 70% scaling every 2–3 years. The naming is formally determined by the International Technology Roadmap for Semiconductors (ITRS).

The 300 mm wafer size became mainstream at the 90 nm node. The previous wafer size was 200 mm diameter.

The 193  nm wavelength was introduced by many (but not all) companies for lithography of critical layers mainly during the 90 nm node. Yield issues associated with this transition (due to the use of new photoresists) were reflected in the high costs associated with this transition.

Since at least 1997, "process nodes" have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit; [1] neither gate length, metal pitch or gate pitch on a "90nm" device is ninety nanometers. [2] [3] [4] [5]

History

A 90 nm silicon MOSFET was fabricated by Iranian engineer Ghavam Shahidi (later IBM director) with D.A. Antoniadis and H.I. Smith at MIT in 1988. The device was fabricated using X-ray lithography. [6]

Toshiba, Sony and Samsung developed a 90 nm process during 2001–2002, before being introduced in 2002 for Toshiba's eDRAM and Samsung's 2  Gb NAND flash memory. [7] [8] IBM demonstrated a 90 nm silicon-on-insulator (SOI) CMOS process, with development led by Shahidi, in 2002. The same year, Intel demonstrated a 90 nm strained-silicon process. [9] Fujitsu commercially introduced its 90 nm process in 2003 [10] followed by TSMC in 2004. [11]

Gurtej Singh Sandhu of Micron Technology initiated the development of atomic layer deposition high-k films for DRAM memory devices. This helped drive cost-effective implementation of semiconductor memory, starting with 90 nm node DRAM. [12]

Intel's 90nm process has a transistor density of 1.45 million transistors per square milimeter (MTr/mm2). [13]

Example: Elpida 90 nm DDR2 SDRAM process

Elpida Memory's 90 nm DDR2 SDRAM process. [14]

Processors using 90 nm process technology

See also

Related Research Articles

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Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically integrated circuits (ICs) such as computer processors, microcontrollers, and memory chips that are present in everyday electronic devices. It is a multiple-step photolithographic and physio-chemical process during which electronic circuits are gradually created on a wafer, typically made of pure single-crystal semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.

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The 65 nm process is an advanced lithographic node used in volume CMOS (MOSFET) semiconductor fabrication. Printed linewidths can reach as low as 25 nm on a nominally 65 nm process, while the pitch between two lines may be greater than 130 nm.

The 32 nm node is the step following the 45 nm process in CMOS (MOSFET) semiconductor device fabrication. "32-nanometre" refers to the average half-pitch of a memory cell at this technology level. Toshiba produced commercial 32 GiB NAND flash memory chips with the 32 nm process in 2009. Intel and AMD produced commercial microchips using the 32-nanometre process in the early 2010s. IBM and the Common Platform also developed a 32 nm high-κ metal gate process. Intel began selling its first 32 nm processors using the Westmere architecture on 7 January 2010.

The transistor count is the number of transistors in an electronic device. It is the most common measure of integrated circuit complexity. The rate at which MOS transistor counts have increased generally follows Moore's law, which observes that transistor count doubles approximately every two years. However, being directly proportional to the area of a chip, transistor count does not represent how advanced the corresponding manufacturing technology is: a better indication of this is transistor density.

The "22 nm" node is the process step following 32 nm in CMOS MOSFET semiconductor device fabrication. The typical half-pitch for a memory cell using the process is around 22 nm. It was first demonstrated by semiconductor companies for use in RAM memory in 2008. In 2010, Toshiba began shipping 24 nm flash memory chips, and Samsung Electronics began mass-producing 20 nm flash memory chips. The first consumer-level CPU deliveries using a 22 nm process started in April 2012 with the Intel Ivy Bridge processors.

The 130 nanometer process is a level of semiconductor process technology that was reached in the 2000–2001 timeframe by such leading semiconductor companies as Intel, Texas Instruments, IBM, and TSMC.

The 180 nm process is a MOSFET (CMOS) semiconductor process technology that was commercialized around the 1998–2000 timeframe by leading semiconductor companies, starting with TSMC and Fujitsu, then followed by Sony, Toshiba, Intel, AMD, Texas Instruments and IBM.

The "14 nanometer process" refers to a marketing term for the MOSFET technology node that is the successor to the "22 nm" node. The "14 nm" was so named by the International Technology Roadmap for Semiconductors (ITRS). Until about 2011, the node following "22 nm" was expected to be "16 nm". All "14 nm" nodes use FinFET technology, a type of multi-gate MOSFET technology that is a non-planar evolution of planar silicon CMOS technology.

<span class="mw-page-title-main">Multigate device</span> MOS field-effect transistor with more than one gate

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GlobalFoundries Inc. (GF) is a multinational semiconductor contract manufacturing and design company incorporated in the Cayman Islands and headquartered in Malta, New York. Created by the divestiture of the manufacturing arm of AMD, the company was privately owned by Mubadala Investment Company, a sovereign wealth fund of the United Arab Emirates, until an initial public offering (IPO) in October 2021.

Per the International Technology Roadmap for Semiconductors, the 45 nm process is a MOSFET technology node referring to the average half-pitch of a memory cell manufactured at around the 2007–2008 time frame.

In semiconductor manufacturing, the International Roadmap for Devices and Systems defines the "5 nm" process as the MOSFET technology node following the "7 nm" node. In 2020, Samsung and TSMC entered volume production of "5 nm" chips, manufactured for companies including Apple, Marvell, Huawei and Qualcomm.

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In semiconductor manufacturing, the "2 nm process" is the next MOSFET die shrink after the "3 nm" process node.

References

  1. ↑ "No More Nanometers – EEJournal". 23 July 2020.
  2. ↑ Shukla, Priyank. "A Brief History of Process Node Evolution". design-reuse.com. Retrieved 9 July 2019.
  3. ↑ Hruska, Joel. "14nm, 7nm, 5nm: How low can CMOS go? It depends if you ask the engineers or the economists..." ExtremeTech .
  4. ↑ "Exclusive: Is Intel Really Starting To Lose Its Process Lead? 7nm Node Slated For Release in 2022". wccftech.com. 10 September 2016.
  5. ↑ "Life at 10nm. (Or is it 7nm?) And 3nm - Views on Advanced Silicon Platforms". eejournal.com. 12 March 2018.
  6. ↑ Shahidi, Ghavam G.; Antoniadis, D. A.; Smith, H. I. (December 1988). "Reduction of hot-electron-generated substrate current in sub-100-nm channel length Si MOSFET's". IEEE Transactions on Electron Devices. 35 (12): 2430–. Bibcode:1988ITED...35.2430S. doi:10.1109/16.8835.
  7. ↑ "Toshiba and Sony Make Major Advances in Semiconductor Process Technologies". Toshiba . 3 December 2002. Retrieved 26 June 2019.
  8. ↑ "Our Proud Heritage from 2000 to 2009". Samsung Semiconductor . Samsung . Retrieved 25 June 2019.
  9. ↑ "IBM, Intel wrangle at 90 nm". EE Times . 13 December 2002. Retrieved 17 September 2019.
  10. ↑ "65nm CMOS Process Technology" (PDF). Archived from the original (PDF) on 16 May 2020. Retrieved 20 June 2019.
  11. ↑ "90nm Technology". TSMC . Retrieved 30 June 2019.
  12. ↑ "IEEE Andrew S. Grove Award Recipients". IEEE Andrew S. Grove Award . Institute of Electrical and Electronics Engineers . Retrieved 4 July 2019.
  13. ↑ "Intel's 10nm Cannon Lake and Core i3-8121U Deep Dive Review".
  14. ↑ Elpida's presentation at Via Technology Forum 2005 and Elpida 2005 Annual Report
  15. ↑ "EMOTION ENGINE® AND GRAPHICS SYNTHESIZER USED IN THE CORE OF PLAYSTATION® BECOME ONE CHIP" (PDF). Sony. 21 April 2003. Retrieved 26 June 2019.
Preceded by
130 nm 		MOSFET manufacturing processes Succeeded by
65 nm
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