|Computer memory types|
|Early stage NVRAM|
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Embedded DRAM (eDRAM) is dynamic random-access memory (DRAM) integrated on the same die or multi-chip module (MCM)of an application-specific integrated circuit (ASIC) or microprocessor. eDRAM's cost-per-bit is higher when compared to equivalent standalone DRAM chips used as external memory, but the performance advantages of placing eDRAM onto the same chip as the processor outweigh the cost disadvantages in many applications. In performance and size, eDRAM is positioned between level 3 cache and conventional DRAM on the memory bus, and effectively functions as a level 4 cache, though architectural descriptions may not explicitly refer to it in those terms.
Embedding memory on the ASIC or processor allows for much wider buses and higher operation speeds, and due to much higher density of DRAM in comparison to SRAM,[ citation needed ] larger amounts of memory can be installed on smaller chips if eDRAM is used instead of eSRAM. eDRAM requires additional fab process steps compared with embedded SRAM, which raises cost, but the 3× area savings of eDRAM memory offsets the process cost when a significant amount of memory is used in the design.
eDRAM memories, like all DRAM memories, require periodic refreshing of the memory cells, which adds complexity. However, if the memory refresh controller is embedded along with the eDRAM memory, the remainder of the ASIC can treat the memory like a simple SRAM type such as in 1T-SRAM. It is also possible to use architectural techniques to mitigate the refresh overhead in eDRAM caches.
eDRAM is used in various products, including IBM's POWER7 processor, GB of eDRAM when 5 such add-on chips/drawers are used but all other levels from L1 up also use eDRAM, for a total of 6.4 GB of eDRAM). Intel's Haswell CPUs with GT3e integrated graphics, many game consoles and other devices, such as Sony's PlayStation 2, Sony's PlayStation Portable, Nintendo's GameCube, Nintendo's Wii, Nintendo's Wii U, Apple Inc.'s iPhone, Microsoft's Zune HD, and Microsoft's Xbox 360 also use eDRAM.and IBM's z15 mainframe processor (mainframes built which use up to 4.69
|Product name||Amount of|
|IBM z15||256+ MB|
|IBM's System Controller (SC) SCM, with L4 cache for the z15||960 MB|
|Intel Haswell, Iris Pro Graphics 5200 (GT3e)||128 MB|
|Intel Broadwell, Iris Pro Graphics 6200 (GT3e)||128 MB|
|Intel Skylake, Iris Graphics 540 and 550 (GT3e)||MB64|
|Intel Skylake, Iris Pro Graphics 580 (GT4e)||MB64 or 128|
|Intel Coffee Lake, Iris Plus Graphics 655 (GT3e)||128 MB|
Certain software utilities can model eDRAM caches.
Static random-access memory is a type of semiconductor random-access memory (RAM) that uses bistable latching circuitry (flip-flop) to store each bit. SRAM exhibits data remanence, but it is still volatile in the conventional sense that data is eventually lost when the memory is not powered.
Dynamic random-access memory (DRAM) is a type of random access semiconductor memory that stores each bit of data in a memory cell consisting of a tiny capacitor and a transistor, both typically based on metal-oxide-semiconductor (MOS) technology. The capacitor can either be charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1. The electric charge on the capacitors slowly leaks off, so without intervention the data on the chip would soon be lost. To prevent this, DRAM requires an external memory refresh circuit which periodically rewrites the data in the capacitors, restoring them to their original charge. This refresh process is the defining characteristic of dynamic random-access memory, in contrast to static random-access memory (SRAM) which does not require data to be refreshed. Unlike flash memory, DRAM is volatile memory, since it loses its data quickly when power is removed. However, DRAM does exhibit limited data remanence.
Xeon is a brand of x86 microprocessors designed, manufactured, and marketed by Intel, targeted at the non-consumer workstation, server, and embedded system markets. It was introduced in June 1998. Xeon processors are based on the same architecture as regular desktop-grade CPUs, but have some advanced features such as support for ECC memory, higher core counts, support for larger amounts of RAM, larger cache memory and extra provision for enterprise-grade reliability, availability and serviceability (RAS) features responsible for handling hardware exceptions through the Machine Check Architecture. They are often capable of safely continuing execution where a normal processor cannot due to these extra RAS features, depending on the type and severity of the machine-check exception (MCE). Some also support multi-socket systems with two, four, or eight sockets through use of the Quick Path Interconnect (QPI) bus.
A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, which stores copies of the data from frequently used main memory locations. Most CPUs have different independent caches, including instruction and data caches, where the data cache is usually organized as a hierarchy of more cache levels.
Semiconductor memory is a digital electronic semiconductor device used for digital data storage, such as computer memory. It typically refers to MOS memory, where data is stored within metal–oxide–semiconductor (MOS) memory cells on a silicon integrated circuit memory chip. There are numerous different types using different semiconductor technologies. The two main types of random-access memory (RAM) are static RAM (SRAM), which uses several transistors per memory cell, and dynamic RAM (DRAM), which uses a single transistor and MOS capacitor per cell. Non-volatile memory uses floating-gate memory cells, which consist of a single transistor per cell.
POWER7 is a family of superscalar symmetric multiprocessors based on the Power ISA 2.06 instruction set architecture released in 2010 that succeeded the POWER6. POWER7 was developed by IBM at several sites including IBM's Rochester, MN; Austin, TX; Essex Junction, VT; T. J. Watson Research Center, NY; Bromont, QC and IBM Deutschland Research & Development GmbH, Böblingen, Germany laboratories. IBM announced servers based on POWER7 on 8 February 2010.
The PowerPC 400 family is a line of 32-bit embedded RISC processor cores based on the PowerPC or Power ISA instruction set architectures. The cores are designed to fit inside specialized applications ranging from system-on-a-chip (SoC) microcontrollers, network appliances, application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs) to set-top boxes, storage devices and supercomputers.
1T-SRAM is a pseudo-static random-access memory (PSRAM) technology introduced by MoSys, Inc., which offers a high-density alternative to traditional static random access memory (SRAM) in embedded memory applications. Mosys uses a single-transistor storage cell like dynamic random access memory (DRAM), but surrounds the bit cell with control circuitry that makes the memory functionally equivalent to SRAM. 1T-SRAM has a standard single-cycle SRAM interface and appears to the surrounding logic just as an SRAM would.
A multi-chip module (MCM) is generically an electronic assembly where multiple integrated circuits, semiconductor dies and/or other discrete components are integrated, usually onto a unifying substrate, so that in use it can be treated as if it were a larger IC. Other terms, such as "hybrid" or "hybrid integrated circuit", also refer to MCMs. The individual ICs that make up an MCM are known as Chiplets. Intel and AMD are using MCMs to improve performance and reduce costs, as splitting a large monolithic IC into smaller chiplets allows for easy performance improvements, more ICs per wafer, and improved yield, as smaller dies have a reduced risk of getting destroyed by dust particles during semiconductor fabrication. Each chiplet is physically smaller than a conventional monolithic IC die,. An example of MCMs in use for mainstream CPUs is AMD's Zen 2 design.
Memory refresh is the process of periodically reading information from an area of computer memory and immediately rewriting the read information to the same area without modification, for the purpose of preserving the information. Memory refresh is a background maintenance process required during the operation of semiconductor dynamic random-access memory (DRAM), the most widely used type of computer memory, and in fact is the defining characteristic of this class of memory.
Microsoft XCPU, codenamed Xenon, is a CPU used in the Xbox 360 game console, to be used with ATI's Xenos graphics chip.
The transistor count is the number of transistors on an integrated circuit (IC). It typically refers to the number of MOSFETs on an IC chip, as all modern ICs use MOSFETs. It is the most common measure of IC complexity. The rate at which MOS transistor counts have increased generally follows Moore's law, which observed that the transistor count doubles approximately every two years.
The memory controller is a digital circuit that manages the flow of data going to and from the computer's main memory. A memory controller can be a separate chip or integrated into another chip, such as being placed on the same die or as an integral part of a microprocessor; in the latter case, it is usually called an integrated memory controller (IMC). A memory controller is sometimes also called a memory chip controller (MCC) or a memory controller unit (MCU).
Hollywood is the name of the graphics processing unit (GPU) used in Nintendo's Wii video game console. It was designed by ATI, and is manufactured using the same 90 nm CMOS process as the "Broadway" processor. Very few official details were released to the public by Nintendo, ATI, or IBM. The Hollywood GPU is reportedly based on the GameCube's "Flipper" GPU and is clocked 50% higher at 243 MHz, though none of the clock rates were ever confirmed by Nintendo, IBM, or ATI.
The 800 nm process refers to the level of MOSFET semiconductor fabrication process technology that was reached around the 1987–1990 timeframe, by leading semiconductor companies like NTT, NEC, Toshiba, IBM, Hitachi, Matsushita, Mitsubishi Electric and Intel.
Haswell is the codename for a processor microarchitecture developed by Intel as the "fourth-generation core" successor to the Ivy Bridge. Intel officially announced CPUs based on this microarchitecture on June 4, 2013, at Computex Taipei 2013, while a working Haswell chip was demonstrated at the 2011 Intel Developer Forum. With Haswell, which uses a 22 nm process, Intel also introduced low-power processors designed for convertible or "hybrid" ultrabooks, designated by the "Y" suffix.
Random-access memory is a form of computer memory that can be read and changed in any order, typically used to store working data and machine code. A random-access memory device allows data items to be read or written in almost the same amount of time irrespective of the physical location of data inside the memory. In contrast, with other direct-access data storage media such as hard disks, CD-RWs, DVD-RWs and the older magnetic tapes and drum memory, the time required to read and write data items varies significantly depending on their physical locations on the recording medium, due to mechanical limitations such as media rotation speeds and arm movement.
A 1996–2004 research project in the Computer Science Division of the University of California, Berkeley, the Berkeley IRAM project explored computer architecture enabled by the wide bandwidth between memory and processor made possible when both are designed on the same integrated circuit (chip). Since it was envisioned that such a chip would consist primarily of random-access memory (RAM), with a smaller part needed for the central processing unit (CPU), the research team used the term "Intelligent RAM" to describe a chip with this architecture. Like the J–Machine project at MIT, the primary objective of the research was to avoid the Von Neumann bottleneck which occurs when the connection between memory and CPU is a relatively narrow memory bus between separate integrated circuits.
Broadwell is Intel's codename for the 14 nanometer die shrink of its Haswell microarchitecture. It is a "tick" in Intel's tick–tock principle as the next step in semiconductor fabrication. Like some of the previous tick-tock iterations, Broadwell did not completely replace the full range of CPUs from the previous microarchitecture (Haswell), as there were no low-end desktop CPUs based on Broadwell.
Espresso is the codename of the 32-bit central processing unit (CPU) used in Nintendo's Wii U video game console. It was designed by IBM, and was produced using a 45 nm silicon-on-insulator process. The Espresso chip resides together with a GPU from AMD on a MCM manufactured by Renesas. It was revealed at E3 2011 in June 2011 and released in November 2012.