Logo for Core i7 Bloomfield processors
|Launched||November 11, 2008|
|Max. CPU clock rate||1.06 GHz to 3.33 GHz|
|L1 cache||64 KB per core|
|L2 cache||256 KB per core|
|L3 cache||4 MB to 24 MB shared|
|Architecture and classification|
|Products, models, variants|
|Predecessor|| Core (tock) |
|Successor|| Westmere (tick) |
Sandy Bridge (tock)
Nehalem // is the codename for an Intel processor microarchitecture released in November 2008. Nehalem was used in the first generation of the Intel Core processors (Core i7 and i5, with Core i3 being based on the subsequent Westmere and Sandy Bridge designs). Nehalem is the successor to the older Core microarchitecture (Intel Core 2 processors).
The Intel codename "Nehalem" was taken from the Nehalem River. nm process, run at higher clock speeds, and are more energy-efficient than Penryn microprocessors. Hyper-threading is reintroduced, along with a reduction in L2 cache size, as well as an enlarged L3 cache that is shared among all cores.It is an architecture that differs radically from Netburst, while retaining some of the latter's minor features. Nehalem-based microprocessors use the 45
Nehalem was replaced with the Sandy Bridge microarchitecture, released in January 2011.
|Name||Level||4 KB||2 MB|
|ITLB||1st||128||7 / logical core|
It has been reported that Nehalem has a focus on performance, thus the increased core size.Compared to Penryn, Nehalem has:
Overclocking is possible with Bloomfield processors and the X58 chipset. Lynnfield processors use a PCH removing the need for a northbridge.
Nehalem processors incorporate SSE 4.2 SIMD instructions, adding seven new instructions to the SSE 4.1 set in the Core 2 series. The Nehalem architecture reduces atomic operation latency by 50% in an attempt to eliminate overhead on atomic operations such as the
LOCK CMPXCHG compare-and-swap instruction.
|Processing Cores (interface)||Process||Die Size||CPUID||Model||Stepping||Mobile||Desktop, UP Server||DP Server||MP Server|
|Eight-Core (Quad-Channel)||45 nm||684 mm²||206E6||46||D0||Beckton (80604)|
|Quad-Core (Triple-Channel)||45 nm||263 mm²||106A4|
|Bloomfield (80601)||Gainestown (80602)|
|Quad-Core (Dual-Channel, PCIe)||45 nm||296 mm²||106E4|
|Clarksfield (80607)||Lynnfield (80605)||Jasper Forest (80612)|
|Dual-Core (Dual-Channel, PCIe, Graphics Core)||45 nm||Auburndale (80608) (canceled)||Havendale (80606) (canceled)|
|Codename||Market|| Cores /|
Branding & Model
|Release Date||Price for|
|Beckton1||MP Server /|
|8 (16)|| LGA|
|Xeon||X7560||2.26 GHz||Yes||130 W||4× QPI 6.4 GT/s||DDR3-800 /|
(Up to 4x with
|X7550||2.0 GHz||18 MB||$2837|
|L7555||1.86 GHz||95 W||4× QPI 5.86 GT/s||24 MB||$3157|
|6 (12)||E7540||2.0 GHz||105 W||4× QPI 6.4 GT/s||18 MB||$1980|
|E7530||1.86 GHz||4× QPI 5.86 GT/s||$1391|
|L7545||95 W||18 MB||$2087|
|6 (6)||X7542||2.66 GHz||130 W||$1980|
|4 (8)||E7520||1.86 GHz||No||105 W||4× QPI 4.8 GT/s||$856|
|E6510||1.73 GHz||12 MB||$744|
|Gainestown||DP Server||4 (8)|| LGA|
|Xeon||W5590||3.33 GHz||Yes||130 W||2× QPI 6.4 GT/s||3× DDR3-13331||8 MB||2009-08-09||$1600|
|X5570||2.93 GHz||95 W||$1286|
|E5540||2.53 GHz||80 W||2× 5.86 GT/s||3× DDR3-10661||$744|
|L5530||2.4 GHz||60 W||2009-08-09||$744|
|4 (4)||E5507||2.26 GHz||No||80 W||2× 4.8 GT/s||3× DDR3-8001||4 MB||2010-03-16||$266|
|L5506||2.13 GHz||60 W||$423|
|E5504||2.0 GHz||80 W||$224|
|2 (4)||L5508||2.0 GHz||Yes||38 W||2× 5.86 GT/s||3× DDR3-1066||8 MB||$|
|2 (2)||E5503||2.0 GHz||No||80 W||2× 4.8 GT/s||3× DDR3-800||4 MB||2010-03-16||$224|
|Jasper Forest||4 (8)||EC5549||2.53 GHz||Yes||85 W||1× 5.86 GT/s||3× DDR3-1333||8 MB||2010-02-11||$530|
|LC5528||2.13 GHz||60 W||1× 4.8 GT/s||3× DDR3-1066||$519|
|LC5518||1.73 GHz||48 W|
|4 (4)||EC5509||2 GHz||No||85 W||$265|
|2 (4)||EC5539||2.27 GHz||65 W||1× 5.86 GT/s||3× DDR3-1333||4 MB||$387|
|Bloomfield||UP Server||4 (8)||Xeon||W3580||3.33 GHz||Yes||130 W||1× QPI 6.4 GT/s||3× DDR3-1333||8 MB||2009-08-09||$999|
|W3565||3.2 GHz||1× QPI 4.8 GT/s||3× DDR3-1066||2009-11-01||$562|
|2 (2)||W3505||2.53 GHz||No||4 MB||$|
|Jasper Forest||4 (4)||EC3539||2.13 GHz||65 W||DMI||8 MB||2010-02-11||$302|
|2 (4)||LC3528||1.73 GHz||Yes||35 W||3× DDR3-800||4 MB|
|1 (1)||LC3518||No||23 W||2 MB||$192|
|Lynnfield||4 (8)|| LGA|
|X3480||3.06 GHz||Yes||95 W||DMI||2× DDR3-1333||8 MB||2010-05-30||$612|
|L3426||1.86 GHz||45 W||$284|
|4 (4)||X3430||2.4 GHz||95 W||$189|
| Core i7 |
|975||3.33 GHz||Yes||130 W||1× QPI 6.4 GT/s||3× DDR3-1066||2009-05-31||$999|
|Core i7||960||3.2 GHz||1× QPI 4.8 GT/s||2009-10-20||$562|
|880||3.06 GHz||Yes||95 W||DMI||2× DDR3-1333||2010-05-30||$583|
|870S||2.66 GHz||82 W||2010-07-19||$351|
|860||2.8 GHz||95 W||2009-09-08||$284|
|860S||2.53 GHz||82 W||2010-01-07||$337|
|4 (4)||Core i5||760||2.8 GHz||95 W||2010-07-17||$209|
|750||2.66 GHz||95 W||2009-09-08||$196|
|750S||2.4 GHz||82 W||2010-01-07||$259|
|Celeron||P1053||1.33 GHz||No||30 W||3× DDR3-800||2 MB||2010-12-02||$160|
Branding & Model
|Interface||Release Date||Price for|
|940XM||2.13 GHz||Yes||55 W||8 MB||* DMI|
* 2x DDR3-1333
* PCIe 1 x16 / 2 x8
|Core i7||840QM||1.86 GHz||45 W||2010-06-21||$568|
The successor to Nehalem and Westmere is Sandy Bridge .
Hyper-threading is Intel's proprietary simultaneous multithreading (SMT) implementation used to improve parallelization of computations performed on x86 microprocessors. It first appeared in February 2002 on Xeon server processors and in November 2002 on Pentium 4 desktop CPUs. Later, Intel included this technology in Itanium, Atom, and Core 'i' Series CPUs, among others.
Xeon is a brand of x86 microprocessors designed, manufactured, and marketed by Intel, targeted at the non-consumer workstation, server, and embedded system markets. It was introduced in June 1998. Xeon processors are based on the same architecture as regular desktop-grade CPUs, but have some advanced features such as support for ECC memory, higher core counts, support for larger amounts of RAM, larger cache memory and extra provision for enterprise-grade reliability, availability and serviceability (RAS) features responsible for handling hardware exceptions through the Machine Check Architecture. They are often capable of safely continuing execution where a normal processor cannot due to these extra RAS features, depending on the type and severity of the machine-check exception (MCE). Some also support multi-socket systems with two, four, or eight sockets through use of the Quick Path Interconnect (QPI) bus.
The NetBurst microarchitecture, called P68 inside Intel, was the successor to the P6 microarchitecture in the x86 family of CPUs made by Intel. The first CPU to use this architecture was the Willamette-core Pentium 4, released on November 20, 2000 and the first of the Pentium 4 CPUs; all subsequent Pentium 4 and Pentium D variants have also been based on NetBurst. In mid-2004, Intel released the Foster core, which was also based on NetBurst, thus switching the Xeon CPUs to the new architecture as well. Pentium 4-based Celeron CPUs also use the NetBurst architecture.
The Intel QuickPath Interconnect (QPI) is a point-to-point processor interconnect developed by Intel which replaced the front-side bus (FSB) in Xeon, Itanium, and certain desktop platforms starting in 2008. It increased the scalability and available bandwidth. Prior to the name's announcement, Intel referred to it as Common System Interface (CSI). Earlier incarnations were known as Yet Another Protocol (YAP) and YAP+.
The P6 microarchitecture is the sixth-generation Intel x86 microarchitecture, implemented by the Pentium Pro microprocessor that was introduced in November 1995. It is frequently referred to as i686. It was succeeded by the NetBurst microarchitecture in 2000, but eventually revived in the Pentium M line of microprocessors. The successor to the Pentium M variant of the P6 microarchitecture is the Core microarchitecture which in turn is also derived from the P6 microarchitecture.
The Intel Core microarchitecture is a multi-core processor microarchitecture unveiled by Intel in Q1 2006. It is based on the Yonah processor design and can be considered an iteration of the P6 microarchitecture introduced in 1995 with Pentium Pro. High power consumption and heat intensity, the resulting inability to effectively increase clock speed, and other shortcomings such as an inefficient pipeline were the primary reasons why Intel abandoned the NetBurst microarchitecture and switched to a completely different architectural design, delivering high efficiency through a small pipeline rather than high clock speeds. The Core microarchitecture initially did not reach the clock speeds of the NetBurst microarchitecture, even after moving to 45 nm lithography. However after many generations of successor microarchitectures which used Core as their basis, Intel managed to eventually surpass the clock speeds of Netburst with the Devil's Canyon microarchitecture reaching a base frequency of 4 GHz and a maximum tested frequency of 4.4 GHz using 22 nm lithography.
Pentium is a brand used for a series of x86 architecture-compatible microprocessors produced by Intel since 1993. In their form as of November 2011, Pentium processors are considered entry-level products that Intel rates as "two stars", meaning that they are above the low-end Atom and Celeron series, but below the faster Intel Core lineup, and workstation Xeon series.
Sandy Bridge is the codename for the microarchitecture used in the "second generation" of the Intel Core processors - the Sandy Bridge microarchitecture is the successor to Nehalem microarchitecture. Intel demonstrated a Sandy Bridge processor in 2009, and released first products based on the architecture in January 2011 under the Core brand.
Larrabee is the codename for a cancelled GPGPU chip that Intel was developing separately from its current line of integrated graphics accelerators. It is named after Larrabee State Park in Whatcom County, Washington, near the town of Bellingham. The chip was to be released in 2010 as the core of a consumer 3D graphics card, but these plans were cancelled due to delays and disappointing early performance figures. The project to produce a GPU retail product directly from the Larrabee research project was terminated in May 2010. The Intel MIC multiprocessor architecture announced in 2010 inherited many design elements from the Larrabee project, but does not function as a graphics processing unit; the product is intended as a co-processor for high performance computing.
Haswell is the codename for a processor microarchitecture developed by Intel as the "fourth-generation core" successor to the Ivy Bridge. Intel officially announced CPUs based on this microarchitecture on June 4, 2013, at Computex Taipei 2013, while a working Haswell chip was demonstrated at the 2011 Intel Developer Forum. With Haswell, which uses a 22 nm process, Intel also introduced low-power processors designed for convertible or "hybrid" ultrabooks, designated by the "Y" suffix.
"Uncore" is a term used by Intel to describe the functions of a microprocessor that are not in the core, but which must be closely connected to the core to achieve high performance. It has been called "system agent" since the release of the Sandy Bridge microarchitecture. The core contains the components of the processor involved in executing instructions, including the ALU, FPU, L1 and L2 cache. Uncore functions include QPI controllers, L3 cache, snoop agent pipeline, on-die memory controller, and Thunderbolt controller. Other bus controllers such as SPI and LPC are part of the chipset.
Bloomfield is the code name for Intel high-end desktop processors sold as Core i7-9xx and single-processor servers sold as Xeon 35xx., in almost identical configurations, replacing the earlier Yorkfield processors. The Bloomfield core is closely related to the dual-processor Gainestown, which has the same CPUID value of 0106Ax and which uses the same socket. Bloomfield uses a different socket than the later Lynnfield and Clarksfield processors based on the same 45 nm Nehalem microarchitecture, even though some of these share the same Intel Core i7 brand.
Intel Core is a line of mid- to high-end consumer, workstation, and enthusiast central processing units (CPU) marketed by Intel Corporation. These processors displaced the existing mid- to high-end Pentium processors of the time, moving the Pentium to the entry level, and bumping the Celeron series of processors to the low end. Identical or more capable versions of Core processors are also sold as Xeon processors for the server and workstation markets.
Clarkdale is the code name for an Intel processor, initially sold as desktop Intel Core i5 and Core i3 and Pentium. It is closely related to the mobile Arrandale processor; both use dual-core dies based on the Westmere 32 nm die shrink of the Nehalem microarchitecture, and have integrated Graphics as well as PCI Express and DMI links.
Bonnell is a CPU microarchitecture used by Intel Atom processors which can execute up to two instructions per cycle. Like many other x86 microprocessors, it translates x86 instructions into simpler internal operations prior to execution. The majority of instructions produce one micro-op when translated, with around 4% of instructions used in typical programs producing multiple micro-ops. The number of instructions that produce more than one micro-op is significantly fewer than the P6 and NetBurst microarchitectures. In the Bonnell microarchitecture, internal micro-ops can contain both a memory load and a memory store in connection with an ALU operation, thus being more similar to the x86 level and more powerful than the micro-ops used in previous designs. This enables relatively good performance with only two integer ALUs, and without any instruction reordering, speculative execution or register renaming. A side effect of having no speculative execution is invulnerability against Meltdown and Spectre.
Ivy Bridge is the codename for the "third generation" of the Intel Core processors. Ivy Bridge is a die shrink to 22 nanometer manufacturing process based on the 32 nanometer Sandy Bridge - see tick–tock model. The name is also applied more broadly to the 22 nm die shrink of the Sandy Bridge microarchitecture based on FinFET ("3D") Tri-Gate transistors, which is also used in the Xeon and Core i7 Ivy Bridge-EX (Ivytown), Ivy Bridge-EP and Ivy Bridge-E microprocessors released in 2013.
Westmere is the code name given to the 32 nm die shrink of Nehalem. While sharing the same CPU sockets, Westmere included Intel HD, UHD and Iris Graphics, Nehalem did not.
This is a table of 64/32-bit ARMv8-A architecture cores comparing microarchitectures which implement the AArch64 instruction set and mandatory or optional extensions of it. Most chips support 32-bit AArch32 for legacy applications. All chips of this type have a floating-point unit (FPU) that is better than the one in older ARMv7 and NEON (SIMD) chips. Some of these chips have coprocessors also include cores from the older 32-bit architecture (ARMv7). Some of the chips are SoCs and can combine both ARM Cortex-A53 and ARM Cortex-A57, such as the Samsung Exynos 7 Octa.