StrongARM

Last updated October 14, 2024

The StrongARM is a family of computer microprocessors developed by Digital Equipment Corporation and manufactured in the late 1990s which implemented the ARM v4 instruction set architecture.^[1] It was later acquired by Intel in 1997 from DEC's own Digital Semiconductor division as part of a settlement of a lawsuit between the two companies over patent infringement.^[2] Intel then continued to manufacture it before replacing it with the StrongARM-derived ARM-based follow-up architecture called XScale in the early 2000s.

History

According to Allen Baum, the StrongARM traces its history to attempts to make a low-power version of the DEC Alpha, which DEC's engineers quickly concluded was not possible. They then became interested in designs dedicated to low-power applications which led them to the ARM family. One of the only major users of the ARM for performance-related products at that time was Apple, whose Newton device was based on the ARM platform. DEC approached Apple wondering if they might be interested in a high-performance ARM, to which the Apple engineers replied "Phhht, yeah. You can't do it, but, yeah, if you could we'd use it."^[3]

The StrongARM was a collaborative project between DEC and Advanced RISC Machines to create a faster ARM microprocessor. The StrongARM was designed to address the upper end of the low-power embedded market, where users needed more performance than the ARM could deliver while being able to accept more external support. Targets were devices such as newer personal digital assistants and set-top boxes.^[4]^[5]

Traditionally, the semiconductor division of DEC was located in Massachusetts. In order to gain access to the design talent in Silicon Valley, DEC opened a design center in Palo Alto, California. This design center was led by Dan Dobberpuhl and was the main design site for the StrongARM project. Another design site that worked on the project was in Austin, Texas that was created by some ex-DEC designers returning from Apple Computer and Motorola. The project was set up in 1995, and quickly delivered their first design, the SA-110.

DEC agreed to sell StrongARM to Intel as part of a lawsuit settlement in 1997.^[6] Intel used the StrongARM to replace their ailing line of RISC processors, the i860 and i960.

When the semiconductor division of DEC was sold to Intel, many engineers from the Palo Alto design group moved to SiByte, a start-up company designing MIPS system-on-a-chip (SoC) products for the networking market. The Austin design group spun off to become Alchemy Semiconductor, another start-up company designing MIPS SoCs for the hand-held market. A new StrongARM core was developed by Intel and introduced in 2000 as the XScale.^[7]

SA-110

The SA-110 was the first microprocessor in the StrongARM family. The first versions, operating at 100, 160, and 200 MHz, were announced on 5 February 1996.^[8] When announced, samples of these versions were available, with volume production slated for mid-1996. Faster 166 and 233 MHz versions were announced on 12 September 1996.^[9] Samples of these versions were available at announcement, with volume production slated for December 1996. Throughout 1996, the SA-110 was the highest performing microprocessor for portable devices.^[10] Towards the end of 1996 it was a leading CPU for internet/intranet appliances and thin client systems.^[11] The SA-110's first design win was the Apple MessagePad 2000.^[12] It was also used in a number of products including the Acorn Computers Risc PC and Eidos Optima video editing system. The SA-110's lead designers were Daniel W. Dobberpuhl, Gregory W. Hoeppner, Liam Madden, and Richard T. Witek.^[4]

Description

The SA-110 had a simple microarchitecture. It was a scalar design that executed instructions in-order with a five-stage classic RISC pipeline. The microprocessor was partitioned into several blocks, the IBOX, EBOX, IMMU, DMMU, BIU, WB and PLL. The IBOX contained hardware that operated in the first two stages of the pipeline such as the program counter. It fetched, decoded and issued instructions. Instruction fetch occurs during the first stage, decode and issue during the second. The IBOX decodes the more complex instructions in the ARM instruction set by translating them into sequences of simpler instructions. The IBOX also handled branch instructions. The SA-110 did not have branch prediction hardware, but had mechanisms for their speedy processing.

Execution starts at stage three. The hardware that operates during this stage is contained in the EBOX, which comprises the register file, arithmetic logic unit (ALU), barrel shifter, multiplier and condition code logic. The register file had three read ports and two write ports. The ALU and barrel shifter executed instructions in a single cycle. The multiplier is not pipelined and has a latency of multiple cycles.

The IMMU and DMMU are memory management units for instructions and data, respectively. Each MMU contained a 32-entry fully associative translation lookaside buffer (TLB) that can map 4 KB, 64 KB or 1 MB pages. The write buffer (WB) has eight 16-byte entries. It enables the pipelining of stores. The bus interface unit (BIU) provided the SA-110 with an external interface.

The PLL generates the internal clock signal from an external 3.68 MHz clock signal. It was not designed by DEC, but was contracted to the Centre Suisse d'Electronique et de Microtechnique (CSEM) located in Neuchâtel, Switzerland.

The instruction cache and data cache each have a capacity of 16 KB and are 32-way set-associative and virtually addressed. The SA-110 was designed to be used with slow (and therefore low-cost) memory and therefore the high set associativity allows a higher hit rate than competing designs, and the use of virtual addresses allows memory to be simultaneously cached and uncached. The caches are responsible for most of the transistor count and they take up half the die area.

The SA-110 contained 2.5 million transistors and is 7.8 mm by 6.4 mm large (49.92 mm²). It was fabricated by DEC in its proprietary CMOS-6 process at its Fab 6 fab in Hudson, Massachusetts. CMOS-6 was DEC's sixth-generation complementary metal–oxide–semiconductor (CMOS) process. CMOS-6 has a 0.35 μm feature size, a 0.25 μm effective channel length but for use with the SA-110, only three levels of aluminium interconnect. It used a power supply with a variable voltage of 1.2 to 2.2 volts (V) to enable designs to find a balance between power consumption and performance (higher voltages enable higher clock rates). The SA-110 was packaged in a 144-pin thin quad flat pack (TQFP).

SA-1100

The SA-1100 was a derivative of the SA-110 developed by DEC. Announced in 1997, the SA-1100 was targeted for portable applications such as PDAs and differs from the SA-110 by providing a number of features that are desirable for such applications. To accommodate these features, the data cache was reduced in size to 8 KB.

The extra features are integrated memory, PCMCIA, and color LCD controllers connected to an on-die system bus, and five serial I/O channels that are connected to a peripheral bus attached to the system bus. The memory controller supported FPM and EDO DRAM, SRAM, flash, and ROM. The PCMCIA controller supports two slots. The memory address and data bus is shared with the PCMCIA interface. Glue logic is required. The serial I/O channels implement a slave USB interface, a SDLC, two UARTs, an IrDA interface, a MCP, and a synchronous serial port.

The SA-1100 had a companion chip, the SA-1101. It was introduced by Intel on 7 October 1998.^[13] The SA-1101 provided additional peripherals to complement those integrated on the SA-1100 such as a video output port, two PS/2 ports, a USB controller and a PCMCIA controller that replaces that on the SA-1100. Design of the device started by DEC, but was only partially complete when acquired by Intel, who had to finish the design. It was fabricated at DEC's former Hudson, Massachusetts fabrication plant, which was also sold to Intel.^[14]

The SA-1100 contained 2.5 million transistors and measured 8.24 mm by 9.12 mm (75.15 mm²). It was fabricated in a 0.35 μm CMOS process with three levels of aluminium interconnect and was packaged in a 208-pin TQFP.^[15]

One of the early recipients of this processor was-ill-fated Psion netBook and its more consumer oriented sibling Psion Series 7.

SA-1110

The SA-1110 was a derivative of the SA-110 developed by Intel. It was announced on 31 March 1999, positioned as an alternative to the SA-1100.^[16] At announcement, samples were set for June 1999 and volume later that year. Intel discontinued the SA-1110 in early 2003.^[17] The SA-1110 was available in 133 or 206 MHz versions. It differed from the SA-1100 by featuring support for 66 MHz (133 MHz version only) or 103 MHz (206 MHz version only) SDRAM.^[18] Its companion chip, which provided additional support for peripherals, was the SA-1111. The SA-1110 was packaged in a 256-pin micro ball grid array. It was used in mobile phones, personal data assistants (PDAs) such as the Compaq (later HP) iPAQ and HP Jornada, the Sharp SL-5x00 Linux Based Platforms and the Simputer.^[19] It was also used to run the Intel Web Tablet, a tablet device that is considered potentially the first to introduce large screen, portable web browsing. Intel dropped the product just prior to launch in 2001.

SA-1500

The SA-1500 was a derivative of the SA-110 developed by DEC initially targeted for set-top boxes.^[20]^[21] It was designed and manufactured in low volumes by DEC but was never put into production by Intel. The SA-1500 was available at 200 to 300 MHz. The SA-1500 featured an enhanced SA-110 core, an on-chip coprocessor called the Attached Media Processor (AMP), and an on-chip SDRAM and I/O bus controller. The SDRAM controller supported 100 MHz SDRAM, and the I/O controller implemented a 32-bit I/O bus that may run at frequencies up to 50 MHz for connecting to peripherals and the SA-1501 companion chip.

The AMP implemented a long-instruction-word instruction set containing instructions designed for multimedia, such as integer and floating-point multiply–accumulate operations and SIMD arithmetic. Each long-instruction word is 64 bits wide and specifies an arithmetic operation and a branch or a load/store. Instructions operate on operands from a 64-entry 36-bit register file, and on a set of control registers. The AMP communicates with the SA-110 core via an on-chip bus and it shares the data cache with the SA-110. The AMP contained an ALU with a shifter, a branch unit, a load/store unit, a multiply–accumulate unit, and a single-precision floating-point unit. The AMP supported user-defined instructions via a 512-entry writable control store.^[22]

The SA-1501 companion chip provided additional video and audio processing capabilities and various I/O functions such as PS/2 ports, a parallel port, and interfaces for various peripherals.

The SA-1500 contains 3.3 million transistors and measures 60 mm². It was fabricated in a 0.28 μm CMOS process. It used a 1.5 to 2.0 V internal power supply and 3.3 V I/O, consuming less than 0.5 W at 100 MHz and 2.5 W at 300 MHz. It was packaged in a 240-pin metal quad flat package or a 256-ball plastic ball grid array.

StrongARM latch

The StrongARM latch is an electronic latch circuit topology first^[23]^[24] proposed by Toshiba engineers Tsuguo Kobayashi et al.^[25] and got significant attention after being used in StrongARM microprocessors.^[23]^[24] It is widely used as a sense amplifier, a comparator, or just a robust latch with high sensitivity.^[23]^[24]

Related Research Articles

Processor design is a subfield of computer science and computer engineering (fabrication) that deals with creating a processor, a key component of computer hardware.

Alpha is a 64-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC). Alpha was designed to replace 32-bit VAX complex instruction set computers (CISC) and to be a highly competitive RISC processor for Unix workstations and similar markets.

A microprocessor is a computer processor for which the data processing logic and control is included on a single integrated circuit (IC), or a small number of ICs. The microprocessor contains the arithmetic, logic, and control circuitry required to perform the functions of a computer's central processing unit (CPU). The IC is capable of interpreting and executing program instructions and performing arithmetic operations. The microprocessor is a multipurpose, clock-driven, register-based, digital integrated circuit that accepts binary data as input, processes it according to instructions stored in its memory, and provides results as output. Microprocessors contain both combinational logic and sequential digital logic, and operate on numbers and symbols represented in the binary number system.

The Pentium is a x86 microprocessor introduced by Intel on March 22, 1993. It is the first CPU using the Pentium brand. Considered the fifth generation in the 8086 compatible line of processors, its implementation and microarchitecture was internally called P5.

XScale is a microarchitecture for central processing units initially designed by Intel implementing the ARM architecture instruction set. XScale comprises several distinct families: IXP, IXC, IOP, PXA and CE, with some later models designed as system-on-a-chip (SoC). Intel sold the PXA family to Marvell Technology Group in June 2006. Marvell then extended the brand to include processors with other microarchitectures, like Arm's Cortex.

Intel's i960 was a RISC-based microprocessor design that became popular during the early 1990s as an embedded microcontroller. It became a best-selling CPU in that segment, along with the competing AMD 29000. In spite of its success, Intel stopped marketing the i960 in the late 1990s, as a result of a settlement with DEC whereby Intel received the rights to produce the StrongARM CPU. The processor continues to be used for a few military applications.

Alchemy is a family of ultra low power embedded microprocessors originally designed by Alchemy Semiconductor for communication and media devices. Alchemy processors are SoCs integrating a CPU core, a memory controller, and a varying set of peripherals. All members of the family use the Au1 CPU core implementing the MIPS32 instruction set by MIPS Technologies.

The R3000 is a 32-bit RISC microprocessor chipset developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture (ISA). Introduced in June 1988, it was the second MIPS implementation, succeeding the R2000 as the flagship MIPS microprocessor. It operated at 20, 25 and 33.33 MHz.

The R4000 is a microprocessor developed by MIPS Computer Systems that implements the MIPS III instruction set architecture (ISA). Officially announced on 1 October 1991, it was one of the first 64-bit microprocessors and the first MIPS III implementation. In the early 1990s, when RISC microprocessors were expected to replace CISC microprocessors such as the Intel i486, the R4000 was selected to be the microprocessor of the Advanced Computing Environment (ACE), an industry standard that intended to define a common RISC platform. ACE ultimately failed for a number of reasons, but the R4000 found success in the workstation and server markets.

The PowerPC 600 family was the first family of PowerPC processors built. They were designed at the Somerset facility in Austin, Texas, jointly funded and staffed by engineers from IBM and Motorola as a part of the AIM alliance. Somerset was opened in 1992 and its goal was to make the first PowerPC processor and then keep designing general purpose PowerPC processors for personal computers. The first incarnation became the PowerPC 601 in 1993, and the second generation soon followed with the PowerPC 603, PowerPC 604 and the 64-bit PowerPC 620.

The NEC V60 is a CISC microprocessor manufactured by NEC starting in 1986. Several improved versions were introduced with the same instruction set architecture (ISA), the V70 in 1987, and the V80 and AFPP in 1989. They were succeeded by the V800 product families, which is currently produced by Renesas Electronics.

The Alpha 21064 is a microprocessor developed and fabricated by Digital Equipment Corporation that implemented the Alpha instruction set architecture (ISA). It was introduced as the DECchip 21064 before it was renamed in 1994. The 21064 is also known by its code name, EV4. It was announced in February 1992 with volume availability in September 1992. The 21064 was the first commercial implementation of the Alpha ISA, and the first microprocessor from Digital to be available commercially. It was succeeded by a derivative, the Alpha 21064A in October 1993. This last version was replaced by the Alpha 21164 in 1995.

The Alpha 21164, also known by its code name, EV5, is a microprocessor developed and fabricated by Digital Equipment Corporation that implemented the Alpha instruction set architecture (ISA). It was introduced in January 1995, succeeding the Alpha 21064A as Digital's flagship microprocessor. It was succeeded by the Alpha 21264 in 1998.

The Alpha 21264 is a RISC microprocessor developed by Digital Equipment Corporation launched on 19 October 1998. The 21264 implemented the Alpha instruction set architecture (ISA).

The UltraSPARC III, code-named "Cheetah", is a microprocessor that implements the SPARC V9 instruction set architecture (ISA) developed by Sun Microsystems and fabricated by Texas Instruments. It was introduced in 2001 and operates at 600 to 900 MHz. It was succeeded by the UltraSPARC IV in 2004. Gary Lauterbach was the chief architect.

The R2000 is a 32-bit microprocessor chip set developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture (ISA). Introduced in January 1986, it was, by a few months, the first commercial implementation of the RISC architecture. The R2000 competed with Digital Equipment Corporation (DEC) VAX minicomputers and with Motorola 68000 and Intel Corporation 80386 microprocessors. R2000 users included Ardent Computer, DEC, Silicon Graphics, Northern Telecom and MIPS's own Unix workstations.

The IXP1200 is a network processor fabricated by Intel Corporation. The processor was originally a Digital Equipment Corporation (DEC) project that had been in development since late 1996. When parts of DEC's Digital Semiconductor business was acquired by Intel in 1998 as part of an out-of-court settlement to end lawsuits each company had launched at each other for patent infringement, the processor was transferred to Intel. The DEC design team was retained and the design was completed by them under Intel. Samples of the processor were available for Intel partners since 1999, with general sample availability in late 1999. The processor was introduced in early 2000 at 166 and 200 MHz. A 232 MHz version was introduced later. The processor was later succeeded by the IXP2000, an XScale-based family developed entirely by Intel.

The PA-7100LC is a microprocessor that implements the PA-RISC 1.1 instruction set architecture (ISA) developed by Hewlett-Packard (HP). It is also known as the PCX-L, and by its code-name, Hummingbird. It was designed as a low-cost microprocessor for low-end systems. The first systems to feature the PA-7100LC were introduced in January 1994. These systems used 60 and 80 MHz clock rates. A 100 MHz part debuted in June 1994. The PA-7100LC was the first PA-RISC microprocessor to implement the MAX-1 multimedia instructions, an early single instruction, multiple data (SIMD) multimedia instruction set extension that provided instructions for improving the performance of MPEG video decoding.

Since 1985, many processors implementing some version of the MIPS architecture have been designed and used widely.

References

↑ "StrongARM Microprocessor: SA-110". datasheets.chipdb.org. Retrieved 31 July 2024.
↑ Levine, Daniel S. (11 August 2022) [1997-10-27]. "Intel, DEC Settle Alpha Chip Dispute". Wired.com. Archived from the original on 14 March 2016. Retrieved 11 August 2022.
↑ Baum, Allen (18 July 2018). "Oral History of Allen Baum" (PDF) (Interview). Interviewed by David Brock. p. 60.
1 2 Montanaro, James et al. (1997). "A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor" Archived 1 January 2019 at the Wayback Machine . Digital Technical Journal, vol. 9, no. 1. pp. 49–62.
↑ "Digital targets supercharged StrongARM chip at consumer electronics market". PR Newswire. 5 February 1996. Retrieved 7 June 2011.
↑ Luening, Erich (27 October 1997). "Intel, Digital settle suit". CNet news.com. Retrieved 29 July 2008.
↑ "Embedded Processor Watch #46; 5/4/1999". mdronline.com. Archived from the original on 19 October 2007.
↑ Digital Equipment Corporation (5 February 1996). "Digital Targets Supercharged StrongARM Chip at Consumer Electronics Market". Press release.
↑ Digital Equipment Corporation (12 September 1996). "Digital's StrongARM Chips Pull Away in Embedded Race". Press release.
↑ Turley, Jim (27 January 1997). "Embedded Vendors Seek Differentiation". Microprocessor Report , pp. 16–21.
↑ "Digital's StrongARM Microprocessors Take CPU Lead in Network Client Market". EE Times . 18 November 1996. Retrieved 16 March 2012.
↑ Turley, Jim (18 November 1996). "Newton First Design Win for StrongARM". Microprocessor Report, p. 5.
↑ Intel Corporation (7 October 1998). "Intel Introduces StrongARM Products for PC Companions". Press release.
↑ "The Linley Group - The industry's leading experts in communications semiconductor markets". mdronline.com.
↑ Stephany, R. et al. (1998). "A 200MHz 32b 0.5W CMOS RISC Microprocessor". ISSCC Digest of Technical Papers, pp. 238–239, 443.
↑ Intel Corporation (31 March 1999). "Intel StrongARM Processor, Companion Chip Optimized For Handheld Computing Devices". Press release.
↑ Martyn Williams (14 February 2003). "Intel puts StrongArm on death row". InfoWorld .
↑ "The Linley Group - The industry's leading experts in communications semiconductor markets". mdronline.com.
↑ "The Linley Group - The industry's leading experts in communications semiconductor markets". mdronline.com.
↑ Rick Boyd-Merrit; Peter Clarke (24 July 1998). "Intel to reveal details on StrongARM chip". EE Times .
↑ Prashant P. Gandhi (18 August 1998). "SA-1500: A 300 MHz RISC CPU with Attached Media Processor" Archived 20 November 2008 at the Wayback Machine . Hot Chips 10.
↑ Turley, Jim (8 December 1997). "StrongARM-1500 Grapples With MPEG-2" (PDF). Microprocessor Report . Retrieved 14 March 2024.
1 2 3 Abidi, A.; Hao Xu (15–17 September 2014). "Understanding the regenerative comparator circuit". Proceedings of the IEEE 2014 Custom Integrated Circuits Conference. IEEE. pp. 1–8. doi:10.1109/CICC.2014.6946003. ISBN 978-1-4799-3286-3. S2CID 329565.{{cite book}}: CS1 maint: numeric names: authors list (link)
1 2 3 Razavi, B. (22 June 2015). "The StrongARM Latch". IEEE Solid-State Circuits Magazine. 7 (2). IEEE: 12–17. doi:10.1109/MSSC.2015.2418155. S2CID 9477992.{{cite journal}}: CS1 maint: numeric names: authors list (link)
↑ Kobayashi, T.; Nogami, K.; Shirotori, T.; Fujimoto, Y.; Watanabe, O. (4–6 June 1992). "A current-mode latch sense amplifier and a static power saving input buffer for low-power architecture". 1992 Symposium on VLSI Circuits Digest of Technical Papers. IEEE. pp. 28–29. doi:10.1109/VLSIC.1992.229252. ISBN 0-7803-0701-1. S2CID 67412709.{{cite book}}: CS1 maint: numeric names: authors list (link)