The Alpha 21164, also known by its code name, EV5, is a microprocessor developed and fabricated by Digital Equipment Corporation that implemented the Alpha instruction set architecture (ISA). It was introduced in January 1995, succeeding the Alpha 21064A as Digital's flagship microprocessor. It was succeeded by the Alpha 21264 in 1998.
First silicon of the Alpha 21164 was produced in February 1994, and the OpenVMS, Digital UNIX and Windows NT operating systems were successfully booted on it. It was sampled in late 1994 and was introduced in January 1995 at 266 MHz. A 300 MHz version was introduced in March 1995. The final Alpha 21164, a 333 MHz version, was announced on 2 October 1995, available in sample quantities. The Alpha 21164 was replaced by the Alpha 21164A as Digital's flagship microprocessor in 1996 when a 400 MHz version became available in volume quantities.
Digital used the Alpha 21164 operating at various clock frequencies in their AlphaServer servers, AlphaStation workstations. Digital also used the Alpha 21164 in their Alpha VME 5/352 and Alpha VME 5/480 single board computers and AlphaPC 164 and AlphaPC 164LX motherboards. Alpha partner Cray Research used a 300 MHz Alpha 21164 in their T3E-600 supercomputer. Third parties such as DeskStation also built workstations using the Alpha 21164.
The 21164 continued the performance lead from the 275 MHz Alpha 21064A until the introduction of the Intel Pentium Pro in November 1995, when a 200 MHz version outperformed the 300 MHz 21164 on the SPECint95_base benchmark suite. The 21164 retained its floating-point performance lead. The 333 MHz 21164 introduce the following year outperformed the Pentium Pro, but it was later surpassed by the MIPS Technologies R10000 and then by the Hewlett-Packard PA-8000 in the same year. [1]
The Alpha 21164 is a four-issue superscalar microprocessor capable of issuing a maximum of four instructions per clock cycle to four execution units: two integer and two floating-point. The integer pipeline is seven stages long, and the floating-point pipeline is ten stages long. The 21164 implemented a 43-bit virtual address and a 40-bit physical address. It was therefore capable of addressing 8 TB of virtual memory and 1 TB of physical memory.
The integer unit consisted of two integer pipelines and the integer register file. The two pipelines, the add pipeline and the multiply pipeline are not identical, each are responsible for executing different instructions, although both are capable of executing common add, logical, load, compare, and conditional move instructions. The multiply pipeline exclusively executes shift, store, and multiply instructions (in a non-pipelined multiplier). The add pipeline exclusively executes branch instructions.
Except for branch, conditional move, and multiply instructions, all other instructions begin and finish execution during stage five for a one cycle latency. Branch and conditional move instructions are executed during stage six so they can be issued with a compare instruction whose result they depend on.
The integer register file contained forty 64-bit registers, of which thirty-two are specified by the Alpha Architecture and eight are for use by PALcode as scratchpad memory. The register file has four read ports and two write ports evenly divided between the two integer pipelines. [2]
The floating-point unit consisted of two floating-point pipelines and the floating point register file. The two pipelines are not identical, one executed all floating-point instructions except for multiply, and the other executed only multiply instructions. Both pipelines have four stages. A non-pipelined floating-point divider is connected to the add pipeline. All floating-point instructions except for divide have four-cycle latency. Divides have variable latency that depends on whether the operation is being performed on single or on double precision floating-point numbers and numbers. Including overhead, single precision divides have a 15- to 31-cycle latency, whereas double precision divides have a 22- to 60-cycle latency.
The 21164 has three levels of cache, two on-die and one external and optional. The caches and the associated logic consisted of 7.2 million transistors. [3]
The primary cache is split into separate caches for instructions and data, referred to as the I-cache and D-cache respectively. They are 8 KB in size, direct-mapped and have a cache line size of 32 bytes. The D-cache is dual-ported, to improve performance, and is implemented by duplicating the cache twice. It uses a write-through write policy and an on-read allocation policy.
The secondary cache, known as the S-cache, is on-die and has a capacity of 96 KB. An on-die secondary cache was required as the 21164 required more bandwidth than an external secondary cache could supply in order to provide it with enough instructions and data. [4] The cache required two cycles to access due to its large area. To improve performance, the cache is pipelined. Another benefit of an on-die secondary cache was that it could be easily implemented as a multi-way cache, and as a result, the cache is three-way set associative, offering improved hit rates than direct-mapped caches. [5] The S-cache, due to the large physical area required, was implemented in two halves which flank the I-box, E-box, F-box and M-box. This was done so the cache could return data in two cycles.
The tertiary cache, known as the B-cache, is implemented with external SRAMs. The B-cache was optional and some systems using the Alpha 21164 did not have any. The B-cache could have a capacity of 1 to 64 MB, smaller capacities were not supported as they were rendered useless by the on-die S-cache. [6] It is direct-mapped, uses a write-back write policy and an on-write allocation policy. The B-cache is controlled by on-die external interface logic, unlike the 21064, which required an external cache controller. The B-cache could be built with asynchronous or synchronous SRAMs. The B-cache is accessed via the system bus.
The external interface is a 128-bit system bus. The system bus operates at a clock frequency that is 3 to 15 times lower than the internal clock frequency, or 20 to 100 MHz with an internal clock frequency 300 MHz. The system bus' clock signal is generated by the microprocessor.
The internal clock frequency is generated by dividing an external clock signal by two. The Alpha 21164 therefore requires an external clock signal of 600 MHz for a 300 MHz Alpha 21164.
The Alpha 21164 contains 9.3 million transistors on a die measuring 16.5 by 18.1 mm (299 mm2), which was close to the maximum limits of the process. The die was fabricated in Digital's fifth-generation complementary metal–oxide–semiconductor (CMOS) process, CMOS-5, a 0.50 μm process with four levels of aluminium interconnect. [7] The 21164 used a 3.3-volt (V) power supply. It dissipated 46 W at 266 MHz, 51 W at 300 MHz, 56 W at 333 MHz.
The Alpha 21164 is packaged in a 499-pin ceramic interstitial pin grid array (IPGA) measuring 57.40 by 57.40 mm. The package had a heat spreader with two studs to which the heat sink was bolted.
The Alpha 21164 was the basis of a further development code-named EV56. It was introduced as the Alpha 21164, but was originally known as the Alpha 21164A. It operated at clock frequencies of 366, 433, 500, 533, 566, 600 and 666 MHz. [8] [9] [10]
It was first described in October 1995 at the Microprocessor Forum. On 13 November 1995, Digital announced that samples would ship later in the month. The first version, operating at 366 MHz, was introduced in 1996. On 8 July 1996, Digital announced that a 433 MHz version was available and a 500 MHz version was sampling with volume quantities due in September 1996. The 433 MHz version was priced at $1,492 per unit in quantities of 1,000. The 600 MHz version was introduced on 31 March 1997, shipping in volume quantities. Samsung Electronics signed a deal with Digital in June 1996 to second source the Alpha 21164A and the company was the only one to fabricate the 666 MHz model. 366 to 500 MHz samples were introduced on 11 November 1996 with volume availability in 1997. The Alpha 21164A was fabricated at Digital's Hudson, Massachusetts and Samsung's Kihueng, South Korea fabrication plants.
Users of the Alpha 21164A included Cray Research, Digital, Network Appliance (now NetApp), and DeskStation. Cray Research used 450, 600 and 675 MHz Alpha 21164As in later models of their T3E supercomputer. Digital used the Alpha 21164A operating at various clock frequencies in their AlphaServers, AlphaStations, Celebris XL workstations and Digital Personal Workstations. NetApp used 400, 500 and 600 MHz Alpha 21164As in their storage systems. DeskStation used the Alpha 21164A in their Raptor Reflex workstations.
The most notable change was the inclusion of Byte Word Extensions (BWX), an extension to the Alpha Architecture designed to improve byte and word accesses. These instructions are executed by the multiply pipeline. The Alpha 21164A contained 9.66 million transistors on a die measuring 14.4 mm by 14.5 mm, for a die area of 209 mm2. [11] Digital fabricated the die in their sixth generation CMOS process, CMOS-6, a 0.35 μm process with four layers of interconnect. Samsung fabricated the die in their 0.35 μm process with four layers of interconnect based on a 0.3 μm process they developed in early 1996. The Alpha 21164A used a 3.3 V power supply, dissipating 31.0 W at 366 MHz, 36.0 W at 433 MHz, 41.0 W at 500 MHz, 43.5 W at 533 MHz and 48.5 W at 600 MHz.
The Alpha 21164PC, also known as the PCA56, is a low-cost version of the Alpha 21164A introduced on 17 March 1997. The microprocessor was jointly developed by Digital and Mitsubishi Electric Corporation, and both companies fabricated the design. Mitsubishi later suspended the joint development agreement for future Alpha microprocessors with Digital in early 1998 and ceased to fabricate the Alpha 21164PC in mid-1998, exited the Alpha market because the economic conditions in the company's markets. [12] [13]
The Alpha 21164PC operated at clock frequencies of 400, 466 and 533 MHz. Major changes are the omission of the S-cache, a larger I-cache, and the inclusion of Motion Video Instructions (MVI), an extension to the Alpha Architecture which introduced single instruction multiple data (SIMD) instructions for improving the performance of MPEG encoding. The S-cache was removed to reduce the transistor count, which reduced the die size and in turn, cost. The I-cache was doubled in capacity to 16 KB from 8 KB to compensate for the lack of S-cache, as the Alpha 21164 relied on the S-cache to complement the I-cache in order to provide enough bandwidth to achieve adequate performance. The amount of B-cache was limited to 512 KB to 4 MB, with 1 and 2 MB capacities also supported. The microprocessor uses a 43-bit virtual address and 33-bit physical address.
The Alpha 21164PC contained 3.5 million transistors on a die measuring 8.65 by 16.28 mm, for a die area of 141 mm2. Digital fabricated the die in the same process as the Alpha 21164, CMOS-5. The Alpha 21164PC was packaged in 413-pin IPGA measuring 49.78 by 49.78 mm. It used a 3.3 V power supply, dissipating 26.5 W at 400 MHz, 30.5 W at 466 MHz and 35.0 W at 533 MHz.
The Alpha 21164PC was used by Digital in their AlphaPC 164SX motherboard.
A derivative of the PCA56, the PCA57 was designed and fabricated by Samsung Electronics in a 0.28 μm CMOS process. The PCA57 was introduced in late 1998 and operated at clock frequencies of 533, 600 and 666 MHz. Improvements to the PCA56 microarchitecture included doubled I-cache and D-cache capacities: 32 KB and 16 KB respectively. The PCA57 contained 5.7 million transistors on a die measuring 6.7 mm by 15 mm, for a die area of 101 mm2. It operated on a 2.5 V power supply and dissipated 18 W at 533 MHz, 20 W at 600 MHz and 23 W at 666 MHz.
The PCA57 was used by Digital in its AlphaPC 164RX motherboard.
Digital and VLSI Technology developed chipsets for the 21164 and its derivatives. Digital also developed custom application-specific integrated circuit (ASICs) for use in the high-end models of their AlphaServer family such as the AlphaServer 8200 and 8400.
The 21171, also known as Alcor, was the first chipset for the 21164, introduced in January 1995 alongside the microprocessor it supports. It was developed and fabricated by Digital. The 21171 is an upgraded DECchip 21071 modified to support the new system bus protocol the 21164 uses. It consisted of a control chip that contained the memory and PCI controllers, and four data slice chips that interfaced the 256-bit memory bus and PCI bus to the system bus. The 21171 provides a 64-bit wide PCI bus that runs at 33 MHz.
The 21172, also known as Alcor2, was an updated 21171 that supported the 21164A.
The Pyxis chipset, also known as the 21174, supported the 21164A and 21164PC microprocessors. Unlike previous chipsets, it was designed for low-cost systems. As a result, it was a single-chip design packaged in a 474-contact ceramic ball grid array (CBGA) instead of multiple packages. [14] It was subsequently used in cost-sensitive applications such as entry-level workstations (Digital Personal Workstation a-Series) and motherboards such as the AlphaPC 164LX and 164SX. When it was introduced, the 21174 was priced at US$142 in quantities of 1,000. [15]
The 21174 contains a memory controller and PCI controller. The memory controller supported up to 512 MB of synchronous dynamic random access memory (SDRAM) and accesses it via a 128-bit memory bus. The memory can be either ECC or parity protected. The PCI controller provided a PCI or PCI-X bus.
Polaris is a system controller developed by VLSI Technology for personal computers that supports the 21164A and 21164PC microprocessors. Polaris was announced on 16 June 1997. [16] It supports up to 768 MB of EDO DRAM or up to 512 MB of SDRAM. The memory is accessed via a 128-bit bus. It provides a 32-bit, 33 MHz PCI bus for I/O.
Users of Polaris included Digital, for its AlphaPC 164RX motherboard.
Alpha is a 64-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC). Alpha was designed to replace 32-bit VAX complex instruction set computers (CISC) and to be a highly competitive RISC processor for Unix workstations and similar markets.
The Pentium Pro is a sixth-generation x86 microprocessor developed and manufactured by Intel and introduced on November 1, 1995. It introduced the P6 microarchitecture and was originally intended to replace the original Pentium in a full range of applications. While the Pentium and Pentium MMX had 3.1 and 4.5 million transistors, respectively, the Pentium Pro contained 5.5 million transistors. Later, it was reduced to a more narrow role as a server and high-end desktop processor and was used in supercomputers like ASCI Red, the first computer to reach the trillion floating point operations per second (teraFLOPS) performance mark. The Pentium Pro was capable of both dual- and quad-processor configurations. It only came in one form factor, the relatively large rectangular Socket 8. The Pentium Pro was succeeded by the Pentium II Xeon in 1998.
The UltraSPARC is a microprocessor developed by Sun Microsystems and fabricated by Texas Instruments, introduced in mid-1995. It is the first microprocessor from Sun to implement the 64-bit SPARC V9 instruction set architecture (ISA). Marc Tremblay was a co-microarchitect.
SPARC64 is a microprocessor developed by HAL Computer Systems and fabricated by Fujitsu. It implements the SPARC V9 instruction set architecture (ISA), the first microprocessor to do so. SPARC64 was HAL's first microprocessor and was the first in the SPARC64 brand. It operates at 101 and 118 MHz. The SPARC64 was used exclusively by Fujitsu in their systems; the first systems, the Fujitsu HALstation Model 330 and Model 350 workstations, were formally announced in September 1995 and were introduced in October 1995, two years late. It was succeeded by the SPARC64 II in 1996.
The RISC Single Chip, or RSC, is a single-chip microprocessor developed and fabricated by International Business Machines (IBM). The RSC was a feature-reduced single-chip implementation of the POWER1, a multi-chip central processing unit (CPU) which implemented the POWER instruction set architecture (ISA). It was used in entry-level workstation models of the IBM RS/6000 family, such as the Model 220 and 230.
The POWER3 is a microprocessor, designed and exclusively manufactured by IBM, that implemented the 64-bit version of the PowerPC instruction set architecture (ISA), including all of the optional instructions of the ISA such as instructions present in the POWER2 version of the POWER ISA but not in the PowerPC ISA. It was introduced on 5 October 1998, debuting in the RS/6000 43P Model 260, a high-end graphics workstation. The POWER3 was originally supposed to be called the PowerPC 630 but was renamed, probably to differentiate the server-oriented POWER processors it replaced from the more consumer-oriented 32-bit PowerPCs. The POWER3 was the successor of the P2SC derivative of the POWER2 and completed IBM's long-delayed transition from POWER to PowerPC, which was originally scheduled to conclude in 1995. The POWER3 was used in IBM RS/6000 servers and workstations at 200 MHz. It competed with the Digital Equipment Corporation (DEC) Alpha 21264 and the Hewlett-Packard (HP) PA-8500.
The NVAX is a CMOS microprocessor developed and produced by Digital Equipment Corporation (DEC) that implemented the VAX instruction set architecture (ISA). A variant of the NVAX, the NVAX+, differed in the bus interface and external cache supported, but was otherwise identical in regards to microarchitecture. The NVAX+ was designed to have the same bus as the DECchip 21064, allowing drop-in replacement.
The CVAX is a microprocessor chipset developed and fabricated by Digital Equipment Corporation (DEC) that implemented the VAX instruction set architecture (ISA). The chipset consisted of the CVAX 78034 CPU, CFPA floating-point accelerator, CVAX clock chip, and the associated support chips, the CVAX System Support Chip (CSSC), CVAX Memory Controller (CMCTL), and CVAX Q-Bus Interface Chip (CQBIC).
The R10000, code-named "T5", is a RISC microprocessor implementation of the MIPS IV instruction set architecture (ISA) developed by MIPS Technologies, Inc. (MTI), then a division of Silicon Graphics, Inc. (SGI). The chief designers are Chris Rowen and Kenneth C. Yeager. The R10000 microarchitecture is known as ANDES, an abbreviation for Architecture with Non-sequential Dynamic Execution Scheduling. The R10000 largely replaces the R8000 in the high-end and the R4400 elsewhere. MTI was a fabless semiconductor company; the R10000 was fabricated by NEC and Toshiba. Previous fabricators of MIPS microprocessors such as Integrated Device Technology (IDT) and three others did not fabricate the R10000 as it was more expensive to do so than the R4000 and R4400.
The R4000 is a microprocessor developed by MIPS Computer Systems that implements the MIPS III instruction set architecture (ISA). Officially announced on 1 October 1991, it was one of the first 64-bit microprocessors and the first MIPS III implementation. In the early 1990s, when RISC microprocessors were expected to replace CISC microprocessors such as the Intel i486, the R4000 was selected to be the microprocessor of the Advanced Computing Environment (ACE), an industry standard that intended to define a common RISC platform. ACE ultimately failed for a number of reasons, but the R4000 found success in the workstation and server markets.
The R5000 is a 64-bit, bi-endian, superscalar, in-order execution 2-issue design microprocessor, that implements the MIPS IV instruction set architecture (ISA) developed by Quantum Effect Design (QED) in 1996. The project was funded by MIPS Technologies, Inc (MTI), also the licensor. MTI then licensed the design to Integrated Device Technology (IDT), NEC, NKK, and Toshiba. The R5000 succeeded the QED R4600 and R4700 as their flagship high-end embedded microprocessor. IDT marketed its version of the R5000 as the 79RV5000, NEC as VR5000, NKK as the NR5000, and Toshiba as the TX5000. The R5000 was sold to PMC-Sierra when the company acquired QED. Derivatives of the R5000 are still in production today for embedded systems.
The R8000 is a microprocessor chipset developed by MIPS Technologies, Inc. (MTI), Toshiba, and Weitek. It was the first implementation of the MIPS IV instruction set architecture. The R8000 is also known as the TFP, for Tremendous Floating-Point, its name during development.
The PowerPC 600 family was the first family of PowerPC processors built. They were designed at the Somerset facility in Austin, Texas, jointly funded and staffed by engineers from IBM and Motorola as a part of the AIM alliance. Somerset was opened in 1992 and its goal was to make the first PowerPC processor and then keep designing general purpose PowerPC processors for personal computers. The first incarnation became the PowerPC 601 in 1993, and the second generation soon followed with the PowerPC 603, PowerPC 604 and the 64-bit PowerPC 620.
The Alpha 21064 is a microprocessor developed and fabricated by Digital Equipment Corporation that implemented the Alpha instruction set architecture (ISA). It was introduced as the DECchip 21064 before it was renamed in 1994. The 21064 is also known by its code name, EV4. It was announced in February 1992 with volume availability in September 1992. The 21064 was the first commercial implementation of the Alpha ISA, and the first microprocessor from Digital to be available commercially. It was succeeded by a derivative, the Alpha 21064A in October 1993. This last version was replaced by the Alpha 21164 in 1995.
The Alpha 21264 is a Digital Equipment Corporation RISC microprocessor launched on 19 October 1998. The 21264 implemented the Alpha instruction set architecture (ISA).
The PA-8000 (PCX-U), code-named Onyx, is a microprocessor developed and fabricated by Hewlett-Packard (HP) that implemented the PA-RISC 2.0 instruction set architecture (ISA). It was a completely new design with no circuitry derived from previous PA-RISC microprocessors. The PA-8000 was introduced on 2 November 1995 when shipments began to members of the Precision RISC Organization (PRO). It was used exclusively by PRO members and was not sold on the merchant market. All follow-on PA-8x00 processors are based on the basic PA-8000 processor core.
The UltraSPARC III, code-named "Cheetah", is a microprocessor that implements the SPARC V9 instruction set architecture (ISA) developed by Sun Microsystems and fabricated by Texas Instruments. It was introduced in 2001 and operates at 600 to 900 MHz. It was succeeded by the UltraSPARC IV in 2004. Gary Lauterbach was the chief architect.
The TurboSPARC is a microprocessor that implements the SPARC V8 instruction set architecture (ISA) developed by Fujitsu Microelectronics, Inc. (FMI), the United States subsidiary of the Japanese multinational information technology equipment and services company Fujitsu Limited located in San Jose, California. It was a low-end microprocessor primarily developed as an upgrade for the Sun Microsystems microSPARC-II-based SPARCstation 5 workstation. It was introduced on 30 September 1996, with a 170 MHz version priced at US$499 in quantities of 1,000. The TurboSPARC was mostly succeeded in the low-end SPARC market by the UltraSPARC IIi in late 1997, but remained available.
The PA-7100LC is a microprocessor that implements the PA-RISC 1.1 instruction set architecture (ISA) developed by Hewlett-Packard (HP). It is also known as the PCX-L, and by its code-name, Hummingbird. It was designed as a low-cost microprocessor for low-end systems. The first systems to feature the PA-7100LC were introduced in January 1994. These systems used 60 and 80 MHz parts. A 100 MHz part debuted in June 1994. The PA-7100LC was the first PA-RISC microprocessor to implement the MAX-1 multimedia instructions, an early single instruction, multiple data (SIMD) multimedia instruction set extension that provided instructions for improving the performance of MPEG video decoding.
The R4600, code-named "Orion", is a microprocessor developed by Quantum Effect Design (QED) that implemented the MIPS III instruction set architecture (ISA). As QED was a design firm that did not fabricate or sell their designs, the R4600 was first licensed to Integrated Device Technology (IDT), and later to Toshiba and then NKK. These companies fabricated the microprocessor and marketed it. The R4600 was designed as a low-end workstation or high-end embedded microprocessor. Users included Silicon Graphics, Inc. (SGI) for their Indy workstation and DeskStation Technology for their Windows NT workstations. The R4600 was instrumental in making the Indy successful by providing good integer performance at a competitive price. In embedded systems, prominent users included Cisco Systems in their network routers and Canon in their printers.
