The CVAX is a microprocessor chipset developed and fabricated by Digital Equipment Corporation (DEC) that implemented the VAX instruction set architecture (ISA). The chipset consisted of the CVAX 78034 CPU, CFPA floating-point accelerator, CVAX clock chip, and the associated support chips, the CVAX System Support Chip (CSSC), CVAX Memory Controller (CMCTL), and CVAX Q-Bus Interface Chip (CQBIC).
The CVAX 78034, also known as the MicroVAX 78034, is a second-generation single-chip VAX microprocessor. Systems featuring the CVAX chip set became available in late 1987. It is clocked at frequencies of 12.5 MHz (80 ns) in higher-end systems such as the VAX 6000 Model 200 and at 11.11 MHz (90 ns) in lower-end systems such as the MicroVAX 3500 and 3600. [1]
The 78034 was the first VAX microprocessor to have internal caches, a 1 KB combined instruction and data stream cache. [1] The cache is quite unusual as it is implemented with one-transistor DRAM, [1] whereas the majority of microprocessors use SRAM for their internal caches. This was the first microprocessor to use one-transistor DRAM for cache. [1] DEC chose to use DRAM for the cache to reduce the area of the cache array. The designers concluded that to implement this cache with four-transistor DRAM cells or six-transistor SRAM cells would have taken 2.4 to 3 times more area. [1] The internal cache is located in a narrow strip along the left side of the die. An external 64 KB cache complements the 1 KB internal cache.
The 78034 contains 134,000 transistors on a die measuring 9.7 by 7.4 mm (71.78 mm2). It is fabricated in DEC's first-generation CMOS process, CMOS-1, a 2.0 μm CMOS process with two layers of aluminium interconnect. The 78034 is packaged in an 84-pin ceramic chip carrier with a heat sink. It uses single +5 volt power supply and dissipates a maximum of 1.5 W. [1]
The microprocessor is microprogrammed and partially pipelined and consists of six major functional units, the I-Box, E-Box, M-box, bus interface unit (BIU), cache, and control store and microsequencer. The I-Box fetches VAX instructions from the cache and decodes them (parses) into macroinstructions. The I-Box has an IROM (Instruction decode ROM) that holds the information required to do so.
The E-Box consists of a register file, a 32-bit program counter, a constant generator, a shifter and an arithmetic logic unit (ALU). The register file contains 31 single-read-port/single-write-port registers and eight dual-read-port/single-write port registers. The ALU is 32-bit and is capable of executing addition, subtraction and logic instructions. Although the E-Box contains a dedicated shifter, the ALU also features a shifter, a less powerful one, for the purpose of executing integer multiply and divide instructions. The design of the register file permits these execution units to achieve higher performance by permitting more instances of simultaneous access to the registers.
The M-Box is the memory management unit. It has a 28-entry fully associative translation look-aside buffer (TLB) to translate virtual addresses into physical address. In addition to the TLB, it has registers that determine the memory address to read or write to. The M-Box works closely with the BIU, which controls access to the internal cache and interfaces the microprocessor to the 32-bit address data multiplexed external bus.
The control store and microsequencer provides the means of controls of the operation of the other functional units with microcode. The control store has a ROM containing 1,600 41-bit words. Each 41-bit word is divided into two, a 28-bit field that controls the functional units, and a 13-bit field that controls the microsequencer. Unlike the MicroVAX 78032, which uses X-shaped cells, the 78034 uses conventional H-shaped cells. The microsequencer's purpose is to supply microaddresses to the control store.
The CFPA (CVAX Floating Point Accelerator) is a floating point coprocessor for the CVAX 78034.
The CFPA contains 65,000 transistors on a die measuring 7.3 by 9.1 mm (66.43 mm2). It is fabricated in DEC's first-generation CMOS process, CMOS-1, a 2.0 μm process with two layers of aluminium interconnect. It is packaged in a 68-pin surface mountable chip carrier. [2]
CVAX+ referred to an optical shrink of the original CVAX fabricated in DEC's second-generation CMOS process, CMOS-2, a 1.5 μm process with two levels of wiring. The original design team shrunk the CVAX 78034, CFPA and CMCTL, with the other chips left unchanged. The shrunk 78034 was known as the CVAX-60, which taped out in August 1987, before the original 78034 begun volume production, and the CFPA-60 taped out in November 1987. The CVAX+ operated at 16.67 MHz, but power requirements was unchanged.
The CVAX+ started to ship in late 1988, as upgrades to all entry-level CVAX-based systems and were also provided as an upgrade to the VAX 6000 when the introduction of Rigel was delayed by yield issues.
SOC referred to a microprocessor which contained the CVAX 78034, CFPA, clock chip, and an 8 KB second level cache on a single die. Operating at 25 or 28.5 MHz, it was introduced in 1990 and used in entry-level servers, workstations, VXT-2000 X terminals, and as an embedded microprocessor in DEC's high-end printers and terminals. It was fabricated in DEC's third-generation CMOS process, CMOS-3, a 1.0 μm process with three levels of wiring.
The StrongARM is a family of computer microprocessors developed by Digital Equipment Corporation and manufactured in the late 1990s which implemented the ARM v4 instruction set architecture. It was later acquired by Intel in 1997 from DEC's own Digital Semiconductor division as part of a settlement of a lawsuit between the two companies over patent infringement. Intel then continued to manufacture it before replacing it with the StrongARM-derived ARM-based follow-up architecture called XScale in the early 2000s.
The UltraSPARC is a microprocessor developed by Sun Microsystems and fabricated by Texas Instruments, introduced in mid-1995. It is the first microprocessor from Sun to implement the 64-bit SPARC V9 instruction set architecture (ISA). Marc Tremblay was a co-microarchitect.
The POWER1 is a multi-chip CPU developed and fabricated by IBM that implemented the POWER instruction set architecture (ISA). It was originally known as the RISC System/6000 CPU or, when in an abbreviated form, the RS/6000 CPU, before introduction of successors required the original name to be replaced with one that used the same naming scheme (POWERn) as its successors in order to differentiate it from the newer designs.
SPARC64 is a microprocessor developed by HAL Computer Systems and fabricated by Fujitsu. It implements the SPARC V9 instruction set architecture (ISA), the first microprocessor to do so. SPARC64 was HAL's first microprocessor and was the first in the SPARC64 brand. It operates at 101 and 118 MHz. The SPARC64 was used exclusively by Fujitsu in their systems; the first systems, the Fujitsu HALstation Model 330 and Model 350 workstations, were formally announced in September 1995 and were introduced in October 1995, two years late. It was succeeded by the SPARC64 II in 1996.
The POWER3 is a microprocessor, designed and exclusively manufactured by IBM, that implemented the 64-bit version of the PowerPC instruction set architecture (ISA), including all of the optional instructions of the ISA such as instructions present in the POWER2 version of the POWER ISA but not in the PowerPC ISA. It was introduced on 5 October 1998, debuting in the RS/6000 43P Model 260, a high-end graphics workstation. The POWER3 was originally supposed to be called the PowerPC 630 but was renamed, probably to differentiate the server-oriented POWER processors it replaced from the more consumer-oriented 32-bit PowerPCs. The POWER3 was the successor of the P2SC derivative of the POWER2 and completed IBM's long-delayed transition from POWER to PowerPC, which was originally scheduled to conclude in 1995. The POWER3 was used in IBM RS/6000 servers and workstations at 200 MHz. It competed with the Digital Equipment Corporation (DEC) Alpha 21264 and the Hewlett-Packard (HP) PA-8500.
The NVAX is a CMOS microprocessor developed and produced by Digital Equipment Corporation (DEC) that implemented the VAX instruction set architecture (ISA). A variant of the NVAX, the NVAX+, differed in the bus interface and external cache supported, but was otherwise identical in regards to microarchitecture. The NVAX+ was designed to have the same bus as the DECchip 21064, allowing drop-in replacement.
The R10000, code-named "T5", is a RISC microprocessor implementation of the MIPS IV instruction set architecture (ISA) developed by MIPS Technologies, Inc. (MTI), then a division of Silicon Graphics, Inc. (SGI). The chief designers are Chris Rowen and Kenneth C. Yeager. The R10000 microarchitecture is known as ANDES, an abbreviation for Architecture with Non-sequential Dynamic Execution Scheduling. The R10000 largely replaces the R8000 in the high-end and the R4400 elsewhere. MTI was a fabless semiconductor company; the R10000 was fabricated by NEC and Toshiba. Previous fabricators of MIPS microprocessors such as Integrated Device Technology (IDT) and three others did not fabricate the R10000 as it was more expensive to do so than the R4000 and R4400.
The R4000 is a microprocessor developed by MIPS Computer Systems that implements the MIPS III instruction set architecture (ISA). Officially announced on 1 October 1991, it was one of the first 64-bit microprocessors and the first MIPS III implementation. In the early 1990s, when RISC microprocessors were expected to replace CISC microprocessors such as the Intel i486, the R4000 was selected to be the microprocessor of the Advanced Computing Environment (ACE), an industry standard that intended to define a common RISC platform. ACE ultimately failed for a number of reasons, but the R4000 found success in the workstation and server markets.
The POWER2, originally named RIOS2, is a processor designed by IBM that implemented the POWER instruction set architecture. The POWER2 was the successor of the POWER1, debuting in September 1993 within IBM's RS/6000 systems. When introduced, the POWER2 was the fastest microprocessor, surpassing the Alpha 21064. When the Alpha 21064A was introduced in 1993, the POWER2 lost the lead and became second. IBM claimed that the performance for a 62.5 MHz POWER2 was 73.3 SPECint92 and 134.6 SPECfp92.
The PowerPC 600 family was the first family of PowerPC processors built. They were designed at the Somerset facility in Austin, Texas, jointly funded and staffed by engineers from IBM and Motorola as a part of the AIM alliance. Somerset was opened in 1992 and its goal was to make the first PowerPC processor and then keep designing general purpose PowerPC processors for personal computers. The first incarnation became the PowerPC 601 in 1993, and the second generation soon followed with the PowerPC 603, PowerPC 604 and the 64-bit PowerPC 620.
The V-11, code-named "Scorpio", is a miniprocessor chip set implementation of the VAX instruction set architecture (ISA) developed and fabricated by Digital Equipment Corporation (DEC).
The Alpha 21064 is a microprocessor developed and fabricated by Digital Equipment Corporation that implemented the Alpha instruction set architecture (ISA). It was introduced as the DECchip 21064 before it was renamed in 1994. The 21064 is also known by its code name, EV4. It was announced in February 1992 with volume availability in September 1992. The 21064 was the first commercial implementation of the Alpha ISA, and the first microprocessor from Digital to be available commercially. It was succeeded by a derivative, the Alpha 21064A in October 1993. This last version was replaced by the Alpha 21164 in 1995.
The Alpha 21164, also known by its code name, EV5, is a microprocessor developed and fabricated by Digital Equipment Corporation that implemented the Alpha instruction set architecture (ISA). It was introduced in January 1995, succeeding the Alpha 21064A as Digital's flagship microprocessor. It was succeeded by the Alpha 21264 in 1998.
The Alpha 21264 is a Digital Equipment Corporation RISC microprocessor launched on 19 October 1998. The 21264 implemented the Alpha instruction set architecture (ISA).
The MicroVAX 78032 is a microprocessor developed and fabricated by Digital Equipment Corporation (DEC) that implements a subset of the VAX instruction set architecture (ISA). The 78032 is used exclusively in DEC's VAX-based systems, starting with the MicroVAX II in 1985. When clocked at a frequency of 5 MHz, the 78032's integer performance is comparable to the original VAX-11/780 of 1977. The microprocessor can be paired with the MicroVAX 78132 floating point accelerator for improved floating point performance.
Rigel was a microprocessor chip set developed and fabricated by Digital Equipment Corporation (DEC) that implemented the VAX instruction set architecture (ISA). It was introduced on 11 July 1989 with the introduction of the VAX 6000 Model 400, the first system to feature the chip set. Rigel was also used in the VAX 4000 Model 300 and VAXstation 3100 Model 76. Production Rigel CPUs were rated at 35 to 43 MHz.
The SPARC64 V (Zeus) is a SPARC V9 microprocessor designed by Fujitsu. The SPARC64 V was the basis for a series of successive processors designed for servers, and later, supercomputers.
The PA-8000 (PCX-U), code-named Onyx, is a microprocessor developed and fabricated by Hewlett-Packard (HP) that implemented the PA-RISC 2.0 instruction set architecture (ISA). It was a completely new design with no circuitry derived from previous PA-RISC microprocessors. The PA-8000 was introduced on 2 November 1995 when shipments began to members of the Precision RISC Organization (PRO). It was used exclusively by PRO members and was not sold on the merchant market. All follow-on PA-8x00 processors are based on the basic PA-8000 processor core.
The UltraSPARC III, code-named "Cheetah", is a microprocessor that implements the SPARC V9 instruction set architecture (ISA) developed by Sun Microsystems and fabricated by Texas Instruments. It was introduced in 2001 and operates at 600 to 900 MHz. It was succeeded by the UltraSPARC IV in 2004. Gary Lauterbach was the chief architect.
The R2000 is a 32-bit microprocessor chip set developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture (ISA). Introduced in January 1986, it was the first commercial implementation of the MIPS architecture and the first commercial RISC processor available to all companies. The R2000 competed with Digital Equipment Corporation (DEC) VAX minicomputers and with Motorola 68000 and Intel Corporation 80386 microprocessors. R2000 users included Ardent Computer, DEC, Silicon Graphics, Northern Telecom and MIPS's own Unix workstations.
