NVAX

Last updated July 14, 2022

The NVAX is a CMOS microprocessor developed and produced by Digital Equipment Corporation (DEC) that implemented the VAX instruction set architecture (ISA). A variant of the NVAX, the NVAX+, differed in the bus interface and external cache supported, but was otherwise identical in regards to microarchitecture. The NVAX+ was designed to have the same bus as the DECchip 21064, allowing drop-in replacement.

The NVAX and NVAX+ was used in late-model VAX systems released in 1991 such as the MicroVAX 3100, VAXstation 4000, VAX 4000, VAX 6000, VAX 7000/10000 and VAXft. Although Digital updated the design throughout the early 1990s, the processors, and the VAX platform itself, were ultimately superseded by the introduction of the DECchip 21064, an implementation of the Alpha (then Alpha AXP) architecture, and the resulting systems in November 1992.

The NVAX was offered at a variety of clock speeds, 83.3 MHz (12 ns), 71 MHz (14 ns) and 62.5 MHz (16 ns), while the NVAX+ is clocked at a frequency of 90.9 MHz (11 ns). The NVAX offered about 25 VAX Unit of Performance (VUPs), while the NVAX+ was roughly 35 VUPs. This was only slightly less than the VAX 9000 mainframe's roughly 40 VUPs, but available in a desktop form factor.

The final model in the series was the NVAX++, or NV5, offering 50 VUPs. This was the last VAX processor, DEC had moved entirely to the DEC Alpha after that point.

Description

NVAX contained 1.3 million transistors on a die measuring 16.2 by 14.6 mm in size (236.52 mm²). The die was fabricated in Digital's fourth-generation CMOS process, CMOS-4, a 0.75 µm process with three layers of aluminium interconnect. The NVAX is packaged in a 339-pin pin grid array. The NVAX was offered at a variety of clock speeds, 83.3 MHz (12 ns), 71 MHz (14 ns) and 62.5 MHz (16 ns), while the NVAX+ is clocked at a frequency of 90.9 MHz (11 ns). The NVAX offered about 25 VAX Unit of Performance (VUPs).

The NVAX+, introduced at the same time, was identical in terms of the processor design but used a different bus, cache system and its external connection was a 431-pin array. These were identical to those on the Alpha, allowing an NVAX+ machine to be upgraded to an Alpha simply by changing the CPU. These changes also allowed it to operate with slightly higher performance, and the NVAX+ ran at roughly 35 VUPs. This was only slightly less than the VAX 9000 mainframe's roughly 40 VUPs.

In 1994, the NVAX++ (also known as NV5) was introduced in VAX 7000 Model 7x0 and VAX 10000 Model 7x0 systems. It operated at 133 MHz (7.5 ns) and was fabricated in Digital's fifth-generation CMOS process, CMOS-5, a 0.50 µm process. It improved performance to 50 VUPs. In 1996, a 170.9 MHz NV5 was introduced, used in the VAX 7000/10000 Model 8x0.

Microarchitecture

The NVAX is partitioned into five semi-autonomous units, the I-box, E-box, F-box, M-box and C-box. The NVAX is macropipelined. Multiple VAX macroinstructions are processed in parallel by autonomous units, which have their own micropipelines.

The I-box fetches and decodes VAX instructions. It also contains the 2 KB direct-mapped virtual instruction cache (VIC) and the 512-entry by 4-bit branch history table. The I-box aimed to fetch eight bytes of instruction data from the VIC during every cycle.

The E-box executes most non-floating-point instructions. It is controlled by microcode from a 1,600-word control store with the capability to patch 20 words.

The F-box executes floating-point instructions as well as 32-bit integer multiply instructions. It has a four-stage floating-point and integer multiply pipeline and a non-pipelined floating-point divider.

Related Research Articles

Alpha is a 64-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC). Alpha was designed to replace 32-bit VAX complex instruction set computers (CISC) and to be a highly competitive RISC processor for Unix workstations and similar markets.

VAX is a series of computers featuring a 32-bit instruction set architecture (ISA) and virtual memory that was developed and sold by Digital Equipment Corporation (DEC) in the late 20th century. The VAX-11/780, introduced October 25, 1977, was the first of a range of popular and influential computers implementing the VAX ISA. The VAX family was a huge success for DEC - over 100 models were introduced over the lifetime of the design, with the last members arriving in the early 1990s. The VAX was succeeded by the DEC Alpha, which included several features from VAX machines to make porting from the VAX easier.

The Pentium Pro is a sixth-generation x86 microprocessor developed and manufactured by Intel and introduced on November 1, 1995. It introduced the P6 microarchitecture and was originally intended to replace the original Pentium in a full range of applications. While the Pentium and Pentium MMX had 3.1 and 4.5 million transistors, respectively, the Pentium Pro contained 5.5 million transistors. Later, it was reduced to a more narrow role as a server and high-end desktop processor and was used in supercomputers like ASCI Red, the first computer to reach the trillion floating point operations per second (teraFLOPS) performance mark. The Pentium Pro was capable of both dual- and quad-processor configurations. It only came in one form factor, the relatively large rectangular Socket 8. The Pentium Pro was succeeded by the Pentium II Xeon in 1998.

The VAXstation is a discontinued family of workstation computers developed and manufactured by Digital Equipment Corporation using processors implementing the VAX instruction set architecture. VAXstation systems were typically shipped with either the OpenVMS or ULTRIX operating systems. Many members of the VAXstation family had corresponding MicroVAX variants, which primarily differ by the lack of graphics hardware.

The CVAX is a microprocessor chipset developed and fabricated by Digital Equipment Corporation (DEC) that implemented the VAX instruction set architecture (ISA). The chipset consisted of the CVAX 78034 CPU, CFPA floating-point accelerator, CVAX clock chip, and the associated support chips, the CVAX System Support Chip (CSSC), CVAX Memory Controller (CMCTL), and CVAX Q-Bus Interface Chip (CQBIC).

The MicroVAX is a discontinued family of low-cost minicomputers developed and manufactured by Digital Equipment Corporation (DEC). The first model, the MicroVAX I, was introduced in 1983. They used processors that implemented the VAX instruction set architecture (ISA) and were succeeded by the VAX 4000. Many members of the MicroVAX family had corresponding VAXstation variants, which primarily differ by the addition of graphics hardware. The MicroVAX family supports Digital's VMS and ULTRIX operating systems. Prior to VMS V5.0, MicroVAX hardware required a dedicated version of VMS named MicroVMS.

The DEC 4000 AXP is a series of departmental server computers developed and manufactured by Digital Equipment Corporation introduced on 10 November 1992. These systems formed part of the first generation of systems based on the 64-bit Alpha AXP architecture and at the time of introduction, ran Digital's OpenVMS AXP or OSF/1 AXP operating systems.

The V-11, code-named "Scorpio", is a miniprocessor chip set implementation of the VAX instruction set architecture (ISA) developed and fabricated by Digital Equipment Corporation (DEC).

The DEC 7000 AXP and DEC 10000 AXP are a series of high-end multiprocessor server computers developed and manufactured by Digital Equipment Corporation, introduced on 10 November 1992. These systems formed part of the first generation of systems based on the 64-bit Alpha AXP architecture and at the time of introduction, ran Digital's OpenVMS AXP operating system, with DEC OSF/1 AXP available in March 1993. They were designed in parallel with the VAX 7000 and VAX 10000 minicomputers, and are identical except for the processor module(s) and supported bus interfaces. A field upgrade from a VAX 7000/10000 to a DEC 7000/10000 AXP was possible by means of swapping the processor boards.

The VAX 4000 is a discontinued family of low-end minicomputers developed and manufactured by Digital Equipment Corporation using microprocessors implementing the VAX instruction set architecture (ISA). The VAX 4000 succeeded the MicroVAX family, and shipped with the OpenVMS operating system. It was the last family of low-end VAX systems, as the platform was discontinued by Compaq.

The VAX 6000 is a discontinued family of minicomputers developed and manufactured by Digital Equipment Corporation (DEC) using processors implementing the VAX instruction set architecture (ISA). Originally, the VAX 6000 was intended to be a mid-range VAX product line complementing the VAX 8000, but with the introduction of the VAX 6000 Model 400 series, the older VAX 8000 was discontinued in favor of the VAX 6000, which offered slightly higher performance for half the cost. The VAX 6000 family supports Digital's VMS and ULTRIX operating systems.

The VAX 7000 and VAX 10000 are a discontinued family of high-end multiprocessor minicomputers developed and manufactured by Digital Equipment Corporation (DEC), introduced in July 1992. These systems use NVAX microprocessors implementing the VAX instruction set architecture, and run the OpenVMS operating system.

The VAX 8000 is a discontinued family of superminicomputers developed and manufactured by Digital Equipment Corporation (DEC) using processors implementing the VAX instruction set architecture (ISA).

The VAX 9000 is a discontinued family of mainframe computers developed and manufactured by Digital Equipment Corporation (DEC) using custom ECL-based processors implementing the VAX instruction set architecture (ISA). Equipped with optional vector processors, they were marketed into the supercomputer space as well. As with other VAX systems, they were sold with either the VMS or Ultrix operating systems.

The VAXft was a family of fault-tolerant minicomputers developed and manufactured by Digital Equipment Corporation (DEC) using processors implementing the VAX instruction set architecture (ISA). "VAXft" stood for "Virtual Address Extension, fault tolerant". These systems ran the OpenVMS operating system, and were first supported by VMS 5.4. Two layered software products, VAXft System Services and VMS Volume Shadowing, were required to support the fault-tolerant features of the VAXft and for the redundancy of data stored on hard disk drives.

The Alpha 21064 is a microprocessor developed and fabricated by Digital Equipment Corporation that implemented the Alpha instruction set architecture (ISA). It was introduced as the DECchip 21064 before it was renamed in 1994. The 21064 is also known by its code name, EV4. It was announced in February 1992 with volume availability in September 1992. The 21064 was the first commercial implementation of the Alpha ISA, and the first microprocessor from Digital to be available commercially. It was succeeded by a derivative, the Alpha 21064A in October 1993.

The Alpha 21164, also known by its code name, EV5, is a microprocessor developed and fabricated by Digital Equipment Corporation that implemented the Alpha instruction set architecture (ISA). It was introduced in January 1995, succeeding the Alpha 21064A as Digital's flagship microprocessor. It was succeeded by the Alpha 21264 in 1998.

The Alpha 21264 is a Digital Equipment Corporation RISC microprocessor launched on 19 October 1998. The 21264 implemented the Alpha instruction set architecture (ISA).

Rigel was a microprocessor chip set developed and fabricated by Digital Equipment Corporation (DEC) that implemented the VAX instruction set architecture (ISA). It was introduced on 11 July 1989 with the introduction of the VAX 6000 Model 400, the first system to feature the chip set. Rigel was also used in the VAX 4000 Model 300 and VAXstation 3100 Model 76. Production Rigel CPUs were rated at 35 to 43 MHz.

Since 1985, many processors implementing some version of the MIPS architecture have been designed and used widely.

References

Uhler, Michael G. et al. "The NVAX and NVAX+ High-performance VAX Microprocessors". Digital Technical Journal, Volume 4, Number 3, Summer 1992. pp. 11–23.
Nuessgen, Marco. "VAX CPU Model Summary".

External links

This page is based on this Wikipedia article
Text is available under the CC BY-SA 4.0 license; additional terms may apply.
Images, videos and audio are available under their respective licenses.