This article needs additional citations for verification . (June 2013) (Learn how and when to remove this template message)
|Launched||November 1, 1995|
|Max. CPU clock rate||233 MHz to 1.40 GHz|
|FSB speeds||66 MHz to 133 MHz|
|L1 cache||Pentium Pro: 16 KB per core(8 KB I cache + 8 KB D cache) Pentium II/3: 32 KB(16 KB I cache + 16 KB D cache)|
|L2 cache||128 KB to 512 KB|
256 KB to 2048 KB (Xeon)
|Architecture and classification|
|Products, models, variants|
|Successor||NetBurst, Intel Core|
The P6 microarchitecture is the sixth-generation Intel x86 microarchitecture, implemented by the Pentium Pro microprocessor that was introduced in November 1995. It is frequently referred to as i686.It was succeeded by the NetBurst microarchitecture in 2000, but eventually revived in the Pentium M line of microprocessors. The successor to the Pentium M variant of the P6 microarchitecture is the Core microarchitecture which in turn is also derived from the P6 microarchitecture.
The P6 core was the sixth generation Intel microprocessor in the x86 line. The first implementation of the P6 core was the Pentium Pro CPU in 1995, the immediate successor to the original Pentium design (P5).
P6 processors dynamically translate IA-32 instructions into sequences of buffered RISC-like micro-operations, and then analyze and reorder the micro-operations in order to detect parallelizable operations that may be issued to more than one execution unit at once. The Pentium Pro was not the first x86 chip to use this technique — the NexGen Nx586, introduced in 1994, also used it — but it was the first Intel x86 chip to do so.
Some techniques first used in the x86 space in the P6 core include:
The P6 architecture lasted three generations from the Pentium Pro to Pentium III, and was widely known for low power consumption, excellent integer performance, and relatively high instructions per cycle (IPC). The P6 line of processing cores was succeeded with the NetBurst (P68) architecture which appeared with the introduction of Pentium 4. This was a completely different design based on the use of very long pipelines that favoured high clock speed at the cost of lower IPC, and higher power consumption.
|Launched||March 12, 2003|
|Max. CPU clock rate||600 MHz to 2.26 GHz|
|FSB speeds||400 MT/s to 533 MT/s|
|L1 cache||64KB (32 KB I Cache + 32 KB D cache)|
|L2 cache||512 KB to 2048 KB|
|Architecture and classification|
|Products, models, variants|
|Successor||Enhanced Pentium M|
Upon release of the Pentium 4-M and Mobile Pentium 4, it was quickly realized that the new mobile NetBurst processors were not ideal for mobile computing. The Netburst-based processors were simply not as efficient per clock or per watt compared to their P6 predecessors. Mobile Pentium 4 processors ran much hotter than Pentium III-M processors and didn't offer significant performance advantages. Its inefficiency affected not only the cooling system complexity, but also the all-important battery life.
Realizing their new microarchitecture wasn't the best choice for the mobile space, Intel went back to the drawing board for a design that would be optimally suited for this market segment. The result was a modernized P6 design called the Pentium M:
The Pentium M was the most power efficient x86 processor for notebooks for several years, consuming a maximum of 27 watts at maximum load and 4-5 watts while idle. The processing efficiency gains brought about by its modernization allowed it to rival the Mobile Pentium 4 clocked over 1 GHz higher (the fastest-clocked Mobile Pentium 4 compared to the fastest-clocked Pentium M) and equipped with much more memory and bus bandwidth. The first Pentium M family processors ("Banias") internally support PAE but do not show the PAE support flag in their CPUID information; this causes some operating systems (primarily Linux distributions) to refuse to boot on such processors since PAE support is required in their kernels.
|Max. CPU clock rate||1.06 GHz to 2.33 GHz|
|FSB speeds||533 MT/s to 667 MT/s|
|L1 cache||64 KB|
|L2 cache||1 MB to 2 MB|
2 MB (Xeon)
|Architecture and classification|
|Products, models, variants|
The Yonah CPU was launched in January 2006 under the Core brand. Single and dual-core mobile version were sold under the Core Solo, Core Duo, and Pentium Dual-Core brands, and a server version was released as Xeon LV. These processors provided partial solutions to some of the Pentium M's shortcomings by adding:
This resulted in the interim microarchitecture for low-voltage only CPUs, part way between P6 and the following Core microarchitecture.
On July 27, 2006, the Core microarchitecture, a derivative of P6, was launched in form of the Core 2 processor. Subsequently, more processors were released with the Core microarchitecture under Core 2, Xeon, Pentium and Celeron brand names. The Core microarchitecture is Intel's final mainstream processor line to use FSB, with all later Intel processors based on Nehalem and later Intel microarchitectures featuring an integrated memory controller and a QPI or DMI bus for communication with the rest of the system. Improvements relative to the Intel Core processors were:
While all these chips are technically derivatives of the Pentium Pro, the architecture has gone through several radical changes since its inception.
Celeron is a brand name given by Intel to a number of different low-end IA-32 and x86-64 computer microprocessor models targeted at low-cost personal computers.
Pentium 4 is a brand by Intel for an entire series of single-core CPUs for desktops, laptops and entry-level servers. The processors were shipped from November 20, 2000, until August 8, 2008. The production of Netburst processors was active from 2000 until May 21, 2010.
The Pentium II brand refers to Intel's sixth-generation microarchitecture ("P6") and x86-compatible microprocessors introduced on May 7, 1997. Containing 7.5 million transistors, the Pentium II featured an improved version of the first P6-generation core of the Pentium Pro, which contained 5.5 million transistors. However, its L2 cache subsystem was a downgrade when compared to the Pentium Pros.
The Pentium III brand refers to Intel's 32-bit x86 desktop and mobile microprocessors based on the sixth-generation P6 microarchitecture introduced on February 26, 1999. The brand's initial processors were very similar to the earlier Pentium II-branded microprocessors. The most notable differences were the addition of the Streaming SIMD Extensions (SSE) instruction set, and the introduction of a controversial serial number embedded in the chip during manufacturing.
The Pentium Pro is a sixth-generation x86 microprocessor developed and manufactured by Intel and introduced on November 1, 1995. It introduced the P6 microarchitecture and was originally intended to replace the original Pentium in a full range of applications. While the Pentium and Pentium MMX had 3.1 and 4.5 million transistors, respectively, the Pentium Pro contained 5.5 million transistors. Later, it was reduced to a more narrow role as a server and high-end desktop processor and was used in supercomputers like ASCI Red, the first computer to reach the teraFLOPS performance mark. The Pentium Pro was capable of both dual- and quad-processor configurations. It only came in one form factor, the relatively large rectangular Socket 8. The Pentium Pro was succeeded by the Pentium II Xeon in 1998.
The Pentium M is a family of mobile 32-bit single-core x86 microprocessors introduced in March 2003 and forming a part of the Intel Carmel notebook platform under the then new Centrino brand. The Pentium M processors had a maximum thermal design power (TDP) of 5–27 W depending on the model, and were intended for use in laptops. They evolved from the core of the last Pentium III–branded CPU by adding the front-side bus (FSB) interface of Pentium 4, an improved instruction decoding and issuing front end, improved branch prediction, SSE2 support, and a much larger cache. The first Pentium M–branded CPU, code-named Banias, was followed by Dothan. The Pentium M-branded processors were succeeded by the Core-branded dual-core mobile Yonah CPU with a modified microarchitecture.
Tejas was a code name for Intel's microprocessor, which was to be a successor to the latest Pentium 4 with the Prescott core and was sometimes referred to as Pentium V. Jayhawk was a code name for its Xeon counterpart. The cancellation of the processors in May 2004 underscored Intel's historical transition of its focus on single-core processors to multi-core processors.
Xeon is a brand of x86 microprocessors designed, manufactured, and marketed by Intel, targeted at the non-consumer workstation, server, and embedded system markets. It was introduced in June 1998. Xeon processors are based on the same architecture as regular desktop-grade CPUs, but have advanced features such as support for ECC memory, higher core counts, more PCI Express lanes, support for larger amounts of RAM, larger cache memory and extra provision for enterprise-grade reliability, availability and serviceability (RAS) features responsible for handling hardware exceptions through the Machine Check Architecture. They are often capable of safely continuing execution where a normal processor cannot due to these extra RAS features, depending on the type and severity of the machine-check exception (MCE). Some also support multi-socket systems with two, four, or eight sockets through use of the Quick Path Interconnect (QPI) bus.
The NetBurst microarchitecture, called P68 inside Intel, was the successor to the P6 microarchitecture in the x86 family of central processing units (CPUs) made by Intel. The first CPU to use this architecture was the Willamette-core Pentium 4, released on November 20, 2000 and the first of the Pentium 4 CPUs; all subsequent Pentium 4 and Pentium D variants have also been based on NetBurst. In mid-2004, Intel released the Foster core, which was also based on NetBurst, thus switching the Xeon CPUs to the new architecture as well. Pentium 4-based Celeron CPUs also use the NetBurst architecture.
The Intel Core microarchitecture is a multi-core processor microarchitecture unveiled by Intel in Q1 2006. It is based on the Yonah processor design and can be considered an iteration of the P6 microarchitecture introduced in 1995 with Pentium Pro. High power consumption and heat intensity, the resulting inability to effectively increase clock rate, and other shortcomings such as an inefficient pipeline were the primary reasons why Intel abandoned the NetBurst microarchitecture and switched to a different architectural design, delivering high efficiency through a small pipeline rather than high clock rates. The Core microarchitecture initially did not reach the clock rates of the NetBurst microarchitecture, even after moving to 45 nm lithography. However after many generations of successor microarchitectures which used Core as their basis, Intel managed to eventually surpass the clock rates of Netburst with the Devil's Canyon microarchitecture reaching a base frequency of 4 GHz and a maximum tested frequency of 4.4 GHz using 22 nm lithography.
Yonah was the code name of Intel's first generation 65 nm process CPU cores, based on cores of the earlier Banias / Dothan Pentium M microarchitecture. Yonah CPU cores were used within Intel's Core Solo and Core Duo mobile microprocessor products. SIMD performance on Yonah improved through the addition of SSE3 instructions and improvements to SSE and SSE2 implementations; integer performance decreased slightly due to higher latency cache. Additionally, Yonah included support for the NX bit.
Pentium is a brand used for a series of x86 architecture-compatible microprocessors produced by Intel since 1993. In their form as of November 2011, Pentium processors are considered entry-level products that Intel rates as "two stars", meaning that they are above the low-end Atom and Celeron series, but below the faster Intel Core lineup, and workstation Xeon series.
The Pentium Dual-Core brand was used for mainstream x86-architecture microprocessors from Intel from 2006 to 2009 when it was renamed to Pentium. The processors are based on either the 32-bit Yonah or 64-bit Merom-2M, Allendale, and Wolfdale-3M core, targeted at mobile or desktop computers.
Conroe is the code name for many Intel processors sold as Core 2 Duo, Xeon, Pentium Dual-Core and Celeron. It was the first desktop processor to be based on the Core microarchitecture, replacing the NetBurst microarchitecture based Cedar Mill processor. It has product code 80557, which is shared with Allendale and Conroe-L that are very similar but have a smaller L2 cache. Conroe-L has only one processor core and a new CPUID model. The mobile version of Conroe is Merom, the dual-socket server version is Woodcrest, and the quad-core desktop version is Kentsfield. Conroe was replaced by the 45 nm Wolfdale processor.
Wolfdale is the code name for a processor from Intel that is sold in varying configurations as Core 2 Duo, Celeron, Pentium and Xeon. In Intel's Tick-Tock cycle, the 2007/2008 "Tick" was Penryn microarchitecture, the shrink of the Core microarchitecture to 45 nanometers as CPUID model 23. This replaced the Conroe processor with Wolfdale.
Yorkfield is the code name for some Intel processors sold as Core 2 Quad and Xeon. In Intel's Tick-Tock cycle, the 2007/2008 "Tick" was Penryn microarchitecture, the shrink of the Core microarchitecture to 45 nanometers as CPUID model 23, replacing Kentsfield, the previous model.
In Intel's Tick-Tock cycle, the 2007/2008 "Tick" was the shrink of the Core microarchitecture to 45 nanometers as CPUID model 23. In Core 2 processors, it is used with the code names Penryn, Wolfdale and Yorkfield, some of which are also sold as Celeron, Pentium and Xeon processors. In the Xeon brand, the Wolfdale-DP and Harpertown code names are used for LGA 771 based MCMs with two or four active Wolfdale cores.