Protected mode

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In computing, protected mode, also called protected virtual address mode, [1] is an operational mode of x86-compatible central processing units (CPUs). It allows system software to use features such as segmentation, virtual memory, paging and safe multi-tasking designed to increase an operating system's control over application software. [2] [3]

Contents

When a processor that supports x86 protected mode is powered on, it begins executing instructions in real mode, in order to maintain backward compatibility with earlier x86 processors. [4] Protected mode may only be entered after the system software sets up one descriptor table and enables the Protection Enable (PE) bit in the control register 0 (CR0). [5]

Protected mode was first added to the x86 architecture in 1982, [6] with the release of Intel's 80286 (286) processor, and later extended with the release of the 80386 (386) in 1985. [7] Due to the enhancements added by protected mode, it has become widely adopted and has become the foundation for all subsequent enhancements to the x86 (IA-32) architecture, [8] although many of those enhancements, such as added instructions and new registers, also brought benefits to the real mode.

History

The first x86 processor, the Intel 8086, had a 20-bit address bus for its memory, as did its Intel 8088 variant. [9] This allowed them to access 220 bytes of memory, equivalent to 1 megabyte. [9] At the time, 1 megabyte was considered a relatively large amount of memory, [10] so the designers of the IBM Personal Computer reserved the first 640 kilobytes for use by applications and the operating system and the remaining 384 kilobytes for the BIOS (Basic Input/Output System) and memory for add-on devices. [11]

As the cost of memory decreased and memory use increased, the 1 MB limitation became a significant problem. Intel intended to solve this limitation along with others with the release of the 286. [11]

The 286

The initial protected mode, released with the 286, was not widely used; [11] for example, it was used by Coherent (from 1982), [12] Microsoft Xenix (around 1984) [13] and Minix. [14] Several shortcomings such as the inability to make BIOS and DOS calls due to inability to switch back to real mode without resetting the processor prevented widespread usage. [15] Acceptance was additionally hampered by the fact that the 286 only allowed memory access in 64  kilobyte segments, addresed by its four segment registers, meaning that only 4 × 64 KB, equivalent to 256 KB, could be accessed at a time. [11] Because changing a segment register in protected mode caused a 6-byte segment descriptor to be loaded into the CPU from memory, the segment register load instruction took many tens of processor cycles, making it much slower than on the 8086 and 8088; therefore, the strategy of computing segment addresses on-the-fly in order to access data structures larger than 128  kilobytes (the combined size of the two data segments) became impractical, even for those few programmers who had mastered it on the 8086 and 8088.

The 286 maintained backward compatibility with the 8086 and 8088 by initially entering real mode on power up. [4] Real mode functioned virtually identically to the 8086 and 8088, allowing the vast majority of existing software for those processors to run unmodified on the newer 286. Real mode also served as a more basic mode in which protected mode could be set up, solving a sort of chicken-and-egg problem. To access the extended functionality of the 286, the operating system would set up some tables in memory that controlled memory access in protected mode, set the addresses of those tables into some special registers of the processor, and then set the processor into protected mode. This enabled 24-bit addressing, which allowed the processor to access 224 bytes of memory, equivalent to 16  megabytes. [9]

The 386

An Intel 80386 microprocessor Ic-photo-intel-A80386DX-33-IV-(386DX).png
An Intel 80386 microprocessor

With the release of the 386 in 1985, [7] many of the issues preventing widespread adoption of the previous protected mode were addressed. [11] The 386 was released with an address bus size of 32 bits, which allows for 232 bytes of memory accessing, equivalent to 4 gigabytes. [16] The segment sizes were also increased to 32 bits, meaning that the full address space of 4 gigabytes could be accessed without the need to switch between multiple segments. [16] In addition to the increased size of the address bus and segment registers, many other new features were added with the intention of increasing operational security and stability. [17] Protected mode is now used in virtually all modern operating systems which run on the x86 architecture, such as Microsoft Windows, Linux, and many others. [18]

Furthermore, learning from the failures of the 286 protected mode to satisfy the needs for multiuser DOS, Intel added a separate virtual 8086 mode, [19] which allowed multiple virtualized 8086 processors to be emulated on the 386. Hardware x86 virtualization required for virtualizing the protected mode itself, however, had to wait for another 20 years. [20]

386 additions to protected mode

With the release of the 386, the following additional features were added to protected mode: [2]

Entering and exiting protected mode

Until the release of the 386, protected mode did not offer a direct method to switch back into real mode once protected mode was entered. IBM devised a workaround (implemented in the IBM AT) which involved resetting the CPU via the keyboard controller and saving the system registers, stack pointer and often the interrupt mask in the real-time clock chip's RAM. This allowed the BIOS to restore the CPU to a similar state and begin executing code before the reset.[ clarification needed ] Later, a triple fault was used to reset the 286 CPU, which was a lot faster and cleaner than the keyboard controller method (and does not depend on IBM AT-compatible hardware, but will work on any 80286 CPU in any system).

To enter protected mode, the Global Descriptor Table (GDT) must first be created with a minimum of three entries: a null descriptor, a code segment descriptor and data segment descriptor. In an IBM-compatible machine, the A20 line (21st address line) also must be enabled to allow the use of all the address lines so that the CPU can access beyond 1 megabyte of memory (Only the first 20 are allowed to be used after power-up, to guarantee compatibility with older software written for the Intel 8088-based IBM PC and PC/XT models). [22] After performing those two steps, the PE bit must be set in the CR0 register and a far jump must be made to clear the prefetch input queue. [23] [24] 

; MASM program; enter protected mode (set PE bit)movEBX,CR0; save control register 0 (CR0) to EBXorEBX,PE_BIT; set PE bit by ORing, save to EBXmovCR0,EBX; save EBX back to CR0; clear prefetch queue; (using far jump instruction jmp)jmpCLEAR_LABELCLEAR_LABEL:

With the release of the 386, protected mode could be exited by loading the segment registers with real mode values, disabling the A20 line and clearing the PE bit in the CR0 register, without the need to perform the initial setup steps required with the 286. [25]

Features

Protected mode has a number of features designed to enhance an operating system's control over application software, in order to increase security and system stability. [3] These additions allow the operating system to function in a way that would be significantly more difficult or even impossible without proper hardware support. [26]

Privilege levels

Example of privilege ring usage in an operating system using all rings Priv rings.svg
Example of privilege ring usage in an operating system using all rings

In protected mode, there are four privilege levels or rings, numbered from 0 to 3, with ring 0 being the most privileged and 3 being the least. The use of rings allows for system software to restrict tasks from accessing data, call gates or executing privileged instructions. [27] In most environments, the operating system and some device drivers run in ring 0 and applications run in ring 3. [27]

Real mode application compatibility

According to the Intel 80286 Programmer's Reference Manual, [28]

the 80286 remains upwardly compatible with most 8086 and 80186 application programs. Most 8086 application programs can be re-compiled or re-assembled and executed on the 80286 in Protected Mode.

For the most part, the binary compatibility with real-mode code, the ability to access up to 16 MB of physical memory, and 1 GB of virtual memory, were the most apparent changes to application programmers. [29] This was not without its limitations. If an application utilized or relied on any of the techniques below, it would not run: [30]

In reality, almost all DOS application programs violated these rules. [32] Due to these limitations, virtual 8086 mode was introduced with the 386. Despite such potential setbacks, Windows 3.0 and its successors can take advantage of the binary compatibility with real mode to run many Windows 2.x (Windows 2.0 and Windows 2.1x) applications in protected mode, which ran in real mode in Windows 2.x. [33]

Virtual 8086 mode

With the release of the 386, protected mode offers what the Intel manuals call virtual 8086 mode. Virtual 8086 mode is designed to allow code previously written for the 8086 to run unmodified and concurrently with other tasks, without compromising security or system stability. [34]

Virtual 8086 mode, however, is not completely backward compatible with all programs. Programs that require segment manipulation, privileged instructions, direct hardware access, or use self-modifying code will generate an exception that must be served by the operating system. [35] In addition, applications running in virtual 8086 mode generate a trap with the use of instructions that involve input/output (I/O), which can negatively impact performance. [36]

Due to these limitations, some programs originally designed to run on the 8086 cannot be run in virtual 8086 mode. As a result, system software is forced to either compromise system security or backward compatibility when dealing with legacy software. An example of such a compromise can be seen with the release of Windows NT, which dropped backward compatibility for "ill-behaved" DOS applications. [37]

Segment addressing

Virtual segments of 80286 080810-protected-286-segments.PNG
Virtual segments of 80286

Real mode

In real mode each logical address points directly into a physical memory location, every logical address consists of two 16-bit parts: The segment part of the logical address contains the base address of a segment with a granularity of 16 bytes, i.e. a segment may start at physical address 0, 16, 32, ..., 220 − 16. The offset part of the logical address contains an offset inside the segment, i.e. the physical address can be calculated as physical_address = segment_part × 16 + offset, if the address line A20 is enabled, or (segment_part × 16 + offset) mod 220, if A20 is off.[ clarification needed ] Every segment has a size of 216 bytes.

Protected mode

In protected mode, the segment_part is replaced by a 16-bit selector, in which the 13 upper bits (bit 3 to bit 15) contain the index of an entry inside a descriptor table. The next bit (bit 2) specifies whether the operation is used with the GDT or the LDT. The lowest two bits (bit 1 and bit 0) of the selector are combined to define the privilege of the request, where the values of 0 and 3 represent the highest and the lowest privilege, respectively. This means that the byte offset of descriptors in the descriptor table is the same as the 16-bit selector, provided the lower three bits are zeroed.

The descriptor table entry defines the real linear address of the segment, a limit value for the segment size, and some attribute bits (flags).

286

The segment address inside the descriptor table entry has a length of 24 bits so every byte of the physical memory can be defined as bound of the segment. The limit value inside the descriptor table entry has a length of 16 bits so segment length can be between 1 byte and 216 byte. The calculated linear address equals the physical memory address.

386

The segment address inside the descriptor table entry is expanded to 32 bits so every byte of the physical memory can be defined as bound of the segment. The limit value inside the descriptor table entry is expanded to 20 bits and completed with a granularity flag (G-bit, for short):

  • If G-bit is zero limit has a granularity of 1 byte, i.e. segment size may be 1, 2, ..., 220 bytes.
  • If G-bit is one limit has a granularity of 212 bytes, i.e. segment size may be 1 × 212, 2 × 212, ..., 220 × 212 bytes. If paging is off, the calculated linear address equals the physical memory address. If paging is on, the calculated linear address is used as input of paging.

The 386 processor also uses 32 bit values for the address offset.

For maintaining compatibility with 286 protected mode a new default flag (D-bit, for short) was added. If the D-bit of a code segment is off (0) all commands inside this segment will be interpreted as 16-bit commands by default; if it is on (1), they will be interpreted as 32-bit commands.

Structure of segment descriptor entry

80286 Segment descriptor
3130292827262524232221201918171615141312111009080706050403020100
Base[0..15]Limit[0..15]
6362616059585756555453525150494847464544434241403938373635343332
UnusedPDPLSXCRABase[16..23]
80386 Segment descriptor
3130292827262524232221201918171615141312111009080706050403020100
Base[0..15]Limit[0..15]
6362616059585756555453525150494847464544434241403938373635343332
Base[24..31]GD0ULimit[16..19]PDPLSXCRABase[16..23]

Where:

  • A is the Accessed bit;
  • R is the Readable bit;
  • C (Bit 42) depends on X: [38]
    • if X = 1 then C is the Conforming bit, and determines which privilege levels can far-jump to this segment (without changing privilege level):
      • if C = 0 then only code with the same privilege level as DPL may jump here;
      • if C = 1 then code with the same or a lower privilege level relative to DPL may jump here.
    • if X = 0 then C is the direction bit:
      • if C = 0 then the segment grows up;
      • if C = 1 then the segment grows down.
  • X is the Executable bit: [38]
    • if X = 1 then the segment is a code segment;
    • if X = 0 then the segment is a data segment.
  • S is the Segment type bit, which should generally be cleared for system segments; [38]
  • DPL is the Descriptor Privilege Level;
  • P is the Present bit;
  • D is the Default operand size;
  • G is the Granularity bit;
  • Bit 52 of the 80386 descriptor is not used by the hardware.

Paging

Common method of using paging to create a virtual address space Virtual address space and physical address space relationship.svg
Common method of using paging to create a virtual address space
Paging (on Intel 80386) with page size of 4K 080810-protected-386-paging.svg
Paging (on Intel 80386) with page size of 4K

In addition to adding virtual 8086 mode, the 386 also added paging to protected mode. [39] Through paging, system software can restrict and control a task's access to pages, which are sections of memory. In many operating systems, paging is used to create an independent virtual address space for each task, preventing one task from manipulating the memory of another. Paging also allows for pages to be moved out of primary storage and onto a slower and larger secondary storage, such as a hard disk drive. [40] This allows for more memory to be used than physically available in primary storage. [40]

The x86 architecture allows control of pages through two arrays: page directories and page tables. Originally, a page directory was the size of one page, four kilobytes, and contained 1,024 page directory entries (PDE), although subsequent enhancements to the x86 architecture have added the ability to use larger page sizes. Each PDE contained a pointer to a page table. A page table was also originally four kilobytes in size and contained 1,024 page table entries (PTE). Each PTE contained a pointer to the actual page's physical address and are only used when the four-kilobyte pages are used. At any given time, only one page directory may be in active use. [41]

Multitasking

Through the use of the rings, privileged call gates, and the Task State Segment (TSS), introduced with the 286, preemptive multitasking was made possible on the x86 architecture. The TSS allows general-purpose registers, segment selector fields, and stacks to all be modified without affecting those of another task. The TSS also allows a task's privilege level, and I/O port permissions to be independent of another task's.

In many operating systems, the full features of the TSS are not used. [42] This is commonly due to portability concerns or due to the performance issues created with hardware task switches. [42] As a result, many operating systems use both hardware and software to create a multitasking system. [43]

Operating systems

Operating systems like OS/2 1.x try to switch the processor between protected and real modes. This is both slow and unsafe, because a real mode program can easily crash a computer. OS/2 1.x defines restrictive programming rules allowing a Family API or bound program to run in either real or protected mode. Some early Unix operating systems, OS/2  1.x, and Windows used this mode.

Windows 3.0 was able to run real mode programs in 16-bit protected mode; when switching to protected mode, it decided to preserve the single privilege level model that was used in real mode, which is why Windows applications and DLLs can hook interrupts and do direct hardware access. That lasted through the Windows 9x series. If a Windows 1.x or 2.x program is written properly and avoids segment arithmetic, it will run the same way in both real and protected modes. Windows programs generally avoid segment arithmetic because Windows implements a software virtual memory scheme, moving program code and data in memory when programs are not running, so manipulating absolute addresses is dangerous; programs should only keep handles to memory blocks when not running. Starting an old program while Windows 3.0 is running in protected mode triggers a warning dialog, suggesting to either run Windows in real mode or to obtain an updated version of the application. Updating well-behaved programs using the MARK utility with the MEMORY parameter avoids this dialog. It is not possible to have some GUI programs running in 16-bit protected mode and other GUI programs running in real mode. In Windows 3.1, real mode was no longer supported and could not be accessed.

In modern 32-bit operating systems, virtual 8086 mode is still used for running applications, e.g. DPMI compatible DOS extender programs (through virtual DOS machines) or Windows 3.x applications (through the Windows on Windows subsystem) and certain classes of device drivers (e.g. for changing the screen-resolution using BIOS functionality) in OS/2 2.0 (and later OS/2) and 32-bit Windows NT, all under control of a 32-bit kernel. However, 64-bit operating systems (which run in long mode) no longer use this, since virtual 8086 mode has been removed from long mode.

See also

Related Research Articles

IA-32 is the 32-bit version of the x86 instruction set architecture, designed by Intel and first implemented in the 80386 microprocessor in 1985. IA-32 is the first incarnation of x86 that supports 32-bit computing; as a result, the "IA-32" term may be used as a metonym to refer to all x86 versions that support 32-bit computing.

<span class="mw-page-title-main">Intel 80286</span> Microprocessor model

The Intel 80286 is a 16-bit microprocessor that was introduced on February 1, 1982. It was the first 8086-based CPU with separate, non-multiplexed address and data buses and also the first with memory management and wide protection abilities. The 80286 used approximately 134,000 transistors in its original nMOS (HMOS) incarnation and, just like the contemporary 80186, it can correctly execute most software written for the earlier Intel 8086 and 8088 processors.

i386 32-bit microprocessor by Intel

The Intel 386, originally released as 80386 and later renamed i386, is a 32-bit microprocessor designed by Intel. The first pre-production samples of the 386 were released to select developers in 1985, while mass production commenced in 1986. The processor was a significant evolution in the x86 architecture, extending a long line of processors that stretched back to the Intel 8008. The 386 was the central processing unit (CPU) of many workstations and high-end personal computers of the time. The 386 began to fall out of public use starting with the release of the i486 processor in 1989, while in embedded systems the 386 remained in widespread use until Intel finally discontinued it in 2007.

x86 Family of instruction set architectures

x86 is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel based on the 8086 microprocessor and its 8-bit-external-bus variant, the 8088. The 8086 was introduced in 1978 as a fully 16-bit extension of 8-bit Intel's 8080 microprocessor, with memory segmentation as a solution for addressing more memory than can be covered by a plain 16-bit address. The term "x86" came into being because the names of several successors to Intel's 8086 processor end in "86", including the 80186, 80286, 80386 and 80486. Colloquially, their names were "186", "286", "386" and "486".

Real mode, also called real address mode, is an operating mode of all x86-compatible CPUs. The mode gets its name from the fact that addresses in real mode always correspond to real locations in memory. Real mode is characterized by a 20-bit segmented memory address space and unlimited direct software access to all addressable memory, I/O addresses and peripheral hardware. Real mode provides no support for memory protection, multitasking, or code privilege levels.

The Intel x86 computer instruction set architecture has supported memory segmentation since the original Intel 8086 in 1978. It allows programs to address more than 64 KB (65,536 bytes) of memory, the limit in earlier 80xx processors. In 1982, the Intel 80286 added support for virtual memory and memory protection; the original mode was renamed real mode, and the new version was named protected mode. The x86-64 architecture, introduced in 2003, has largely dropped support for segmentation in 64-bit mode.

x86 assembly language is the name for the family of assembly languages which provide some level of backward compatibility with CPUs back to the Intel 8008 microprocessor, which was launched in April 1972. It is used to produce object code for the x86 class of processors.

x86-64 64-bit version of x86 architecture

x86-64 is a 64-bit version of the x86 instruction set, first announced in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging mode.

In computing, Physical Address Extension (PAE), sometimes referred to as Page Address Extension, is a memory management feature for the x86 architecture. PAE was first introduced by Intel in the Pentium Pro, and later by AMD in the Athlon processor. It defines a page table hierarchy of three levels (instead of two), with table entries of 64 bits each instead of 32, allowing these CPUs to directly access a physical address space larger than 4 gigabytes (232 bytes).

<span class="mw-page-title-main">Extended memory</span>

In DOS memory management, extended memory refers to memory above the first megabyte (220 bytes) of address space in an IBM PC or compatible with an 80286 or later processor. The term is mainly used under the DOS and Windows operating systems. DOS programs, running in real mode or virtual x86 mode, cannot directly access this memory, but are able to do so through an application programming interface (API) called the Extended Memory Specification (XMS). This API is implemented by a driver (such as HIMEM.SYS) or the operating system kernel, which takes care of memory management and copying memory between conventional and extended memory, by temporarily switching the processor into protected mode. In this context, the term "extended memory" may refer to either the whole of the extended memory or only the portion available through this API.

The x86 instruction set refers to the set of instructions that x86-compatible microprocessors support. The instructions are usually part of an executable program, often stored as a computer file and executed on the processor.

In the 80386 microprocessor and later, virtual 8086 mode allows the execution of real mode applications that are incapable of running directly in protected mode while the processor is running a protected mode operating system. It is a hardware virtualization technique that allowed multiple 8086 processors to be emulated by the 386 chip. It emerged from the painful experiences with the 80286 protected mode, which by itself was not suitable to run concurrent real-mode applications well. John Crawford developed the Virtual Mode bit at the register set, paving the way to this environment.

In x86 computing, unreal mode, also big real mode, flat real mode, or voodoo mode is a variant of real mode, in which one or more segment descriptors has been loaded with non-standard values, like 32-bit limits allowing access to the entire memory. Contrary to its name, it is not a separate addressing mode that the x86 processors can operate in. It is used in the 80286 and later x86 processors.

Memory segmentation is an operating system memory management technique of dividing a computer's primary memory into segments or sections. In a computer system using segmentation, a reference to a memory location includes a value that identifies a segment and an offset within that segment. Segments or sections are also used in object files of compiled programs when they are linked together into a program image and when the image is loaded into memory.

Virtual DOS machines (VDM) refer to a technology that allows running 16-bit/32-bit DOS and 16-bit Windows programs when there is already another operating system running and controlling the hardware.

LOADALL is the common name for two different, undocumented machine instructions of Intel 80286 and Intel 80386 processors, which allow access to areas of the internal processor state that are normally outside of the IA-32 API scope, like descriptor cache registers. The LOADALL for 286 processors is encoded 0Fh 05h, while the LOADALL for 386 processors is 0Fh 07h.

In computing, the reset vector is the default location a central processing unit will go to find the first instruction it will execute after a reset. The reset vector is a pointer or address, where the CPU should always begin as soon as it is able to execute instructions. The address is in a section of non-volatile memory initialized to contain instructions to start the operation of the CPU, as the first step in the process of booting the system containing the CPU.

In the x86-64 computer architecture, long mode is the mode where a 64-bit operating system can access 64-bit instructions and registers. 64-bit programs are run in a sub-mode called 64-bit mode, while 32-bit programs and 16-bit protected mode programs are executed in a sub-mode called compatibility mode. Real mode or virtual 8086 mode programs cannot be natively run in long mode.

The interrupt descriptor table (IDT) is a data structure used by the x86 architecture to implement an interrupt vector table. The IDT is used by the processor to determine the memory addresses of the handlers to be executed on interrupts and exceptions.

The maximum random access memory (RAM) installed in any computer system is limited by hardware, software and economic factors. The hardware may have a limited number of address bus bits, limited by the processor package or design of the system. Some of the address space may be shared between RAM, peripherals, and read-only memory. In the case of a microcontroller with no external RAM, the size of the RAM array is limited by the size of the integrated circuit die. In a packaged system, only enough RAM may be provided for the system's required functions, with no provision for addition of memory after manufacture.

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  33. ↑ Robinson, Tim (August 26, 2002). "Virtual 8086 Mode". berliOS. Archived from the original (Guide) on October 3, 2002. Retrieved 2007-07-25.
  34. ↑ Intel 64 and IA-32 Architectures Software Developer's Manual Combined Volumes 3A, 3B, 3C, and 3D: System Programming Guide. Intel. May 2019. Section 20.2 Virtual 8086 Mode.
  35. ↑ Intel 64 and IA-32 Architectures Software Developer's Manual Combined Volumes 3A, 3B, 3C, and 3D: System Programming Guide. Intel. May 2019. Section 20.2.7 Sensitive Instructions.
  36. ↑ Robinson, Tim (August 26, 2002). "Virtual 8086 Mode". berliOS. Archived from the original (Guide) on October 3, 2002. Retrieved 2007-07-25. A downside to using V86 mode is speed: every IOPL-sensitive instruction will cause the CPU to trap to kernel mode, as will I/O to ports which are masked out in the TSS.
  37. ↑ Dabak, Prasad; Millind Borate (October 1999). Undocumented Windows NT (Book). Hungry Minds. ISBN   0-7645-4569-8.
  38. 1 2 3 "Global Descriptor table - OSDev Wiki".
  39. ↑ "ProtectedMode overview [deinmeister.de]" (Website). Retrieved 2007-07-29.
  40. 1 2 "What Is PAE X86?". Microsoft TechNet. May 28, 2003. Archived from the original (Article) on 2008-04-22. Retrieved 2007-07-29. The paging process allows the operating system to overcome the real physical memory limits. However, it also has a direct impact on performance because of the time necessary to write or retrieve data from disk.
  41. ↑ Gareau, Jean. "Advanced Embedded x86 Programming: Paging". Embedded.com. Archived from the original (Guide) on 2008-05-16. Retrieved 2007-07-29. Only one page directory may be active at a time, indicated by the CR3 register.
  42. 1 2 zwanderer (May 2, 2004). "news: Multitasking for x86 explained #1". NewOrer. NewOrder. Archived from the original (Article) on 2007-02-12. Retrieved 2007-07-29. The reason why software task switching is so popular is that it can be faster than hardware task switching. Intel never actually developed the hardware task switching, they implemented it, saw that it worked, and just left it there. Advances in multitasking using software have made this form of task switching faster (some say up to 3 times faster) than the hardware method. Another reason is that the Intel way of switching tasks isn't portable at all
  43. ↑ zwanderer (May 2, 2004). "news: Multitasking for x86 explained #1". NewOrer. NewOrder. Archived from the original (Article) on 2007-02-12. Retrieved 2007-07-29. ... both rely on the Intel processors ability to switch tasks, they rely on it in different ways.
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