MMIX

Last updated
Mmix.png
Designer Donald Knuth
Bits64-bit
Introduced1999
Design RISC
Encoding Fixed
Branching Condition Code
Endianness Big
OpenYes, and royalty free
Registers
32 special-purpose registers
General-purpose 256

MMIX (pronounced em-mix) is a 64-bit reduced instruction set computing (RISC) architecture designed by Donald Knuth, with significant contributions by John L. Hennessy (who contributed to the design of the MIPS architecture) and Richard L. Sites (who was an architect of the Alpha architecture). Knuth has said that,

Contents

MMIX is a computer intended to illustrate machine-level aspects of programming. In my books The Art of Computer Programming , it replaces MIX, the 1960s-style machine that formerly played such a role… I strove to design MMIX so that its machine language would be simple, elegant, and easy to learn. At the same time I was careful to include all of the complexities needed to achieve high performance in practice, so that MMIX could in principle be built and even perhaps be competitive with some of the fastest general-purpose computers in the marketplace." [1]

Knuth started the design of MMIX in 1999, and released the stable version of the design in 2011. [2] The processor is numbered as "2009" with Knuth explaining that this is the arithmetic mean from the numbers of other computer architectures; as well as being "MMIX" in Roman numerals. [3]

Architecture

MMIX is a big-endian 64-bit reduced instruction set computer (RISC), with 256 64-bit general-purpose registers, 32 64-bit special-purpose registers, fixed-length 32-bit instructions and a 64-bit virtual address space. The MMIX instruction set comprises 256 opcodes, one of which is reserved for future expansion.[ citation needed ] MMIX uses IEEE 754 floating-point numbers.

Instructions

All instructions have an associated mnemonic. For example, instruction #20 (32 decimal) is associated with ADD. Most instructions have the symbolic form OP X,Y,Z, where OP specifies the sort of instruction, X specifies the register used to store the result of the instruction and the rest specify the operands of the instruction. Each of these fields is eight bits wide. For example, ADD $0,$1,3 means "Set $0 to the sum of $1 and 3."

Most instructions can take either immediate values or register contents; thus a single instruction mnemonic may correspond to one of two opcodes.

MMIX programs are typically constructed using the MMIXAL assembly language. The below is a simple MMIXAL program, which prints the string "Hello, world!":

        LOC   #100                   % Set the address of the program                                      % initially to 0x100.  Main    GETA  $255,string            % Put the address of the string                                      % into register 255.          TRAP  0,Fputs,StdOut         % Write the string pointed to by                                      % register 255 to the standard                                      % output file.          TRAP  0,Halt,0               % End process.  string  BYTE  "Hello, world!",#a,0   % String to be printed.  #a is                                      % newline, 0 terminates the                                      % string.

Registers

There are 256 directly addressable general-purpose architectural registers in an MMIX chip, designated by $0 through $255, and 32 special-purpose architectural registers. The special-purpose registers can be accessed with the GET and PUT instructions. Two of the special registers, rL and rG, determine which of the general registers are local and which are global. All registers from $0... ([rL] − 1) are local registers, and represent a window into an internal stack of registers. [4] Registers from [rL]... ([rG] − 1) are "marginal registers", they always return 0 if they are used as a source in an operation. Using a marginal register as the destination of an operation will cause the machine to automatically increase rL to include that register. All registers [rG]... $255 are called global registers, and are not part of the register stack.

Local register stack

The local register stack provides each subroutine with its own rL local registers, designated by $0 through $(rL − 1). Whenever a subroutine is called, a number of local registers are pushed down the stack (by shifting the start of the window). The arguments of the called subroutine are left in the remaining local registers. When a subroutine finishes it pops the previously pushed registers. Because the internal stack can contain only a finite number of registers, it may be necessary to store a part of the stack in memory. [4] This is implemented with the special registers rO and rS which record which part of the local register stack is in memory and which part is still in local physical registers. The register stack provides for fast subroutine linkage.

Special registers

The 32 special physical architectural registers are as follows:

  2. rB, the bootstrap register (trip)
    3. When tripping, rB ← $255 and $255 ← rJ. Thus saving rJ in a general register.
  3. rD, the dividend register
    Unsigned integer divide uses this as the left half of the 128-bit input that is to be divided by the other operand.
  4. rE, the epsilon register
    Used for floating comparisons with respect to epsilon.
  5. rH, the himult register
    Used to store the left half of the 128-bit result of unsigned integer multiplication.
  6. rJ, the return-jump register
    Used to save the address of the next instruction by PUSHes and by POP to return from a PUSH.
  7. rM, the multiplex mask register
    Used by the multiplex instruction.
  8. rR, the remainder register
    Is set to the remainder of integer division.
  9. rBB, the bootstrap register (trap)
    When trapping, rBB ← $255 and $255 ← rJ. Thus saving rJ in a general register
  10. rC, the cycle counter
    Incremented every cycle.
  11. rN, the serial number
    A constant identifying this particular MMIX processor.
  12. rO, the register stack offset
    Used to implement the register stack.
  13. rS, the register stack pointer
    Used to implement the register stack.
  14. rI, the interval counter
    Decremented every cycle. Causes an interrupt when zero.
  15. rT, the trap address register
    Used to store the address of the trip vector.
  16. rTT, the dynamic trap address register
    Used to store the address of the trap vector.
  17. rK, the interrupt mask register
    Used to enable and disable specific interrupts.
  18. rQ, the interrupt request register
    Used to record interrupts as they occur.
  19. rU, the usage counter
    Used to keep a count of executed instructions.
  20. rV, the virtual translation register
    Used to translate virtual addresses to physical addresses. Contains the size and number of segments, the root location of the page table and the address space number.
  21. rG, the global threshold register
    All general registers references with a number greater or equal to rG refer to global registers.
  22. rL, the local threshold register
    All general registers references with a number smaller than rL refer to local registers.
  23. rA, the arithmetic status register
    Used to record, enable and disable arithmetic exception like overflow and divide by zero.
  24. rF, the failure location register
    Used to store the address of the instruction that caused a failure.
  25. rP, the prediction register
    Used by conditional swap (CSWAP).
  26. rW, the where-interrupted register (trip)
    Used, when tripping, to store the address of the instruction after the one that was interrupted.
  27. rX, the execution register (trip)
    Used, when tripping, to store the instruction that was interrupted.
  28. rY, the Y operand (trip)
    Used, when tripping, to store the Y operand of the interrupted instruction.
  29. rZ, the Z operand (trip)
    Used, when tripping, to store the Z operand of the interrupted instruction.
  30. rWW, the where-interrupted register (trap)
    Used, when trapping, to store the address of the instruction after the one that was interrupted.
  31. rXX, the execution register (trap)
    Used, when trapping, to store the instruction that was interrupted.
  32. rYY, the Y operand (trap)
    Used, when trapping, to store the Y operand of the interrupted instruction.
  33. rZZ, the Z operand (trap)
    Used, when trapping, to store the Z operand of the interrupted instruction.

Like programs running on almost all other CPUs, MMIX programs can be interrupted in several ways. External hardware, such as timers, are a common source of preemption interrupts. Many instructions cause an interrupt in certain exceptional cases; such as the memory protection page fault exceptions used to implement virtual memory, and floating point exception handling. MMIX has 2 kinds of interrupts: "trips" and "traps". The main difference between "trips" and "traps" is that traps send control to a "trap handler" program in the operating system (trapping), but trips send control to a "trip handler" program in the user application (tripping). Users can also force any interrupt handler to run with explicit software interrupt instructions TRIP and TRAP, similar to some kinds of trap in other computer systems. In particular, a system call from a user program to the operating system uses a TRAP instruction. [1] : 38 

Hardware implementations

As of October 2015, no known hardware implementations of the MMIX instruction set architecture exist. However, the fpgammix [5] project implements MMIX in Verilog, making it possible to implement using a field-programmable gate array.

Software tools

The MMIX instruction set architecture is supported by a number of software tools for computer architecture research and software development.

Simulators and assembler

Compiler

The GNU Compiler Collection includes an MMIX back-end for its C/C++ compilers, contributed by Hans-Peter Nilsson and part of the main GCC distribution since late 2001. As of November 2017, the MMIX back-end to GCC continues to be actively developed and maintained by volunteers.

The above tools could theoretically be used to compile, build, and bootstrap an entire FreeBSD, Linux, or other similar operating system kernel onto MMIX hardware, were such hardware to exist.

See also

Related Research Articles

MIPS is a family of reduced instruction set computer (RISC) instruction set architectures (ISA) developed by MIPS Computer Systems, now MIPS Technologies, based in the United States.

<span class="mw-page-title-main">Motorola 68000</span> Microprocessor

The Motorola 68000 is a 16/32-bit complex instruction set computer (CISC) microprocessor, introduced in 1979 by Motorola Semiconductor Products Sector.

<span class="mw-page-title-main">PDP-8</span> Minicomputer product line

The PDP-8 is a family of 12-bit minicomputers that was produced by Digital Equipment Corporation (DEC). It was the first commercially successful minicomputer, with over 50,000 units being sold over the model's lifetime. Its basic design follows the pioneering LINC but has a smaller instruction set, which is an expanded version of the PDP-5 instruction set. Similar machines from DEC are the PDP-12 which is a modernized version of the PDP-8 and LINC concepts, and the PDP-14 industrial controller system.

x86 Family of instruction set architectures

x86 is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel based on the 8086 microprocessor and its 8-bit-external-bus variant, the 8088. The 8086 was introduced in 1978 as a fully 16-bit extension of 8-bit Intel's 8080 microprocessor, with memory segmentation as a solution for addressing more memory than can be covered by a plain 16-bit address. The term "x86" came into being because the names of several successors to Intel's 8086 processor end in "86", including the 80186, 80286, 80386 and 80486. Colloquially, their names were "186", "286", "386" and "486".

<span class="mw-page-title-main">SPARC</span> RISC instruction set architecture

SPARC is a reduced instruction set computer (RISC) instruction set architecture originally developed by Sun Microsystems. Its design was strongly influenced by the experimental Berkeley RISC system developed in the early 1980s. First developed in 1986 and released in 1987, SPARC was one of the most successful early commercial RISC systems, and its success led to the introduction of similar RISC designs from many vendors through the 1980s and 1990s.

In computer science, threaded code is a programming technique where the code has a form that essentially consists entirely of calls to subroutines. It is often used in compilers, which may generate code in that form or be implemented in that form themselves. The code may be processed by an interpreter or it may simply be a sequence of machine code call instructions.

In computer science, an instruction set architecture (ISA) is an abstract model that generally defines how software controls the CPU in a computer or a family of computers. A device or program that executes instructions described by that ISA, such as a central processing unit (CPU), is called an implementation of that ISA.

MIX is a hypothetical computer used in Donald Knuth's monograph, The Art of Computer Programming (TAOCP). MIX's model number is 1009, which was derived by combining the model numbers and names of several contemporaneous, commercial machines deemed significant by the author. Also, "MIX" read as a Roman numeral is 1009.

x86 assembly language is the name for the family of assembly languages which provide some level of backward compatibility with CPUs back to the Intel 8008 microprocessor, which was launched in April 1972. It is used to produce object code for the x86 class of processors.

The DLX is a RISC processor architecture designed by John L. Hennessy and David A. Patterson, the principal designers of the Stanford MIPS and the Berkeley RISC designs (respectively), the two benchmark examples of RISC design.

In computer science, computer engineering and programming language implementations, a stack machine is a computer processor or a virtual machine in which the primary interaction is moving short-lived temporary values to and from a push down stack. In the case of a hardware processor, a hardware stack is used. The use of a stack significantly reduces the required number of processor registers. Stack machines extend push-down automata with additional load/store operations or multiple stacks and hence are Turing-complete.

Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how the machine language instructions in that architecture identify the operand(s) of each instruction. An addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere.

The TMS9900 was one of the first commercially available, single-chip 16-bit microprocessors. Introduced in June 1976, it implemented Texas Instruments' TI-990 minicomputer architecture in a single-chip format, and was initially used for low-end models of that lineup.

<span class="mw-page-title-main">Clipper architecture</span> 32-bit RISC-like computing architecture

The Clipper architecture is a 32-bit RISC-like instruction set architecture designed by Fairchild Semiconductor. The architecture never enjoyed much market success, and the only computer manufacturers to create major product lines using Clipper processors were Intergraph and High Level Hardware, although Opus Systems offered a product based on the Clipper as part of its Personal Mainframe range. The first processors using the Clipper architecture were designed and sold by Fairchild, but the division responsible for them was subsequently sold to Intergraph in 1987; Intergraph continued work on Clipper processors for use in its own systems.

The Atmel AVR instruction set is the machine language for the Atmel AVR, a modified Harvard architecture 8-bit RISC single chip microcontroller which was developed by Atmel in 1996. The AVR was one of the first microcontroller families to use on-chip flash memory for program storage.

In computer science, a calling convention is an implementation-level (low-level) scheme for how subroutines or functions receive parameters from their caller and how they return a result. When some code calls a function, design choices have been taken for where and how parameters are passed to that function, and where and how results are returned from that function, with these transfers typically done via certain registers or within a stack frame on the call stack. There are design choices for how the tasks of preparing for a function call and restoring the environment after the function has completed are divided between the caller and the callee. Some calling convention specifies the way every function should get called. The correct calling convention should be used for every function call, to allow the correct and reliable execution of the whole program using these functions.

Little Computer 3, or LC-3, is a type of computer educational programming language, an assembly language, which is a type of low-level programming language.

The PDP-11 architecture is a 16-bit CISC instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC). It is implemented by central processing units (CPUs) and microprocessors used in PDP-11 minicomputers. It was in wide use during the 1970s, but was eventually overshadowed by the more powerful VAX architecture in the 1980s.

<span class="mw-page-title-main">ST6 and ST7</span> 8-bit microcontroller product lines from STMicroelectronics

The ST6 and ST7 are 8-bit microcontroller product lines from STMicroelectronics. They are commonly used in small embedded applications like washing machines.

<span class="mw-page-title-main">WD16</span> Microprocessor produced by Western Digital

The WD16 is a 16-bit microprocessor introduced by Western Digital in October 1976. It is based on the MCP-1600 chipset, a general-purpose design that was also used to implement the DEC LSI-11 low-end minicomputer and the Pascal MicroEngine processor. The three systems differed primarily in their microcode, giving each system a unique instruction set architecture (ISA).

References

  1. 1 2 Knuth, Donald E. (October 1999), MMIXware: A RISC Computer for the Third Millennium, Lecture Notes in Computer Science Tutorial, vol. 1750, Heidelberg: Springer-Verlag, ISBN   3-540-66938-8 (Errata)
  2. ↑ "MMIX Home: A Message From Don Knuth". mmix.cs.hm.edu. Retrieved 2021-05-23.
  3. ↑ Knuth, Donald (1999-02-09). MMIX: A RISC Computer for the New Millennium (offset 7:36). Stanford Lecture. Archived from the original on 2021-12-11. (Cray-1 + IBM 801 + RISC II + Clipper C300 + AMD 29k + Motorola 88k + IBM 601 + Intel i960 + Alpha 21164 + POWER2 + MIPS R4000 + Hitachi Super H4 + StrongARM 110 + SPARC64) / 14 = 28126 / 14 = 2009
  4. 1 2 Knuth, Donald (2005). "Section 1.4.2'". MMIX—A RISC Computer for the New Millennium. The Art of Computer Programming. Vol. 1, Fasc. 1. Addison Wesley. p. 58.
  5. ↑ tommythorn. "fpgammix" . Retrieved 2024-09-27.
  6. ↑ "MMIXware". Cs-faculty.stanford.edu. Retrieved 2014-05-25.
  7. ↑ "MMIXX". Malgil.com. 2002-03-06. Retrieved 2014-05-25.
  8. ↑ Installation instructions for GCC + MMIX tools
  9. ↑ https://gcc.gnu.org/onlinedocs/gcc-7.2.0/gcc/MMIX-Options.html §3.17.26. MMIX
  10. ↑ "§9.28 MMIX Dependent Features". Sourceware.org. Retrieved 2017-11-20.

Further reading

This page is based on this Wikipedia article
Text is available under the CC BY-SA 4.0 license; additional terms may apply.
Images, videos and audio are available under their respective licenses.