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KL10-DA 1090 CPU and 6 Memory Modules PDP-10 1090.jpg
KL10-DA 1090 CPU and 6 Memory Modules
PDP-10 systems on the ARPANET highlighted in yellow Arpanet logical map, march 1977 PDP-10.png
PDP-10 systems on the ARPANET highlighted in yellow
Working DEC KI-10 System at Living Computers: Museum + Labs DECSystem10-KI10.JPG
Working DEC KI-10 System at Living Computers: Museum + Labs

Digital Equipment Corporation's PDP-10, later marketed as the DECsystem-10, was a mainframe computer family [1] manufactured beginning in 1966; [2] it was discontinued in 1983. [3] [4] [5] 1970s models and beyond were marketed under the DECsystem-10 name, especially as the TOPS-10 operating system became widely used. [6]

Digital Equipment Corporation (DEC), using the trademark Digital, was a major American company in the computer industry from the 1950s to the 1990s.

TOPS-10 System is a discontinued operating system from Digital Equipment Corporation (DEC) for the PDP-10 mainframe computer family. Launched in 1967, TOPS-10 evolved from the earlier "Monitor" software for the PDP-6 and PDP-10 computers; this was renamed to TOPS-10 in 1970.


The PDP-10's architecture is almost identical to that of DEC's earlier PDP-6, sharing the same 36-bit word length and slightly extending the instruction set (but with improved hardware implementation). Some aspects of the instruction set are unusual, most notably the byte instructions, which operated on bit fields of any size from 1 to 36 bits inclusive, according to the general definition of a byte as a contiguous sequence of a fixed number of bits.


The PDP-6 was a computer model developed by Digital Equipment Corporation (DEC) in 1964. It was influential primarily as the prototype (effectively) for the later PDP-10; the instruction sets of the two machines are almost identical.


In computer architecture, 36-bit integers, memory addresses, or other data units are those that are 36 bits wide. Also, 36-bit CPU and ALU architectures are those that are based on registers, address buses, or data buses of that size.

In computing, a word is the natural unit of data used by a particular processor design. A word is a fixed-sized piece of data handled as a unit by the instruction set or the hardware of the processor. The number of bits in a word is an important characteristic of any specific processor design or computer architecture.

The PDP-10 is the machine that made time-sharing common, and this and other features made it a common fixture in many university computing facilities and research labs during the 1970s, the most notable being Harvard University's Aiken Lab, [7] MIT's AI Lab and Project MAC, Stanford's SAIL, Computer Center Corporation (CCC), ETH (ZIR), and Carnegie Mellon University. Its main operating systems, TOPS-10 and TENEX, were used to build out the early ARPANET. For these reasons, the PDP-10 looms large in early hacker folklore.

In computing, time-sharing is the sharing of a computing resource among many users by means of multiprogramming and multi-tasking at the same time.

Harvard University Private research university in Cambridge, Massachusetts, United States

Harvard University is a private Ivy League research university in Cambridge, Massachusetts, with about 6,700 undergraduate students and about 15,250 postgraduate students. Established in 1636 and named for its first benefactor, clergyman John Harvard, Harvard is the United States' oldest institution of higher learning. Its history, influence, and wealth have made it one of the world's most prestigious universities. The university is often cited as the world's top tertiary institution by most publishers.

Massachusetts Institute of Technology University in Massachusetts

The Massachusetts Institute of Technology (MIT) is a private research university in Cambridge, Massachusetts. The Institute is a land-grant, sea-grant, and space-grant university, with an urban campus that extends more than a mile alongside the Charles River. Founded in 1861 in response to the increasing industrialization of the United States, MIT adopted a European polytechnic university model and stressed laboratory instruction in applied science and engineering. It has since played a key role in the development of many aspects of modern science, engineering, mathematics, and technology, and is widely known for its innovation and academic strength, making it one of the most prestigious institutions of higher learning in the world.

Projects to extend the PDP-10 line were eclipsed by the success of the unrelated VAX superminicomputer, and the cancellation of the PDP-10 line was announced in 1983.

VAX Computer architecture, and a range of computers

VAX is a discontinued instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC) in the mid-1970s. The VAX-11/780, introduced on October 25, 1977, was the first of a range of popular and influential computers implementing that architecture.

A superminicomputer, or supermini, was “a minicomputer with high performance compared to ordinary minicomputers.” The term was an invention used from the mid-1970s mainly to distinguish the emerging 32-bit minis from the classical 16-bit minicomputers. The term is now largely obsolete but still remains of interest for students/researchers of computer history.

Models and technical evolution

Flip Chip from a DEC KA10, containing 9 transistors, 1971 KA10 mod end.jpg
Flip Chip from a DEC KA10, containing 9 transistors, 1971
Quick Latch Memory Bus Terminator, used on KI10, 1973 DEC-10 Memory Bus Terminator H866 top view.jpg
Quick Latch Memory Bus Terminator, used on KI10, 1973
KL10 Wire-Wrap CPU Backplane KL10-backplane.jpg
KL10 Wire-Wrap CPU Backplane

The original PDP-10 processor is the KA10, introduced in 1968 [8] . It uses discrete transistors packaged in DEC's Flip-Chip technology, with backplanes wire wrapped via a semi-automated manufacturing process. Its cycle time is 1 μs and its add time 2.1 μs. [9] [ full citation needed ] In 1973, the KA10 was replaced by the KI10, which uses transistor–transistor logic (TTL) SSI. This was joined in 1975 by the higher-performance KL10 (later faster variants), which is built from emitter-coupled logic (ECL), microprogrammed, and has cache memory. The KL10's performance was about 1 megaflops using 36-bit floating point numbers on matrix row reduction. It was slightly faster than the newer VAX-11/750, although more limited in memory.

Transistor semiconductor device used to amplify and switch electronic signals and electrical power

A transistor is a semiconductor device used to amplify or switch electronic signals and electrical power. It is composed of semiconductor material usually with at least three terminals for connection to an external circuit. A voltage or current applied to one pair of the transistor's terminals controls the current through another pair of terminals. Because the controlled (output) power can be higher than the controlling (input) power, a transistor can amplify a signal. Today, some transistors are packaged individually, but many more are found embedded in integrated circuits.

Wire wrap

Wire wrap was invented to wire telephone crossbar switches, and later adapted to construct electronic circuit boards. Electronic components mounted on an insulating board are interconnected by lengths of insulated wire run between their terminals, with the connections made by wrapping several turns of uninsulated sections of the wire around a component lead or a socket pin.

Magnetic-core memory predominant form of random-access computer memory for 20 years between about 1955 and 1975

Magnetic-core memory was the predominant form of random-access computer memory for 20 years between about 1955 and 1975. Such memory is often just called core memory, or, informally, core.

A smaller, less expensive model, the KS10, was introduced in 1978, using TTL and Am2901 bit-slice components and including the PDP-11 Unibus to connect peripherals. The KS was marketed as the DECsystem-2020, DEC's entry in the distributed processing arena, and it was introduced as "the world's lowest cost mainframe computer system." [10]

AMD Am2900

Am2900 is a family of integrated circuits (ICs) created in 1975 by Advanced Micro Devices (AMD). They were constructed with bipolar devices, in a bit-slice topology, and were designed to be used as modular components each representing a different aspect of a computer control unit (CCU). By using the bit slicing technique, Am2900 family was able to implement a CCU with data, addresses, and instructions to be any multiple of 4 bits by multiplying the number of ICs. One major problem with this modular technique was that it required a larger number of ICs to implement what could be done on a single CPU IC. The Am2901 chip was the arithmetic-logic unit (ALU), and the "core" of the series. It could count using 4 bits and implement binary operations as well as various bit-shifting operations.

PDP-11 Series of 16-bit minicomputers

The PDP-11 is a series of 16-bit minicomputers sold by Digital Equipment Corporation (DEC) from 1970 into the 1990s, one of a succession of products in the PDP series. In total, around 600,000 PDP-11s of all models were sold, making it one of DEC's most successful product lines. The PDP-11 is considered by some experts to be the most popular minicomputer ever.


The Unibus was the earliest of several computer bus and backplane designs used with PDP-11 and early VAX systems manufactured by the Digital Equipment Corporation (DEC) of Maynard, Massachusetts. The Unibus was developed around 1969 by Gordon Bell and student Harold McFarland while at Carnegie Mellon University.


The KA10 has a maximum main memory capacity (both virtual and physical) of 256 kilowords (equivalent to 1152 kilobytes). As supplied by DEC, it did not include paging hardware; memory management consisted of two sets of protection and relocation registers, called base and bounds registers. This allows each half of a user's address space to be limited to a set section of main memory, designated by the base physical address and size. This allows the model of separate read-only shareable code segment (normally the high segment) and read-write data/stack segment (normally the low segment) used by TOPS-10 and later adopted by Unix. Some KA10 machines, first at MIT, and later at Bolt, Beranek and Newman (BBN), were modified to add virtual memory [11] and support for demand paging, [12] [13] and more physical memory.

KA10 weighed about 1,920 pounds (870 kg). [14]

The 10/50 was the top-of-the-line Uni-processor KA machine [15] at the time when the PA1050 software package was introduced. Two other KA10 models were the uniprocessor 10/40, and the dual-processor 10/55. [16] [17]

KI10 and KL10

The KI10 and later processors offer paged memory management, and also support a larger physical address space of 4 megawords. KI10 models include 1060, 1070 and 1077, the latter incorporating two CPUs.

KS10 KS10-open.jpg

The original KL10 PDP-10 (also marketed as DECsystem-10) models (1080, 1088, etc.) use the original PDP-10 memory bus, with external memory modules. Module in this context meant a cabinet, dimensions roughly (WxHxD) 30 x 75 x 30 in. with a capacity of 32 to 256 kWords of magnetic core memory (the picture on the right hand side of the introduction shows six of these cabinets). The processors used in the DECSYSTEM-20 (2040, 2050, 2060, 2065), commonly but incorrectly called "KL20", use internal memory, mounted in the same cabinet as the CPU. The 10xx models also have different packaging; they come in the original tall PDP-10 cabinets, rather than the short ones used later on for the DECSYSTEM-20. The differences between the 10xx and 20xx models are more cosmetic than real; some 10xx systems have "20-style" internal memory and I/O, and some 20xx systems have "10-style" external memory and an I/O bus. In particular, all ARPAnet TOPS-20 systems had an I/O bus because the AN20 IMP interface was an I/O bus device. Both could run either TOPS-10 or TOPS-20 microcode and thus the corresponding operating system.

Model B

Later, the "Model B" version of the 2060 processors removed the 256 kilo word limit on the virtual address space, by allowing the use of up to 32 "sections" of up to 256 kilowords each, along with substantial changes to the instruction set. "Model A" and "Model B" KL10 processors can be thought of as being different CPUs. The first operating system that took advantage of the Model B's capabilities was TOPS-20 release 3, and user mode extended addressing was offered in TOPS-20 release 4. TOPS-20 versions after release 4.1 would only run on a Model B.

TOPS-10 versions 7.02 and 7.03 also use extended addressing when run on a 1090 (or 1091) Model B processor running TOPS-20 microcode.


The final upgrade to the KL10 was the MCA25 upgrade of a 2060 to 2065 (or a 1091 to 1095), which gave some performance increases for programs which run in multiple sections.


The KS10 design was crippled to be a Model A even though most of the necessary data paths needed to support the Model B architecture were present. This was no doubt intended to segment the market, but it greatly shortened the KS10's product life.

Frontend systems

KL10 frontend PDP-11/40 KL10-front-end.jpg
KL10 frontend PDP-11/40

Frontend processors are computers that extend the functionality of the systems to which they are connected. [18]

KL frontends

The KL class machines cannot be started without the assistance of a PDP-11/40 frontend computer installed in every system. The PDP-11 is booted from a dual-ported RP06 disk drive (or alternatively from an 8" floppy disk drive or DECtape), and then commands can be given to the PDP-11 to start the main processor, which is typically booted from the same RP06 disk drive as the PDP-11. The PDP-11 performs watchdog functions once the main processor is running.

Networking [19] and Remote Job Entry (RJE) were accomplished via a PDP-11/34a frontend, for which was DEC used the terms DN60 and D60SPL [20]

KS frontends

The KS system uses a similar boot procedure. An 8080 CPU loads the microcode from an RM03, RM80, or RP06 disk or magnetic tape and then starts the main processor. The 8080 switches modes after the operating system boots and controls the console and remote diagnostic serial ports.


The I/O architecture of the 20xx series KL machines is based on a DEC bus design called the MASSbus. While many attributed the success of the PDP-11 to DEC's decision to make the PDP-11 Unibus an open architecture, DEC reverted to prior philosophy with the KL, making MASSbus both unique and proprietary. Consequently, there were no aftermarket peripheral manufacturers who made devices for the MASSbus, and DEC chose to price their own MASSbus devices, notably the RP06 disk drive, at a substantial premium above comparable IBM-compatible devices. CompuServe for one, designed its own alternative disk controller that could operate on the MASSbus, but connect to IBM style 3330 disk subsystems.

Magnetic tape drives

Two models of tape drives were supported by the TM10 Magnetic Tape Control subsystem:

A mix of up to eight of these could be supported, providing seven-track &/or nine-track devices. The TU20 and TU30 each came in A (9 track) and B (7 track) versions, and all of the aforementioned tape drives could read/write from/to 200 BPI, 556 BPI and 800 BPI IBM-compatible tapes.

The TM10 Magtape controller was available in two submodels:

Instruction set architecture

DEC PDP-10 registers
00. . .1718. . .35(bit position)
General registers
Register 0
 AC1Register 1
 AC2Register 2
 AC3Register 3
 AC4Register 4
 AC5Register 5
 AC6Register 6
 AC7Register 7
 AC10Register 8
 AC11Register 9
 AC12Register 10
 AC13Register 11
 AC14Register 12
 AC15Register 13
 AC16Register 14
 AC17Register 15
Program counter and status flags
Program Flags00000PCProgram Counter

Note that the bit numbering order is different from some other DEC processors, and many newer processors.

From the first PDP-6s to the Model A KL-10s, the user-mode instruction set architecture is largely the same. This section covers that architecture. (Multi-section extended addressing is covered in the DECsystem-10/DECSYSTEM-20 Processor Reference Manual.) [22]


The PDP-10 has 36-bit words and 18-bit word addresses. In supervisor mode, instruction addresses correspond directly to physical memory. In user mode, addresses are translated to physical memory. Earlier models give a user process a "high" and a "low" memory: addresses with a 0 top bit used one base register, and higher addresses used another. Each segment is contiguous. Later architectures have paged memory access, allowing non-contiguous address spaces. The CPU's general-purpose registers can also be addressed as memory locations 0-15.


There are 16 general-purpose, 36-bit registers. The right half of these registers (other than register 0) may be used for indexing. A few instructions operate on pairs of registers. The "PC Word" consists of a 13-bit condition register (plus 5 always zero bits) in the left half and an 18-bit Program Counter in the right half. The condition register, which records extra bits from the results of arithmetic operations (e.g. overflow), can be accessed by only a few instructions.

Supervisor mode

There are two operational modes, supervisor and user mode. Besides the difference in memory referencing described above, supervisor-mode programs can execute input/output operations.

Communication from user-mode to supervisor-mode is done through Unimplemented User Operations (UUOs): instructions which are not defined by the hardware, and are trapped by the supervisor. This mechanism is also used to emulate operations which may not have hardware implementations in cheaper models.

Data types

The major datatypes which are directly supported by the architecture are two's complement 36-bit integer arithmetic (including bitwise operations), 36-bit floating-point, and halfwords. Extended, 72-bit, floating point is supported through special instructions designed to be used in multi-instruction sequences. Byte pointers are supported by special instructions. A word structured as a "count" half and a "pointer" half facilitates the use of bounded regions of memory, notably stacks.


The instruction set is very symmetrical. Every instruction consists of a 9-bit opcode, a 4-bit register code, and a 23-bit effective address field, which consists in turn of a 1-bit indirect bit, a 4-bit register code, and an 18-bit offset. Instruction execution begins by calculating the effective address. It adds the contents of the given register (if non-zero) to the offset; then, if the indirect bit is 1, fetches the word at the calculated address and repeats the effective address calculation until an effective address with a zero indirect bit is reached. The resulting effective address can be used by the instruction either to fetch memory contents, or simply as a constant. Thus, for example, MOVEI A,3(C) adds 3 to the 18 lower bits of register C and puts the result in register A, without touching memory.

There are three main classes of instruction: arithmetic, logical, and move; conditional jump; conditional skip (which may have side effects). There are also several smaller classes.

The arithmetic, logical, and move operations include variants which operate immediate-to-register, memory-to-register, register-to-memory, register-and-memory-to-both or memory-to-memory. Since registers may be addressed as part of memory, register-to-register operations are also defined. (Not all variants are useful, though they are well-defined.) For example, the ADD operation has as variants ADDI (add an 18-bit Immediate constant to a register), ADDM (add register contents to a Memory location), ADDB (add to Both, that is, add register contents to memory and also put the result in the register). A more elaborate example is HLROM (Half Left to Right, Ones to Memory), which takes the Left half of the register contents, places them in the Right half of the memory location, and replaces the left half of the memory location with Ones. Halfword instructions are also used for linked lists: HLRZ is the Lisp CAR operator; HRRZ is CDR.

The conditional jump operations examine register contents and jump to a given location depending on the result of the comparison. The mnemonics for these instructions all start with JUMP, JUMPA meaning "jump always" and JUMP meaning "jump never" – as a consequence of the symmetric design of the instruction set, it contains several no-ops such as JUMP. For example, JUMPN A,LOC jumps to the address LOC if the contents of register A is non-zero. There are also conditional jumps based on the processor's condition register using the JRST instruction. On the KA10 and KI10, JRST is faster than JUMPA, so the standard unconditional jump is JRST.

The conditional skip operations compare register and memory contents and skip the next instruction (which is often an unconditional jump) depending on the result of the comparison. A simple example is CAMN A,LOC which compares the contents of register A with the contents of location LOC and skips the next instruction if they are not equal. A more elaborate example is TLCE A,LOC (read "Test Left Complement, skip if Equal"), which using the contents of LOC as a mask, selects the corresponding bits in the left half of register A. If all those bits are Equal to zero, skip the next instruction; and in any case, replace those bits by their boolean complement.

Some smaller instruction classes include the shift/rotate instructions and the procedure call instructions. Particularly notable are the stack instructions PUSH and POP, and the corresponding stack call instructions PUSHJ and POPJ. The byte instructions use a special format of indirect word to extract and store arbitrary-sized bit fields, possibly advancing a pointer to the next unit.


The original PDP-10 operating system was simply called "Monitor", but was later renamed TOPS-10. Eventually the PDP-10 system itself was renamed the DECsystem-10. Early versions of Monitor and TOPS-10 formed the basis of Stanford's WAITS operating system and the CompuServe time-sharing system.

Over time, some PDP-10 operators began running operating systems assembled from major components developed outside DEC. For example, the main Scheduler might come from one university, the Disk Service from another, and so on. The commercial timesharing services such as CompuServe, On-Line Systems (OLS), and Rapidata maintained sophisticated inhouse systems programming groups so that they could modify the operating system as needed for their own businesses without being dependent on DEC or others. There are also strong user communities such as DECUS through which users can share software that they have developed.

BBN developed their own alternative operating system, TENEX, which fairly quickly became the de facto standard in the research community. DEC later ported TENEX to the KL10, enhanced it considerably, and named it TOPS-20, forming the DECSYSTEM-20 line.

MIT, which had developed CTSS, Compatible Time-Sharing System to run on their IBM 709 (and later a modified IBM 7094 system), also developed ITS, Incompatible Timesharing System [23] to run on their PDP-6 (and later a modified PDP-10); [24] the naming was related, since the IBM and the DEC/PDP hardware were different, i.e. "incompatible" (despite each having a 36-bit CPU).

The ITS name, selected by Tom Knight, "was a play on" the CTSS name. [25]

Tymshare developed TYMCOM-X, [26] derived from TOPS-10 but using a page-based file system like TOPS-20. [27]


In 1971 to 1972, researchers at Xerox PARC were frustrated by top company management's refusal to let them buy a PDP-10. Xerox had just bought Scientific Data Systems (SDS) in 1969, and wanted PARC to use an SDS machine. Instead, a group led by Charles P. Thacker designed and constructed two PDP-10 clone systems named MAXC (pronounced as Max, in honour of Max Palevsky, who had sold SDS to Xerox) for their own use. MAXC was also a backronym for Multiple Access Xerox Computer. MAXC ran a modified version of TENEX. [28]

Third-party attempts to sell PDP-10 clones were relatively unsuccessful; see Foonly, Systems Concepts, and XKL.

Use by CompuServe

One of the largest collections of DECsystem-10 architecture systems ever assembled was at CompuServe, which, at its peak, operated over 200 loosely coupled systems in three data centers in Columbus, Ohio. CompuServe used these systems as 'hosts', providing access to commercial applications, and the CompuServe Information Service. While the first such systems were bought from DEC, when DEC abandoned the PDP-10 architecture in favor of the VAX, CompuServe and other PDP-10 customers began buying plug compatible computers from Systems Concepts. As of January 2007, CompuServe was operating a small number of PDP-10 architecture machines to perform some billing and routing functions.

The main power supplies used in the KL-series machines were so inefficient that CompuServe engineers designed a replacement supply that used about half the energy. CompuServe offered to license the design for its KL supply to DEC for free if DEC would promise that any new KL bought by CompuServe would have the more efficient supply installed. DEC declined the offer.

MF10 Light Panel with LED lamps MF10-Panel.jpg
MF10 Light Panel with LED lamps

Another modification made to the PDP-10 by CompuServe engineers was replacing the hundreds of incandescent indicator lamps on the KI10 processor cabinet with LED lamp modules. The cost of conversion was easily offset by cost savings in electricity use, reduced heat, and labor needed to replace burned-out lamps. Digital followed this step all over the world. The picture on the right hand side shows the light panel of the MF10 memory which is contemporary with the KI10 CPU. This item is part of a computer museum, and was populated with LEDs in 2008 for demonstration purposes only. There were no similar banks of indicator lamps on KL and KS processors.

Cancellation and influence

The PDP-10 was eventually eclipsed by the VAX superminicomputer machines (descendants of the PDP-11) when DEC recognized that the PDP-10 and VAX product lines were competing with each other and decided to concentrate its software development effort on the more profitable VAX. The PDP-10 product line cancellation was announced in 1983, including cancelling the ongoing Jupiter project to produce a new high-end PDP-10 processor (despite that project being in good shape at the time of the cancellation) and the Minnow project to produce a desktop PDP-10, which may then have been at the prototyping stage. [29]

This event spelled the doom of ITS and the technical cultures that had spawned the original jargon file, but by the 1990s it had become something of a badge of honor among old-time hackers to have cut one's teeth on a PDP-10.

The PDP-10 assembly language instructions LDB and DPB (load/deposit byte) live on as functions in the programming language Common Lisp. See the "References" section on the LISP article. The 36-bit word size of the PDP-6 and PDP-10 was influenced by the programming convenience of having 2 LISP pointers, each 18 bits, in one word.

Will Crowther created Adventure , the prototypical computer adventure game, for a PDP-10. Don Daglow created the first computer baseball game (1971) and Dungeon (1975), the first role-playing video game on a PDP-10. Walter Bright originally created Empire for the PDP-10. Roy Trubshaw and Richard Bartle created the first MUD on a PDP-10. Zork was written on the PDP-10. Infocom used PDP-10s for game development and testing. [30]

Bill Gates and Paul Allen originally wrote Altair BASIC using an Intel 8080 emulator running on a PDP-10 at Harvard University. They founded Microsoft shortly after.

Emulation or simulation

The software for simulation of historical computers SIMH contains a module to emulate the KS10 CPU on a Windows or Unix-based machine. Copies of DEC's original distribution tapes are available as downloads from the Internet so that a running TOPS-10 or TOPS-20 system may be established. ITS is also available for SIMH.

Ken Harrenstien's KLH10 software for Unix-like systems emulates a KL10B processor with extended addressing and 4 MW of memory or a KS10 processor with 512 KW of memory. The KL10 emulation supports v.442 of the KL10 microcode, which enables it to run the final versions of both TOPS-10 and TOPS-20. The KS10 emulation supports both ITS v.262 microcode for the final version of KS10 ITS and DEC v.130 microcode for the final versions of KS TOPS-10 and TOPS-20. [31]

This article is based in part on the Jargon File, which is in the public domain.

See also

Related Research Articles

A control store is the part of a CPU's control unit that stores the CPU's microprogram. It is usually accessed by a microsequencer. Early types of control store took the form of diode-arrays that were accessed via address decoders, but were later implemented as writable microcode that was stored in a form of read-only memory called a writable control store. The outputs generally had to go through a register to prevent a race condition from occurring. The register was clocked by the clock signal of the system it was running on.

Systems Concepts is a company co-founded by Stewart Nelson and Mike Levitt focused on making hardware products related to the DEC PDP-10 series of computers. One of its major products was the SA-10, an interface which allowed PDP-10s to be connected to disk and tape drives designed for use with the channel interfaces of IBM mainframes.

Microcode is a computer hardware technique that imposes an interpreter between the CPU hardware and the programmer-visible instruction set architecture of the computer. As such, the microcode is a layer of hardware-level instructions that implement higher-level machine code instructions or internal state machine sequencing in many digital processing elements. Microcode is used in general-purpose central processing units, although in current desktop CPUs it is only a fallback path for cases that the faster hardwired control unit cannot handle.


The DECSYSTEM-20 was a 36-bit Digital Equipment Corporation PDP-10 mainframe computer running the TOPS-20 operating system.

Programmed Data Processor Name used for several lines of minicomputers

Programmed Data Processor (PDP), referred to by some customers, media and authors as "Programmable Data Processor, is a term used by the Digital Equipment Corporation from 1957 to 1990 for several lines of minicomputers. The name "PDP" intentionally avoids the use of the term "computer" because, at the time of the first PDPs, computers had a reputation of being large, complicated, and expensive machines, and the venture capitalists behind Digital would not support Digital's attempting to build a "computer"; the word "minicomputer" had not yet been coined. So instead, Digital used their existing line of logic modules to build a Programmed Data Processor and aimed it at a market that could not afford the larger computers.

PDP-8 First commercially successful minicomputer

The PDP-8 is a 12-bit minicomputer that was produced by Digital Equipment Corporation (DEC). It was the first commercially successful minicomputer, with over 50,000 examples being sold over the model's lifetime. Its basic design follows the pioneering LINC but has a smaller instruction set, which is an expanded version of the PDP-5 instruction set. Similar machines from DEC are the PDP-12 which is a modernized version of the PDP-8 and LINC concepts, and the PDP-14 industrial controller system.

TOPS-20 operating system by Digital Equipment Corporation

The TOPS-20 operating system by Digital Equipment Corporation (DEC) was a proprietary OS used on some of DEC's 36-bit mainframe computers. The Hardware Reference Manual was described as for "DECsystem-10/DECSYSTEM-20 Processor".

HP 2100 mini computer series by HP

The HP 2100 was a series of 16-bit minicomputers produced by Hewlett-Packard (HP) from the mid-1960s to early 1990s. Tens of thousands of machines in the series were sold over its twenty-five year lifetime, making HP the fourth largest minicomputer vendor during the 1970s.

The CDC Cyber range of mainframe-class supercomputers were the primary products of Control Data Corporation (CDC) during the 1970s and 1980s. In their day, they were the computer architecture of choice for scientific and mathematically intensive computing. They were used for modeling fluid flow, material science stress analysis, electrochemical machining analysis, probabilistic analysis, energy and academic computing, radiation shielding modeling, and other applications. The lineup also included the Cyber 18 and Cyber 1000 minicomputers. Like their predecessor, the CDC 6600, they were unusual in using the ones' complement binary representation.

Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how machine language instructions in that architecture identify the operand(s) of each instruction. An addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere.


The C.mmp was an early MIMD multiprocessor system developed at Carnegie Mellon University by William Wulf (1971). The notation C.mmp came from the PMS notation of Bell and Newell, where a CPU was designated as C and a variant was noted by the dot notation; mmp stood for Multi-Mini-Processor

The Nord-100 was a 16-bit minicomputer series made by Norsk Data, introduced in 1979. It shipped with the Sintran III operating system, and the architecture was based on, and backwards compatible with, the Nord-10 line.

The Massbus is a high-performance computer input/output bus designed in the 1970s by the Digital Equipment Corporation of Maynard, Massachusetts.

The PDP-11 architecture is an instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC). It is implemented by central processing units (CPUs) and microprocessors used in PDP-11 minicomputers. It was in wide use during the 1970s, but was eventually overshadowed by the more powerful VAX-11 architecture in the 1980s.

In computer architecture, 16-bit integers, memory addresses, or other data units are those that are 16 bits wide. Also, 16-bit CPU and ALU architectures are those that are based on registers, address buses, or data buses of that size. 16-bit microcomputers are computers in which 16-bit microprocessors were the norm.

TENEX was an operating system developed in 1969 by BBN for the PDP-10, which later formed the basis for Digital Equipment Corporation's TOPS-20 operating system.


  1. Ceruzzi, p. 208, "It was largeeven DEC's own literature called [the PDP-10] a mainframe."
  2. Ceruzzi, p. 139
  3. "PDP-10 was discontinued in 1983, but PDP-11 wasn't discontinued until 1997". ... with third-parties continuing to sell parts, so it's really not that ...
  4. "What does pdp-10 mean?". definitions.net. The PDP-10 was a mainframe computer family manufactured ... the cancellation of the PDP-10 line was announced in 1983.
  5. Stallman, Richard; Gay, Joshua (2002). Free Software, Free Society: Selected Essays of Richard M. Stallman. ISBN   1882114981. Not long afterwards, Digital discontinued the PDP-10 series.
  6. The TOPS-10 name was announced 1970
  7. https://www.seas.harvard.edu/about-seas/map-directions/buildings identifies Maxwell Dworkin Laborary, located at 33 Oxford Street, as having been named after the mothers of Microsoft's Bill Gates (Maxwell) and Steve Balmer (Dworkin), with the word Laboratory added "in recognition of the former Aiken Lab."
  8. "PDP10 manual" (PDF). Dec 1968.
  9. Digital Equipment Corporation, The digital small computer handbook, p. 376
  10. "DECsystem-2020 – Gordon Bell".
  11. McNamee, L. P. (1976). "A Virtual Memory System for the PDP-10 KA10 Processor".
  12. Bobrow, D. G. (September 8, 1971). "TENEX, a Paged Time Sharing System for the PDP-10" (PDF). PDP-10 processor augmented by special paging hardware
  13. "DECsystem-10/DECSYSTEM-20 Processor Reference Manual" (PDF). June 1, 1982. DECsystem-10 ... dynamic paging and working set management
  14. "PDP-10 KA10 documents". www.bitsavers.org. PDP-10_InstallationMan.pdf, p. 5.
  15. Murphy, Dan (1989). "Origins and Development of TOPS-20".
  16. "PDP-10 models". June 30, 2001. PDP 1055 Dual processor (1050) system ... early DEC-10 monitors
  17. also marketed as 1040, 1050, 1055, as per the KI/KL models as 1060, 1070, etc.
  18. see https://www.pcmag.com/encyclopedia/term/43514/front-end-processor
  19. http://www.inwap.com/pdp10/usenet/decnet
  20. The spooler was named D60SPL; see http://pdp-10.trailing-edge.com/bb-d868b-bm_tops20_v3a_2020_dist/01/3a-sources/d60spl.mac.html (The name D60SPL came from LPTSPL)
  21. "DEC 10 KA10 SitePrep" (PDF). Digital Equipment Corporation. May 1970.
  22. "DECsystem-1O/DECSYSTEM-20 Processor Reference Manual AD-H391 A-T1" (PDF). DEC. Archived from the original (PDF) on 11 October 2015. Retrieved 14 November 2015.
  23. "A Brief History of Hackerdom: The Early Hackers". MIT ... built their own operating system, the fabled .. Incompatible Timesharing System
  24. "Incompatible Timesharing System". gunkies.org (Computer History Wiki). Incompatible Timesharing System ... ITS ... time-sharing operating system; initially for the PDP-6, and later for PDP-10's
  25. Chiou, S. (2001). "The Founding of the MIT AI Lab" (PDF).
  26. "Tymnet operations formed a strategic alliance with the Tymshare PDP-10 TYMCOM-X operating systems group to assist them in developing new network management tools."
  27. "TYMCOM-X". Gunkies.org (Computer History Wiki).
  28. Kossow, Al (interviewer) (August 29, 2007). "Oral History of Charles (Chuck) Thacker" (PDF). Reference no: X4148.2008. Computer History Museum. Archived from the original (PDF) on August 11, 2011. Retrieved April 20, 2011.
  29. "DEC 36-bit Computers" Retrieved on April 4, 2009. Archived December 16, 2009, at the Wayback Machine
  30. "Zork on the PDP-10". Infocom would develop Zork .. PDP-10 .. hosted .. Incompatible Timesharing System ... ARPANET ... DMG’s machine ... community .. a sort of extended beta-testing team
  31. Tim Shoppa "Announcing KLH10", November 10, 2001. Retrieved April 4, 2009.

Further reading